Linaro-uefi November 2016

linaro-uefi@lists.linaro.org

22 participants
39 discussions

[PATCH v2] Platforms/ARM: fix gtdt.asl for VExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- Changelog: v2: Fix a inappropriate definition: GTDT_TIMER_SECURE --> GTDT_TIMER_SAVE_CONTEXT v1: The first upstreaming version: https://lists.linaro.org/pipermail/linaro-uefi/2016-July/002230.html Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc | 128 ++++++++++++++++++++++------ 1 file changed, 101 insertions(+), 27 deletions(-) diff --git a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc index 142249f..fc8f91f 100644 --- a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc +++ b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc @@ -19,21 +19,70 @@ #include <Library/PcdLib.h> #include <IndustryStandard/Acpi61.h> -#define SECURE_TIMER_EL1_GSIV 0x1D -#define NON_SECURE_TIMER_EL1_GSIV 0x1E -#define VIRTUAL_TIMER_GSIV 0x1B -#define NON_SECURE_EL2_GSIV 0x1A +#define FVP_SYSTEM_TIMER_BASE_ADDRESS 0x000000002a430000 +#define FVP_CNT_READ_BASE_ADDRESS 0x000000002a800000 -#define GT_BLOCK_CTL_BASE 0x000000002A810000 -#define GT_BLOCK_FRAME1_CTL_BASE 0x000000002A820000 -#define GT_BLOCK_FRAME1_GSIV 0x29 +#define FVP_SECURE_TIMER_EL1_GSIV 0x1D +#define FVP_NON_SECURE_TIMER_EL1_GSIV 0x1E +#define FVP_VIRTUAL_TIMER_GSIV 0x1B +#define FVP_NON_SECURE_EL2_GSIV 0x1A + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SAVE_CONTEXT EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_LOSE_CONTEXT 0 + +#define FVP_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_EDGE_TRIGGERED) + +#define FVP_PLATFORM_TIMER_COUNT 2 +#define FVP_TIMER_FRAMES_COUNT 2 +#define FVP_WATCHDOG_COUNT 1 + +#define FVP_GT_BLOCK_CTL_BASE 0x000000002A810000 +#define FVP_GT_BLOCK_FRAME0_CTL_BASE 0x000000002A820000 +#define FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define FVP_GT_BLOCK_FRAME0_GSIV 0x39 + +#define FVP_GT_BLOCK_FRAME1_CTL_BASE 0x000000002A830000 +#define FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define FVP_GT_BLOCK_FRAME1_GSIV 0x3A + +#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 + +#define FVP_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 + +#define FVP_GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_SECURE) + +#define FVP_SBSA_WATCHDOG_REFRESH_BASE 0x000000002a450000 +#define FVP_SBSA_WATCHDOG_CONTROL_BASE 0x000000002a440000 +#define FVP_SBSA_WATCHDOG_GSIV 0x3B + +#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 + +#define FVP_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED) #pragma pack (1) typedef struct { EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock; - EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[1]; + EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[FVP_TIMER_FRAMES_COUNT]; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[FVP_WATCHDOG_COUNT]; } FVP_GENERIC_TIMER_DESCRIPTION_TABLES; #pragma pack () @@ -45,27 +94,28 @@ FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { FVP_GENERIC_TIMER_DESCRIPTION_TABLES, EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), - 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress + FVP_SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress EFI_ACPI_RESERVED_DWORD, // UINT32 Reserved - SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 SecurePL1TimerFlags - NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 NonSecurePL1TimerFlags - VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 VirtualTimerFlags - NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 NonSecurePL2TimerFlags - 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress - 1, // UINT32 PlatformTimerCount + FVP_SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FVP_NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FVP_VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FVP_NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + FVP_CNT_READ_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress + FVP_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { EFI_ACPI_6_1_GTDT_GT_BLOCK, // UINT8 Type sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT16 Length - + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), + + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE) * + FVP_TIMER_FRAMES_COUNT, EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved - GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase - 1, // UINT32 GTBlockTimerCount + FVP_GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase + FVP_TIMER_FRAMES_COUNT, // UINT32 GTBlockTimerCount sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset }, { @@ -74,13 +124,37 @@ FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3] - GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX - 0xFFFFFFFFFFFFFFFF, // UINT64 CntEL0BaseX - GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV - 0, // UINT32 GTxPhysicalTimerFlags + FVP_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 CntBaseX + FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 CntEL0BaseX + FVP_GT_BLOCK_FRAME0_GSIV, // UINT32 GTxPhysicalTimerGSIV + FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags 0, // UINT32 GTxVirtualTimerGSIV 0, // UINT32 GTxVirtualTimerFlags - 0 // UINT32 GTxCommonFlags + FVP_GTX_COMMON_FLAGS // UINT32 GTxCommonFlags + }, + { + 1, // UINT8 GTFrameNumber + {EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3] + FVP_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX + FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 CntEL0BaseX + FVP_GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV + FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags + 0, // UINT32 GTxVirtualTimerGSIV + 0, // UINT32 GTxVirtualTimerFlags + FVP_GTX_COMMON_FLAGS // UINT32 GTxCommonFlags + } + }, + { + { + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof(EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), // UINT16 Length + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved + FVP_SBSA_WATCHDOG_REFRESH_BASE, // UINT64 RefreshFramePhysicalAddress + FVP_SBSA_WATCHDOG_CONTROL_BASE, // UINT64 WatchdogControlFramePhysicalAddress + FVP_SBSA_WATCHDOG_GSIV, // UINT32 WatchdogTimerGSIV + FVP_SBSA_WATCHDOG_FLAGS // UINT32 WatchdogTimerFlags } } }; -- 2.5.5

7 years, 2 months

[PATCH v4 0/2] Armada 70x0 firmware update command

by Marcin Wojtas

Hi Leif, Quick resend of the patchset with minor correction pointed in v3. The code can be also found in github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… We will pop the champagne after NonDiscoverable merge, but thank you very much for your help and support getting all Armada 70x0 stuff into the tree. Best regards, Marcin Changelog: v3 -> v4 * Change SPI_ID_SIZE to sizeof (UINT32) * Add reviewed-by v2 -> v3 * Rename header structure to MV_FIRMWARE_IMAGE_HEADER * Add STATIC attribute where possible * Improve flash probe (add comments, use UINT32, SPI_ID_SIZE define and SwapBytes32) * Use CalculateSum32() instead of custom implementation * Improve prints when parsing image path * Sort HiiGuid in Marvell.dec * Improve help in .uni file v1 -> v2 * Remove executing external shell commands from commandline - now only local files can be burnt to flash * Add MARVELL_SPI_FLASH_PROTOCOL and MARVELL_SPI_MASTER_PROTOCOL usage * In order to be standalone command, enable detecting and configuring SPI flash * Style cleanup and new comments Jan Dąbroś (2): Applications/FirmwareUpdate: Add 'fupdate' comand to shell Platforms/Marvell: Enable 'fupdate' command on Armada70x0 platform Applications/FirmwareUpdate/FUpdate.c | 413 ++++++++++++++++++++++++++++++++ Applications/FirmwareUpdate/FUpdate.inf | 75 ++++++ Applications/FirmwareUpdate/FUpdate.uni | Bin 0 -> 5146 bytes Platforms/Marvell/Armada/Armada.dsc.inc | 1 + Platforms/Marvell/Marvell.dec | 1 + 5 files changed, 490 insertions(+) create mode 100644 Applications/FirmwareUpdate/FUpdate.c create mode 100644 Applications/FirmwareUpdate/FUpdate.inf create mode 100644 Applications/FirmwareUpdate/FUpdate.uni -- 1.8.3.1

7 years, 4 months

[Patch v4 00/56] Enable Hisilicon new platform D05 and D02/3 bug fix

by Heyi Guo

The v4 version add D02/03 patches in and put D02/03/05 patches at one branch. Hisilicon new platform D05 will be pushed to Linaro Reference Platform 16.12 release, and these patches are to enable Hisilicon D05 in OPP. Also add the patches D02/3 platform bug fixed. Code can also be found in my linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-16.12-01-all Changelog v3>v4: * Improve the code according to Leif and Graeme's comments - Keep to use Intel BDS. - Keep to use GenericMemoryTest driver. - Other code format improvement - Add new patches which haven't send previous version - Slpit or merge patches according Lefi's comments Chenhui Sun (6): Hisilicon/UpdateFdtDxe: Add GenericMemTestProtocol dependency D02/ACPI: Use HISI0031 HID for uart on Hip05 soc Platform/D02: Update ACPI table header D03: Update ACPI Oem table header id D02: Update ACPI table header id D02/D03: Update version to 16.08 RC1 Hanjun Guo (1): D03/DSDT: use irq producer/consumer to support mbi-gen Heyi Guo (38): Hisilicon/Hi1610/PCIe: Add performace tuning Hisilicon/PCIe: extend support for maximum 8 root ports Hisilicon/PCIe: support different memory address in PCIe domain Hisilicon/PCIe: support multiple MSI target addresses Hisilicon/PCIeInit: Remove unused function PciePortReset Hisilicon/PCIeInit: fix PciePcsInit bug Hisilicon/I2CLib: Extend to support Hi1616 Hisilicon: Reorder DDR timing parameters by alphabetical Hisilicon: update memory init data structure to support D05 Platforms/Hisilicon: Add definition of NUMA related structures Platforms/Hisilicon: add D05 ACPI tables Platform/Hisilicon: Import AcpiPlatformDxe driver from MdeModulePkg Hisilicon/ACPI: Update SRAT from real memory configuration Hisilicon/HwMemInitLib.h: fix typo for phyDqsFallRiseDelay D03: Update SAS driver D03/OemNicConfig: add CpldIoLib to avoid potential build error Hisilicon: Rename Pv660.dsc.inc to be Hisilicon common include Hisilicon: Rename ArmPlatformLibPv660 to Hisilicon common ArmPlatformLib Hisilicon: Remove ArmVExpress including from build option Platforms/Hisilicon: add D05 binary module INF and binary files Platforms/Hisilicon: add D05 platform modules and files Hisilicon: fix FirmwareVendor pcd Hisilicon: Remove unused ACPI files Chips/Hisilicon/Ehci: Fix clang build error Hisilicon/D02: enlarge FVMAIN_COMPACT Hisilicon/D02: fix can not get IP address failed issue Hisilicon/D02: update ATF binaries to fix a bug in ATF code Hisilicon/D03: enlarge FVMAIN_COMPACT Platforms/D03: Update binaries D02/D03/D05: Support Spd mirror mode Hisilicon: remove D02 unused ACPI files Hisilicon: Add D03 ACPI tables Hisilicon/SMBIOS: Update ProcessorID from MIDR Hisilicon: Remove unnesseary variable initializtion D03/FdtUpdateLib: Update refclk in DT D03/ACPI: Refine SAS ASL code indention D03/USB: fix ehci interrupt pin number Hisilicon/Platforms: ignore memory test to speed boot time Kefeng Wang (1): D02/D03/ACPI: Fix wrong GTDT length Kejian Yan (2): D02/D03/Dsdt: add media-type property for hns D02/D03/Dsdt/hns: fix the bug of serdes loopback MaJun (1): D03/IORT:Change the single mapping flags of mbigen node to 1 Peicong Li (3): D03: enhance RTC lock acquiring Hisilicon/Serdes: add support for D05 D03/D05: Change to access EEPROM data by checking page boundary Salil Mehta (3): D03/ACPI: Add RoCE device to ACPI & IORT Tables D03/ACPI: Add support of RoCE Reset in DSDT D03/ACPI/ROCE: Add node-guid parameter to DSDT flyingnosky (1): D03/ACPI: support 50MHZ and 66MHZ boards in acpi mode .../Library/Hi1610Serdes/Hi1610SerdesLib.lib | Bin 601828 -> 603524 bytes .../Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib | Bin 253328 -> 247176 bytes .../Binary/Hi1610/Library/LpcLib/LpcLib.lib | Bin 13870 -> 13998 bytes .../PlatformSysCtrlLibHi1610.lib | Bin 273980 -> 305230 bytes .../Uart/LpcSerialPortLib/LpcSerialPortLib.lib | Bin 17086 -> 17022 bytes .../Library/Hi1616Serdes/Hi1616SerdesLib.inf | 48 + .../Library/Hi1616Serdes/Hi1616SerdesLib.lib | Bin 0 -> 707246 bytes .../PlatformSysCtrlLibHi1616.inf | 54 + .../PlatformSysCtrlLibHi1616.lib | Bin 0 -> 358602 bytes Chips/Hisilicon/Binary/License.txt | 25 + .../Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib | Bin 439708 -> 431524 bytes .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c | 269 +++++ .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni | 22 + .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 62 + .../HisiAcpiPlatformDxe/AcpiPlatformExtra.uni | 20 + .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 136 +++ .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.h | 16 + .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 216 +++- .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 2 + .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 6 +- .../ProcessorSubClassDxe/ProcessorSubClass.c | 6 +- .../Type09/MiscSystemSlotDesignationFunction.c | 23 +- .../Drivers/UpdateFdtDxe/UpdateFdtDxe.inf | 4 +- .../Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +- .../Hi1610/Drivers/PcieInit1610/PcieInit.c | 59 +- .../Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 6 +- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 241 ++-- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 15 +- .../Hi1610/Drivers/PcieInit1610/PcieKernelApi.h | 2 - .../Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf | 56 + .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 368 ++++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 85 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl | 88 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 36 + .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 691 +++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 305 +++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 261 +++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 367 ++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 136 +++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 29 + .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 91 ++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 96 ++ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 48 + .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 128 ++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc | 81 ++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc | 115 ++ Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- .../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 59 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 651 +++++++++++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 127 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 65 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc | 81 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 130 +++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl | 280 +++++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl | 28 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 1233 ++++++++++++++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 56 + .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 438 +++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 584 +++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 244 ++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl | 127 ++ .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 31 + Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 91 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 95 ++ .../Hi1616/D05AcpiTables/Hi1616Platform.h | 48 + .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 282 +++++ Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 78 ++ Chips/Hisilicon/HisiPkg.dec | 116 +- Chips/Hisilicon/Hisilicon.dsc.inc | 371 ++++++ Chips/Hisilicon/Hisilicon.fdf.inc | 139 +++ Chips/Hisilicon/Include/Library/AcpiNextLib.h | 19 +- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 62 +- Chips/Hisilicon/Include/Library/I2CLib.h | 2 +- Chips/Hisilicon/Include/Library/OemMiscLib.h | 1 + Chips/Hisilicon/Include/Library/PlatformPciLib.h | 142 ++- .../Hisilicon/Include/Library/PlatformSysCtrlLib.h | 9 + Chips/Hisilicon/Include/PlatformArch.h | 2 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 1 + .../ArmPlatformLibHisilicon/AArch64/Helper.S | 61 + .../ArmPlatformLibHisilicon/ArmPlatformLib.c | 107 ++ .../ArmPlatformLibHisilicon/ArmPlatformLib.inf | 69 ++ .../ArmPlatformLibHisilicon/ArmPlatformLibMem.c | 97 ++ .../ArmPlatformLibHisilicon/ArmPlatformLibSec.inf | 56 + .../Library/ArmPlatformLibPv660/AArch64/Helper.S | 61 - .../Library/ArmPlatformLibPv660/ArmPlatformLib.c | 108 -- .../Library/ArmPlatformLibPv660/ArmPlatformLib.inf | 69 -- .../ArmPlatformLibPv660/ArmPlatformLibMem.c | 98 -- .../ArmPlatformLibPv660/ArmPlatformLibSec.inf | 56 - Chips/Hisilicon/Library/I2CLib/I2CHw.h | 1 + Chips/Hisilicon/Library/I2CLib/I2CLib.c | 50 +- .../Library/PlatformIntelBdsLib/IntelBdsPlatform.c | 2 +- Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- Chips/Hisilicon/Pv660/Pv660.dsc.inc | 371 ------ Chips/Hisilicon/Pv660/Pv660.fdf.inc | 139 --- .../Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf | 56 - Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl | 337 ------ Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc | 85 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 5 +- .../Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 558 --------- .../Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl | 125 -- .../Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl | 261 ----- .../Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl | 247 ---- .../Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl | 136 --- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- .../Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl | 29 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 16 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl | 25 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl | 152 --- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl | 39 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 6 +- .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 128 -- .../Pv660/Pv660AcpiTables/Pv660Platform.h | 10 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc | 81 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc | 115 -- Platforms/Hisilicon/Binary/D02/Ebl/Ebl.efi | Bin 159744 -> 137056 bytes .../Binary/D02/MemoryInitPei/MemoryInit.efi | Bin 159136 -> 160672 bytes Platforms/Hisilicon/Binary/D02/bl1.bin | Bin 14344 -> 12296 bytes Platforms/Hisilicon/Binary/D02/fip.bin | Bin 45621 -> 45621 bytes .../D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 22304 -> 21696 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 22240 -> 22208 bytes .../Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 26720 -> 25440 bytes .../D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 24704 -> 23712 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 18368 -> 18080 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 63648 -> 56832 bytes .../Binary/D03/Drivers/OhciDxe/NativeOhci.efi | Bin 55488 -> 48352 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 22752 -> 22112 bytes .../Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi | Bin 262144 -> 262144 bytes .../Binary/D03/Drivers/Sas/SasDriverDxe.efi | Bin 233408 -> 210752 bytes .../D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 38624 -> 36480 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 22112 -> 21408 bytes Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi | Bin 159744 -> 134240 bytes .../Library/OemAddressMap2P/OemAddressMap2P.lib | Bin 19568 -> 19486 bytes .../Binary/D03/MemoryInitPei/MemoryInit.efi | Bin 158944 -> 161280 bytes Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/Binary/D03/bl1.bin | Bin 14336 -> 14336 bytes Platforms/Hisilicon/Binary/D03/fip.bin | Bin 45601 -> 45601 bytes .../Drivers/GetInfoFromBmc/GetInfoFromBmc.depex | Bin 0 -> 2 bytes .../D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 0 -> 19552 bytes .../D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf | 26 + .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex | Bin 0 -> 2 bytes .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 0 -> 25696 bytes .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf | 28 + .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 0 -> 22528 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf | 32 + .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 0 -> 23136 bytes .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex | Bin 0 -> 2 bytes .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf | 27 + .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex | Bin 0 -> 2 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 0 -> 15968 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf | 27 + .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf | 29 + .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf | 28 + .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf | 27 + .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf | 27 + .../Binary/D05/Drivers/OhciDxe/NativeOhci.efi | Bin 0 -> 48000 bytes .../Binary/D05/Drivers/OhciDxe/OhciDxe.inf | 26 + .../ReportPciePlugDidVidToBmc.depex | Bin 0 -> 2 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 0 -> 21536 bytes .../ReportPciePlugDidVidToBmc.inf | 25 + .../Binary/D05/Drivers/SFC/SFCDriver.depex | Bin 0 -> 2 bytes .../Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi | Bin 0 -> 262144 bytes .../Binary/D05/Drivers/SFC/SfcDxeDriver.inf | 29 + .../Binary/D05/Drivers/Sas/SasDriverDxe.efi | Bin 0 -> 210400 bytes .../Binary/D05/Drivers/Sas/SasDxeDriver.inf | 28 + .../D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 0 -> 35904 bytes .../Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf | 32 + .../TransferSmbiosInfo/TransSmbiosInfo.depex | Bin 0 -> 2 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 0 -> 16576 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf | 26 + Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi | Bin 0 -> 141344 bytes Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf | 32 + .../D05/Library/FdtUpdateLib/FdtUpdateLib.inf | 51 + .../D05/Library/FdtUpdateLib/FdtUpdateLib.lib | Bin 0 -> 108418 bytes .../Library/OemAddressMapD05/OemAddressMapD05.inf | 44 + .../Library/OemAddressMapD05/OemAddressMapD05.lib | Bin 0 -> 42136 bytes .../Binary/D05/MemoryInitPei/MemoryInit.efi | Bin 0 -> 273312 bytes .../Binary/D05/MemoryInitPei/MemoryInitPeim.inf | 33 + Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv | Bin 0 -> 262144 bytes Platforms/Hisilicon/Binary/D05/bl1.bin | Bin 0 -> 12296 bytes Platforms/Hisilicon/Binary/D05/fip.bin | Bin 0 -> 41493 bytes .../D02/Library/OemMiscLibD02/BoardFeatureD02.c | 9 +- .../D02/Library/PlatformPciLib/PlatformPciLib.c | 32 +- .../D02/Library/PlatformPciLib/PlatformPciLib.inf | 118 +- Platforms/Hisilicon/D02/Pv660D02.dsc | 13 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 24 +- Platforms/Hisilicon/D03/D03.dsc | 27 +- Platforms/Hisilicon/D03/D03.fdf | 10 +- .../Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 45 +- .../OemNicConfig2PHi1610/OemNicConfig2P.inf | 1 + Platforms/Hisilicon/D03/Include/Library/CpldD03.h | 4 + .../DS3231RealTimeClockLib.c | 77 +- .../DS3231RealTimeClockLib.inf | 2 + .../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 60 + .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 + .../Library/OemMiscLib2P/BoardFeature2PHi1610.c | 7 +- .../D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 + .../D03/Library/PlatformPciLib/PlatformPciLib.c | 41 +- .../D03/Library/PlatformPciLib/PlatformPciLib.inf | 118 +- Platforms/Hisilicon/D05/D05.dsc | 674 +++++++++++ Platforms/Hisilicon/D05/D05.fdf | 366 ++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 61 + .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 + .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 218 ++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 + .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 + .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 +++ 222 files changed, 13377 insertions(+), 3606 deletions(-) create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.lib create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib create mode 100644 Chips/Hisilicon/Binary/License.txt create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.h mode change 100755 => 100644 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h create mode 100644 Chips/Hisilicon/Hisilicon.dsc.inc create mode 100644 Chips/Hisilicon/Hisilicon.fdf.inc create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660.dsc.inc delete mode 100644 Chips/Hisilicon/Pv660/Pv660.fdf.inc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/NativeOhci.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.lib create mode 100644 Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.lib create mode 100644 Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInit.efi create mode 100644 Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv create mode 100644 Platforms/Hisilicon/Binary/D05/bl1.bin create mode 100644 Platforms/Hisilicon/Binary/D05/fip.bin create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf -- 1.9.1

7 years, 4 months

[PATCH 0/3] add hikey platform

by Haojian Zhuang

Haojian Zhuang (3): Platforms: add skeleton of hikey platform Drivers/Mmc/DwEmmc: add designware emmc support Platforms/Hisilicon/HiKey: enable emmc Chips/Hisilicon/Hi6220/Hi6220.dec | 33 ++ Chips/Hisilicon/Hi6220/Include/Hi6220.h | 75 +++ Drivers/Mmc/DwEmmcDxe/DwEmmc.h | 128 ++++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c | 651 +++++++++++++++++++++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec | 42 ++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf | 55 ++ Platforms/Hisilicon/HiKey/HiKey.dec | 42 ++ Platforms/Hisilicon/HiKey/HiKey.dsc | 510 ++++++++++++++++ Platforms/Hisilicon/HiKey/HiKey.fdf | 353 +++++++++++ Platforms/Hisilicon/HiKey/Include/ArmPlatform.h | 27 + Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c | 160 +++++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S | 49 ++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf | 54 ++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c | 210 +++++++ 14 files changed, 2389 insertions(+) create mode 100644 Chips/Hisilicon/Hi6220/Hi6220.dec create mode 100644 Chips/Hisilicon/Hi6220/Include/Hi6220.h create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmc.h create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf create mode 100644 Platforms/Hisilicon/HiKey/HiKey.dec create mode 100644 Platforms/Hisilicon/HiKey/HiKey.dsc create mode 100644 Platforms/Hisilicon/HiKey/HiKey.fdf create mode 100644 Platforms/Hisilicon/HiKey/Include/ArmPlatform.h create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c -- 2.7.4

7 years, 4 months

[PATCH 00/28] Update Hisilicon D02/D03 Platform Binaries and bug fixed

by Heyi Guo

Code can also be found in my linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-16.12-08-d02-d03 Changelog v1->v2: *Update D02/D03 platform binaries and bug fixed - Improve the code according to Leif's comments - Sent ACPI related patchs again which have not been reviewed - Update Memory init code - Change ACPI OEM header - Support RoCE Reset through ACPI method Chenhui Sun (5): D02/ACPI: Use HISI0031 HID for uart on Hip05 soc Platform/D02: Update ACPI table header D03: Update ACPI Oem table header id D02: Update ACPI table header id D02/D03: Update version to 16.08 RC1 Hanjun Guo (1): D03/DSDT: use irq producer/consumer to support mbi-gen Heyi Guo (14): Platforms/D02: Update binaries Platforms/D03: Update binaries D02/D03/D05: Support Spd mirror mode Hisilicon: remove D02 unused ACPI files Hisilicon: Add D03 ACPI tables Hisilicon/SMBIOS: Update ProcessorID from MIDR Hisilicon: Remove unnesseary variable initializtion D03/OemMiscLib: Add interface for SAS driver D03: Set PcdArmArchTimerFreqInHz to 0 D03/FdtUpdateLib: Update refclk in DT D02: Disable memory test in BDS D03: Disable memory test in BDS D03/ACPI: Refine SAS ASL code indention D03/USB: fix ehci interrupt pin number Kefeng Wang (1): D02/D03/ACPI: Fix wrong GTDT length Kejian Yan (2): D02/D03/Dsdt: add media-type property for hns D02/D03/Dsdt/hns: fix the bug of serdes loopback MaJun (1): D03/IORT:Change the single mapping flags of mbigen node to 1 Salil Mehta (3): D03/ACPI: Add RoCE device to ACPI & IORT Tables D03/ACPI: Add support of RoCE Reset in DSDT D03/ACPI/ROCE: Add node-guid parameter to DSDT flyingnosky (1): D03/ACPI: support 50MHZ and 66MHZ boards in acpi mode .../Library/Hi1610Serdes/Hi1610SerdesLib.lib | Bin 601828 -> 603524 bytes .../Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib | Bin 253328 -> 247176 bytes .../Binary/Hi1610/Library/LpcLib/LpcLib.lib | Bin 13870 -> 13998 bytes .../PlatformSysCtrlLibHi1610.lib | Bin 273980 -> 305230 bytes .../Uart/LpcSerialPortLib/LpcSerialPortLib.lib | Bin 17086 -> 17022 bytes .../Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib | Bin 439708 -> 431524 bytes .../ProcessorSubClassDxe/ProcessorSubClass.c | 6 +- .../Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf | 56 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 368 +++++++++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 85 +++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl | 88 +++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 36 ++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 692 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 305 +++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 261 ++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 367 +++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 136 ++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 29 + .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 91 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 96 +++ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 48 ++ .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 128 ++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc | 81 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc | 115 ++++ Chips/Hisilicon/Include/Library/HwMemInitLib.h | 4 + .../Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf | 56 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl | 337 ---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc | 85 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 5 +- .../Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 558 ----------------- .../Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl | 125 ---- .../Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl | 261 -------- .../Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl | 247 -------- .../Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl | 136 ---- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- .../Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl | 29 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 16 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl | 25 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl | 152 ----- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl | 39 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 6 +- .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 128 ---- .../Pv660/Pv660AcpiTables/Pv660Platform.h | 10 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc | 81 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc | 115 ---- Platforms/Hisilicon/Binary/D02/Ebl/Ebl.efi | Bin 159744 -> 137056 bytes .../Binary/D02/MemoryInitPei/MemoryInit.efi | Bin 159136 -> 160672 bytes Platforms/Hisilicon/Binary/D02/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/Binary/D02/bl1.bin | Bin 14344 -> 12296 bytes Platforms/Hisilicon/Binary/D02/fip.bin | Bin 45621 -> 45621 bytes .../D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 22304 -> 21696 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 22240 -> 22208 bytes .../Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 26720 -> 25440 bytes .../D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 24704 -> 23712 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 18368 -> 18080 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 63648 -> 56832 bytes .../Binary/D03/Drivers/OhciDxe/NativeOhci.efi | Bin 55488 -> 48352 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 22752 -> 22112 bytes .../Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi | Bin 262144 -> 262144 bytes .../Binary/D03/Drivers/Sas/SasDriverDxe.efi | Bin 233408 -> 210752 bytes .../D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 38624 -> 36480 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 22112 -> 21408 bytes Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi | Bin 159744 -> 134240 bytes .../Library/OemAddressMap2P/OemAddressMap2P.lib | Bin 19568 -> 19486 bytes .../Binary/D03/MemoryInitPei/MemoryInit.efi | Bin 158944 -> 161344 bytes Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/Binary/D03/bl1.bin | Bin 14336 -> 14336 bytes Platforms/Hisilicon/Binary/D03/fip.bin | Bin 45601 -> 45601 bytes Platforms/Hisilicon/D02/Pv660D02.dsc | 4 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 24 +- Platforms/Hisilicon/D03/D03.dsc | 10 +- Platforms/Hisilicon/D03/D03.fdf | 10 +- .../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 60 ++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 + .../D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 + 83 files changed, 3198 insertions(+), 2420 deletions(-) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc -- 1.9.1

7 years, 4 months

[PATCH v3 0/2] Armada 70x0 firmware update command

by Marcin Wojtas

Hi, I sent v3 of firmware update command. I addressed all remarks from v2 review. Details can be found in the changelog below. The code can be also found in github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v2 -> v3 * Rename header structure to MV_FIRMWARE_IMAGE_HEADER * Add STATIC attribute where possible * Improve flash probe (add comments, use UINT32, SPI_ID_SIZE define and SwapBytes32) * Use CalculateSum32() instead of custom implementation * Improve prints when parsing image path * Sort HiiGuid in Marvell.dec * Improve help in .uni file v1 -> v2 * Remove executing external shell commands from commandline - now only local files can be burnt to flash * Add MARVELL_SPI_FLASH_PROTOCOL and MARVELL_SPI_MASTER_PROTOCOL usage * In order to be standalone command, enable detecting and configuring SPI flash * Style cleanup and new comments Jan Dąbroś (2): Applications/FirmwareUpdate: Add 'fupdate' comand to shell Platforms/Marvell: Enable 'fupdate' command on Armada70x0 platform Applications/FirmwareUpdate/FUpdate.c | 413 ++++++++++++++++++++++++++ Applications/FirmwareUpdate/FUpdate.inf | 75 +++++ Applications/FirmwareUpdate/FUpdate.uni | Bin 0 -> 5146 bytes Platforms/Marvell/Armada/Armada.dsc.inc | 1 + Platforms/Marvell/Include/Protocol/SpiFlash.h | 2 + Platforms/Marvell/Marvell.dec | 1 + 6 files changed, 492 insertions(+) create mode 100644 Applications/FirmwareUpdate/FUpdate.c create mode 100644 Applications/FirmwareUpdate/FUpdate.inf create mode 100644 Applications/FirmwareUpdate/FUpdate.uni -- 1.8.3.1

7 years, 4 months

[PATCH v2 0/2] Armada 70x0 firmware update command

by Marcin Wojtas

Hi, I sent the last patchset of Marvell Armada 70x0 support. It is v2 of the firmware update shell command (v1 was in the very first big patchset of basic support). After long discussions, executing external shell commands was removed, as it's not proper (nor supported) solution in EDK2. Command's code was cleaned-up and massively reworked in order to be independent from tftp and sf commands. Now 'fupdate' command performs updating firmware from file placed on local filesystem. It consumes MARVELL_SPI_FLASH_PROTOCOL and MARVELL_SPI_MASTER_PROTOCOL in order to handle SPI transfer of the image. Command also verifies image data correctness before burning to flash. The code can be also found in github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v1 -> v2 * Remove executing external shell commands from commandline - now only local files can be burnt to flash * Add MARVELL_SPI_FLASH_PROTOCOL and MARVELL_SPI_MASTER_PROTOCOL usage * In order to be standalone command, enable detecting and configuring SPI flash * Style cleanup and new comments Jan Dąbroś (2): Applications/FirmwareUpdate: Add 'fupdate' comand to shell Platforms/Marvell: Enable 'fupdate' command on Armada70x0 platform Applications/FirmwareUpdate/FUpdate.c | 430 ++++++++++++++++++++++++++++++++ Applications/FirmwareUpdate/FUpdate.inf | 75 ++++++ Applications/FirmwareUpdate/FUpdate.uni | Bin 0 -> 5838 bytes Platforms/Marvell/Armada/Armada.dsc.inc | 1 + Platforms/Marvell/Marvell.dec | 1 + 5 files changed, 507 insertions(+) create mode 100644 Applications/FirmwareUpdate/FUpdate.c create mode 100644 Applications/FirmwareUpdate/FUpdate.inf create mode 100644 Applications/FirmwareUpdate/FUpdate.uni -- 1.8.3.1

7 years, 4 months

[PATCH v4 00/12] Armada 7040 SD/MMC support + PciEmulation

by Marcin Wojtas

Hi, I send combined patchset of SD/MMC and PciEmulation support, in order to provide reorganized branch for merge. The biggest change is leaving untouched most of imported files, whose renaming was removed. More details can be found in the changelog. Code is also available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… We are looking forward to any comments or remarks. Best regards, Marcin Changelog: v3 -> v4 - Leave original names of imported files - Modify copyrights only in updated files - Change GUID and BASE_NAME of XenonDxe driver - Squash second SD/MMC port addition to initial commit of PciEmulation - Mix order of commits with PciEmulation patchset - Add 'Reviewed-by' to according commits v2 -> v3 - Move driver to Drivers/SdMmc/XenonDxe/ directory - Use 'Retry' instead of 'Timeout', when necessary - Add comments to remaining stalls - Enable DMA and remove PIO-related modifications - Add description of the second controller in PciEmulation (new commit) v1 -> v2 - Import whole stack from MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ - Move driver to Drivers/SdMmc/Xenon/ directory - Use Slot number 0 only, since XENON is using only this one - Remove unnecessary delay - Move SD/MMC PHY configuration to MPP lib (additional commit) - Replace comments with defines - Add descriptions to delays - Improve commit logs Jan Dąbroś (8): Drivers/SdMmc: Import SdMmcPciHcDxe driver Drivers/SdMmc: Replace deprecated debug level macros Drivers/SdMmc: Adjust stack to fulfill Xenon controller demands Platforms/Marvell: MppLib: Configure SD/MMC PHY Platforms/Marvell: Enable USB stack for Armada70x0 platform Platforms/Marvell: Enable SATA stack for Armada70x0 platform Platforms/Marvell: Enable SD/MMC stack for Armada70x0 platforms Platforms/Marvell: Enable PciEmulation driver for Armada70x0 platform Marcin Wojtas (4): Platforms/Marvell: Add PciEmulation driver Platforms/Marvell: Enable two xHCI ports for Armada70x0 board Platforms/Marvell: Enable SATA port for Armada70x0 board Platforms/Marvell: Enable SD/MMC for Armada70x0 board .../Marvell/PortingGuide/PciEmulation.txt | 31 + Drivers/SdMmc/XenonDxe/ComponentName.c | 211 +++ Drivers/SdMmc/XenonDxe/EmmcDevice.c | 1162 ++++++++++++ Drivers/SdMmc/XenonDxe/SdDevice.c | 1190 ++++++++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 1315 +++++++++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h | 785 ++++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 64 + Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.uni | 23 + Drivers/SdMmc/XenonDxe/SdMmcPciHcDxeExtra.uni | 19 + Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 1923 ++++++++++++++++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHci.h | 546 ++++++ Drivers/SdMmc/XenonDxe/XenonSdhci.c | 665 +++++++ Drivers/SdMmc/XenonDxe/XenonSdhci.h | 346 ++++ Platforms/Marvell/Armada/Armada.dsc.inc | 25 + Platforms/Marvell/Armada/Armada70x0.dsc | 8 + Platforms/Marvell/Armada/Armada70x0.fdf | 25 +- Platforms/Marvell/Library/MppLib/MppLib.c | 53 + Platforms/Marvell/Library/MppLib/MppLib.inf | 1 + Platforms/Marvell/Marvell.dec | 5 + Platforms/Marvell/PciEmulation/PciEmulation.c | 230 +++ Platforms/Marvell/PciEmulation/PciEmulation.inf | 61 + 21 files changed, 8687 insertions(+), 1 deletion(-) create mode 100644 Documentation/Marvell/PortingGuide/PciEmulation.txt create mode 100644 Drivers/SdMmc/XenonDxe/ComponentName.c create mode 100755 Drivers/SdMmc/XenonDxe/EmmcDevice.c create mode 100644 Drivers/SdMmc/XenonDxe/SdDevice.c create mode 100644 Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c create mode 100644 Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h create mode 100644 Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf create mode 100644 Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.uni create mode 100644 Drivers/SdMmc/XenonDxe/SdMmcPciHcDxeExtra.uni create mode 100644 Drivers/SdMmc/XenonDxe/SdMmcPciHci.c create mode 100644 Drivers/SdMmc/XenonDxe/SdMmcPciHci.h create mode 100755 Drivers/SdMmc/XenonDxe/XenonSdhci.c create mode 100644 Drivers/SdMmc/XenonDxe/XenonSdhci.h create mode 100644 Platforms/Marvell/PciEmulation/PciEmulation.c create mode 100644 Platforms/Marvell/PciEmulation/PciEmulation.inf -- 1.8.3.1

7 years, 4 months

[PATCH v3 0/7] Armada 7040 SD/MMC support

by Marcin Wojtas

Hi, On top of the latest NonDiscoverable (v4) PciEmulation support (all devices work without modifying already accepted patchset) I submit v3 of Xenon SdMmc driver. Improvements after review of v2 have been implemented, also entire SdMmcPciHcDxe was imported to new driver's directory. There are two big modifications though - DMA operation has been enabled and the diff between original driver and Xenon version has shrunk and is limited only to the initialization process. Other than that, the second controller on Armada 7040 was added to PciEmulation HW description and later enabled. More details can be found in the changelog. Code is also available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… We are looking forward to any comments or remarks. Best regards, Marcin Changelog: v2 -> v3 - Move driver to Drivers/SdMmc/XenonDxe/ directory - Use 'Retry' instead of 'Timeout', when necessary - Add comments to remaining stalls - Enable DMA and remove PIO-related modifications - Add description of the second controller in PciEmulation (new commit) v1 -> v2 - Import whole stack from MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ - Move driver to Drivers/SdMmc/Xenon/ directory - Use Slot number 0 only, since XENON is using only this one - Remove unnecessary delay - Move SD/MMC PHY configuration to MPP lib (additional commit) - Replace comments with defines - Add descriptions to delays - Improve commit logs Jan Dąbroś (5): Platforms/Marvell: MppLib: Configure SD/MMC PHY Drivers/SdMmc: Import SdMmcPciHcDxe driver Drivers/SdMmc: Replace deprecated debug level macros Drivers/SdMmc: Adjust stack to fulfill Xenon controller demands Platforms/Marvell: Enable SD/MMC stack for Armada70x0 platforms Marcin Wojtas (2): Platforms/Marvell/PciEmulation: Add second SD/MMC device of Armada70x0 Platforms/Marvell: Enable SD/MMC for Armada70x0 board Drivers/SdMmc/XenonDxe/MvComponentName.c | 213 +++ Drivers/SdMmc/XenonDxe/MvEmmcDevice.c | 1164 ++++++++++++++ Drivers/SdMmc/XenonDxe/MvSdDevice.c | 1192 ++++++++++++++ Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxe.c | 1314 ++++++++++++++++ Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxe.h | 787 +++++++++ Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxe.inf | 64 + Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxe.uni | 23 + Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxeExtra.uni | 19 + Drivers/SdMmc/XenonDxe/MvSdMmcPciHci.c | 1926 +++++++++++++++++++++++ Drivers/SdMmc/XenonDxe/MvSdMmcPciHci.h | 546 +++++++ Drivers/SdMmc/XenonDxe/XenonSdhci.c | 666 ++++++++ Drivers/SdMmc/XenonDxe/XenonSdhci.h | 346 ++++ Platforms/Marvell/Armada/Armada.dsc.inc | 5 + Platforms/Marvell/Armada/Armada70x0.dsc | 1 + Platforms/Marvell/Armada/Armada70x0.fdf | 7 +- Platforms/Marvell/Library/MppLib/MppLib.c | 53 + Platforms/Marvell/Library/MppLib/MppLib.inf | 1 + Platforms/Marvell/PciEmulation/PciEmulation.c | 8 +- 18 files changed, 8330 insertions(+), 5 deletions(-) create mode 100644 Drivers/SdMmc/XenonDxe/MvComponentName.c create mode 100755 Drivers/SdMmc/XenonDxe/MvEmmcDevice.c create mode 100644 Drivers/SdMmc/XenonDxe/MvSdDevice.c create mode 100644 Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxe.c create mode 100644 Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxe.h create mode 100644 Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxe.inf create mode 100644 Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxe.uni create mode 100644 Drivers/SdMmc/XenonDxe/MvSdMmcPciHcDxeExtra.uni create mode 100644 Drivers/SdMmc/XenonDxe/MvSdMmcPciHci.c create mode 100644 Drivers/SdMmc/XenonDxe/MvSdMmcPciHci.h create mode 100755 Drivers/SdMmc/XenonDxe/XenonSdhci.c create mode 100644 Drivers/SdMmc/XenonDxe/XenonSdhci.h -- 1.8.3.1

7 years, 4 months

[PATCH v3 0/4] OpenPlatformPkg/Drivers/Net/MarvellYukonDxe: Added multi-controller support

by Daniil Egranov

Changelog: v3 Fixed style issues (STATIC, VOID, spaces and include files order). Fixed depreciated defines (EFI_D_ERROR and EFI_D_NET). Split patch into a set of patches due to the patch size. v2 - Updated msk_if_softc structures to hold data pointers to its parent controller structure and corresponding PHY structure. - Updated e1000phy_softc structure to hold a data pointer to its logical controller. - Reduced number of parameters in multiple functions. Using the msk_if_softc and msk_softc structure members instead. - Corrected the code for dual MAC controllers. Each logical interface has its own TX and RX buffers. The YUKON_DRIVER driver's structure includes a controller port number. The SNP interface functions passing a msk_if_softc object (corresponding to the controller interface) to the if_msk interface functions. - Removed linked lists from the if_msk and e1000phy. The association between msk_softc and controller resolved on the SNP interface level. v1 The patch adds support for multi-controller configuration. Daniil Egranov (4): Drivers/Net/MarvellYukonDxe: Pass interface structure as a parameter Drivers/Net/MarvellYukonDxe: Pass PHY structure as a parameter Drivers/Net/MarvellYukonDxe: Added multi-MAC and multi-controller support Drivers/Net/MarvellYukonDxe: Enhance controller's interface structure Drivers/Net/MarvellYukonDxe/DriverBinding.c | 452 +++++++--- Drivers/Net/MarvellYukonDxe/MarvellYukon.h | 71 ++ Drivers/Net/MarvellYukonDxe/Snp.c | 64 +- Drivers/Net/MarvellYukonDxe/e1000phy.c | 241 +++--- Drivers/Net/MarvellYukonDxe/e1000phyreg.h | 12 + Drivers/Net/MarvellYukonDxe/if_msk.c | 1223 ++++++++++++++------------- Drivers/Net/MarvellYukonDxe/if_msk.h | 23 +- Drivers/Net/MarvellYukonDxe/if_mskreg.h | 16 +- Drivers/Net/MarvellYukonDxe/miivar.h | 15 +- 9 files changed, 1274 insertions(+), 843 deletions(-) -- 2.7.4

7 years, 4 months

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Linaro-uefi November 2016