Linaro-uefi July 2016

linaro-uefi@lists.linaro.org

17 participants
33 discussions

[PATCH v6 00/23] Marvell Armada7040 SoC support

by Marcin Wojtas

Hello, Here's 6th version of the support. It's rebased on top of newest master branch and comprise fixes from the latest review. Patches are also available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v5 -> v6 * Initial support - Enable compilation after ArmMmuLib was added to edk2 - Remove commented-out line - Enable up to 64MB RamDisk space for all Armada platforms - Move adding "-fno-unwind-tables" build flag to a separate patch and add explanation for this change * I2C - Change MvI2cDevicePathProtocol to STATIC in MvI2cDxe.c - Generate new I2C_GUID - Move I2C_GUID to header files and extend existing FIXME comment * Fupdate - Add FIXME note over including relative path from edk2. It was needed after fixing regression by replacing ShellExecute with RunShellCommand v4 -> v5 * Add ParsePcdLib - Library created in order to parse PCD strings - it makes support for multi-controller easier to implement * I2c - Introduce multi-bus support - Remove comments regarding GUID-slave address dependency - Add FIXME comment about no-restart dual definition * eeprom command - Enable selecting I2C bus - Add FIXME comment about no-restart dual definition * Spi - Fix writing procedure - Rename protocol to MARVELL_SPI_MASTER_PROTOCOL * General - Remove commented-out, unused lines v3 -> v4 * Update license messages - Unify - Add "Based on" statement were needed - Wrap every message at 80 characters - Add Marvell copyrights * Fix namings - All protocol/file names updated as suggested in review * Clean-up - Remove unneded blank lines and spaces - Fix typos * Add "Reviewed by" for currently accepted patches * Add support for new platform - Armada70x0 - Remove support for old platforms Apn806 and Armada7040_rz - Armada70x0 is based on Armada7040_rz with silicone fixes and improvements - No changes on drivers/libraries caused by this change - Update commit logs in whole tree * MppLib - Fix issue with writing to uninitialized memory * I2c and eeprom command - Remove dependency on BdsLibConnectAll call - I2c stack is connected only if eeprom command is executed and only in case it wasn't done before - gBS->ConnectController() used * BdsLib - Remove import of BdsLib - After rebase on top of new edk2, extra BdsLibConnectAll call isn't necessary (actually for now no BdsLibConnectAll is needed at all for our platform support) * sf command - Remove inclusion of relative path - Necessary macro now defined in globally exported file * RamDisk driver - Drop patch with this feature - As long as there is no possibility to format RamDisk with FAT, driver is not useful on Armada70x0 * fupdate command - Fix issue with "bad checksum" v2 -> v3 * Decrease binary size * Fupdate command - Remove regression - replace ShellExecute with RunShellCommand - Improve error paths * Add proper DEBUG library and change error print levels v1 -> v2 * Fix "may be used uninitialized" variables issue, branch compiles both with DEBUG and RELEASE flags * Remove I2C_FLAG_NORESTART dependency - replace it with local definition * Remove Marvell UART Library: - DW8250 IP has programming interface compatible with NS-16550. Since in edk2 there is support for 16550, internal library is unnecessary. - /Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf is used instead * RamDisk driver: - Remove old driver imported from EFI TOOLKIT 2.0 - Replace it with new MdeModulePkg/Universal/Disk/RamDiskDxe from edk2 - Lack of FAT formatting issue emerged * Add explicit dependency on IoLib in Drivers/Spi/SpiDxe.inf * Add poster's "Signed-off-by" registry to every commit message * Move to 05.04.2016 HEAD of edk2/master - Update CpuExceptionHandlerLib within OPP. Bartosz Szczepanek (3): Drivers/I2c: Create MvI2cDxe driver Drivers/I2c: Add MvEeprom driver Aplications/Eeprom: Add 'eeprom' command to shell Haim Boot (1): Platforms/Marvell: Enable compilation with aarch64-linux-gnueabi toolchain Jan Dąbroś (17): Platforms/Marvell: Create MppLib Platforms/Marvell: Armada: Enable MppLib on Armada70x0 platform Platforms/Marvell: Create ParsePcdLib Platforms/Marvell: Enable ParsePcdLib for Armada70x0 platform Platforms/Marvell: Enable I2C driver on Armada70x0 platform Plaforms/Marvell: Enable EEPROM driver on Armada70x0 platform Platforms/Marvell: Enable 'eeprom' command on Armada70x0 platform Platforms/Marvell: Add MARVELL_SPI_MASTER_PROTOCOL Drivers/Spi: Add Spi master driver Platforms/Marvell: Enable Spi master driver for Armada70x0 platform Platforms/Marvell: Add MARVELL_SPI_FLASH_PROTOCOL Drivers/Spi: Implement Spi flash driver Platforms/Marvell: Enable Spi flash driver for Armada70x0 platform Applications/SpiTool: Add 'sf' command utility Platforms/Marvell: Enable 'sf' command on Armada70x0 platform Applications/FirmwareUpdate: Add 'fupdate' comand to shell Platforms/Marvell: Enable 'fupdate' command on Armada70x0 platform Yehuda Yitschak (2): Platforms/Marvell: Add initial support for Armada70x0 SOC lib Platforms/Marvell: Add support for Armada70x0 platform Applications/EepromCmd/EepromCmd.c | 397 +++++++++++ Applications/EepromCmd/EepromCmd.inf | 71 ++ Applications/EepromCmd/EepromCmd.uni | Bin 0 -> 6816 bytes Applications/FirmwareUpdate/FUpdate.c | 448 +++++++++++++ Applications/FirmwareUpdate/FUpdate.inf | 68 ++ Applications/FirmwareUpdate/FUpdate.uni | Bin 0 -> 5838 bytes Applications/SpiTool/SpiFlashCmd.c | 526 +++++++++++++++ Applications/SpiTool/SpiFlashCmd.inf | 75 +++ Applications/SpiTool/SpiFlashCmd.uni | Bin 0 -> 7216 bytes Documentation/Marvell/Drivers/EepromDriver.txt | 96 +++ Documentation/Marvell/Drivers/I2cDriver.txt | 64 ++ Documentation/Marvell/Drivers/SpiDriver.txt | 116 ++++ Documentation/Marvell/PortingGuide/I2c.txt | 20 + Documentation/Marvell/PortingGuide/Mpp.txt | 48 ++ Documentation/Marvell/PortingGuide/Spi.txt | 15 + Documentation/Marvell/PortingGuide/SpiFlash.txt | 23 + Drivers/I2c/Devices/MvEeprom/MvEeprom.c | 292 ++++++++ Drivers/I2c/Devices/MvEeprom/MvEeprom.h | 103 +++ Drivers/I2c/Devices/MvEeprom/MvEeprom.inf | 70 ++ Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 739 +++++++++++++++++++++ Drivers/I2c/MvI2cDxe/MvI2cDxe.h | 269 ++++++++ Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 75 +++ Drivers/Spi/Devices/MvSpiFlash.c | 531 +++++++++++++++ Drivers/Spi/Devices/MvSpiFlash.h | 132 ++++ Drivers/Spi/Devices/MvSpiFlash.inf | 67 ++ Drivers/Spi/MvSpiDxe.c | 379 +++++++++++ Drivers/Spi/MvSpiDxe.h | 145 ++++ Drivers/Spi/MvSpiDxe.inf | 66 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 453 +++++++++++++ Platforms/Marvell/Armada/Armada70x0.dsc | 97 +++ Platforms/Marvell/Armada/Armada70x0.fdf | 270 ++++++++ .../Armada70x0Lib/AArch64/ArmPlatformHelper.S | 66 ++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 155 +++++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 69 ++ .../Library/Armada70x0Lib/Armada70x0LibMem.c | 93 +++ Platforms/Marvell/Include/Library/MppLib.h | 42 ++ Platforms/Marvell/Include/Library/ParsePcdLib.h | 46 ++ Platforms/Marvell/Include/Protocol/Eeprom.h | 60 ++ Platforms/Marvell/Include/Protocol/Spi.h | 105 +++ Platforms/Marvell/Include/Protocol/SpiFlash.h | 113 ++++ Platforms/Marvell/Library/MppLib/MppLib.c | 163 +++++ Platforms/Marvell/Library/MppLib/MppLib.inf | 107 +++ .../Marvell/Library/ParsePcdLib/ParsePcdLib.c | 228 +++++++ .../Marvell/Library/ParsePcdLib/ParsePcdLib.inf | 50 ++ Platforms/Marvell/Marvell.dec | 136 ++++ 45 files changed, 7088 insertions(+) create mode 100644 Applications/EepromCmd/EepromCmd.c create mode 100644 Applications/EepromCmd/EepromCmd.inf create mode 100644 Applications/EepromCmd/EepromCmd.uni create mode 100644 Applications/FirmwareUpdate/FUpdate.c create mode 100644 Applications/FirmwareUpdate/FUpdate.inf create mode 100644 Applications/FirmwareUpdate/FUpdate.uni create mode 100644 Applications/SpiTool/SpiFlashCmd.c create mode 100644 Applications/SpiTool/SpiFlashCmd.inf create mode 100644 Applications/SpiTool/SpiFlashCmd.uni create mode 100644 Documentation/Marvell/Drivers/EepromDriver.txt create mode 100644 Documentation/Marvell/Drivers/I2cDriver.txt create mode 100644 Documentation/Marvell/Drivers/SpiDriver.txt create mode 100644 Documentation/Marvell/PortingGuide/I2c.txt create mode 100644 Documentation/Marvell/PortingGuide/Mpp.txt create mode 100644 Documentation/Marvell/PortingGuide/Spi.txt create mode 100644 Documentation/Marvell/PortingGuide/SpiFlash.txt create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.c create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.h create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.inf create mode 100755 Drivers/I2c/MvI2cDxe/MvI2cDxe.c create mode 100644 Drivers/I2c/MvI2cDxe/MvI2cDxe.h create mode 100755 Drivers/I2c/MvI2cDxe/MvI2cDxe.inf create mode 100755 Drivers/Spi/Devices/MvSpiFlash.c create mode 100755 Drivers/Spi/Devices/MvSpiFlash.h create mode 100644 Drivers/Spi/Devices/MvSpiFlash.inf create mode 100755 Drivers/Spi/MvSpiDxe.c create mode 100644 Drivers/Spi/MvSpiDxe.h create mode 100644 Drivers/Spi/MvSpiDxe.inf create mode 100644 Platforms/Marvell/Armada/Armada.dsc.inc create mode 100644 Platforms/Marvell/Armada/Armada70x0.dsc create mode 100644 Platforms/Marvell/Armada/Armada70x0.fdf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c create mode 100644 Platforms/Marvell/Include/Library/MppLib.h create mode 100644 Platforms/Marvell/Include/Library/ParsePcdLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Eeprom.h create mode 100644 Platforms/Marvell/Include/Protocol/Spi.h create mode 100644 Platforms/Marvell/Include/Protocol/SpiFlash.h create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.c create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.inf create mode 100644 Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.c create mode 100644 Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.inf create mode 100644 Platforms/Marvell/Marvell.dec -- 1.8.3.1

8 years, 1 month

[PATCH v6 0/4] arm64, xen: add xen_boot support into grup-mkconfig

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> This patchset add xen_boot support into grup-mkconfig for generating xen boot entrances automatically Also update the docs/grub.texi for new xen_boot commands. This patchset has been tested on Foudation model with a bug fix: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00205.html ChangeLog: v6: http://lists.gnu.org/archive/html/grub-devel/2016-07/ Fix Coding style of util/grub.d/20_linux_xen.in, use soft tab. v5: http://lists.gnu.org/archive/html/grub-devel/2016-07/msg00008.html Update the introduction of xen_module commands in docs/grub.texi, according to the suggestion from Julien Grall v4: http://lists.gnu.org/archive/html/grub-devel/2016-05/ according to the XSM loading mechanism of Xen(upstreamed), update the introduction of xen_module commands in docs/grub.texi v3: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00314.html reorder the patches update the introduction of xen_module commands in docs/grub.texi v2: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00282.html add "--nounzip" option support in xen_module use "feature_xen_boot" instead of "grub_xen_boot" update the introduction of xen boot commands in docs/grub.texi v1 :first upstream patchset: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00264.html Fu Wei (4): i386,xen: Add xen_hypervisor and xen_module aliases for i386 arm64: add "--nounzip" option support in xen_module command * util/grub.d/20_linux_xen.in: Add xen_boot command support arm64: update the introduction of xen boot commands in docs/grub.texi docs/grub.texi | 32 +++++++++----------------------- grub-core/loader/arm64/xen_boot.c | 17 +++++++++++++++++ grub-core/loader/i386/xen.c | 7 +++++++ grub-core/normal/main.c | 2 +- util/grub.d/20_linux_xen.in | 13 ++++++++++--- 5 files changed, 44 insertions(+), 27 deletions(-) -- 2.5.5

8 years, 1 month

[PATCH 1/3] Platforms/ARM/Juno: Fix IO window translate offset in PCIe root complex

by Sudeep Holla

XPress-RICH3 PCIe driver initialises the root complex with the same source and target address for IO window which makes translate offset 0. This patch fixes the translate offset for the IO window in Juno PCIe root complex ACPI table. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl index 800d2cb3b2fb..ab5041db731a 100644 --- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl +++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl @@ -109,7 +109,7 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM 0x00000000, // Granularity 0x5f800000, // Min Base Address 0x5fffffff, // Max Base Address - 0x5f800000, // Translate + 0x00000000, // Translate 0x00800000 // Length ) }) // Name(RBUF) -- 1.9.1

8 years, 1 month

[PATCH] Platforms/ARM: fix gtdt.asl for VExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc | 128 ++++++++++++++++++++++------ 1 file changed, 101 insertions(+), 27 deletions(-) diff --git a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc index 142249f..8ed9a31 100644 --- a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc +++ b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc @@ -19,21 +19,70 @@ #include <Library/PcdLib.h> #include <IndustryStandard/Acpi61.h> -#define SECURE_TIMER_EL1_GSIV 0x1D -#define NON_SECURE_TIMER_EL1_GSIV 0x1E -#define VIRTUAL_TIMER_GSIV 0x1B -#define NON_SECURE_EL2_GSIV 0x1A +#define FVP_SYSTEM_TIMER_BASE_ADDRESS 0x000000002a430000 +#define FVP_CNT_READ_BASE_ADDRESS 0x000000002a800000 -#define GT_BLOCK_CTL_BASE 0x000000002A810000 -#define GT_BLOCK_FRAME1_CTL_BASE 0x000000002A820000 -#define GT_BLOCK_FRAME1_GSIV 0x29 +#define FVP_SECURE_TIMER_EL1_GSIV 0x1D +#define FVP_NON_SECURE_TIMER_EL1_GSIV 0x1E +#define FVP_VIRTUAL_TIMER_GSIV 0x1B +#define FVP_NON_SECURE_EL2_GSIV 0x1A + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SECURE EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_NON_SECURE 0 + +#define FVP_GTDT_GTIMER_FLAGS (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_EDGE_TRIGGERED) + +#define FVP_PLATFORM_TIMER_COUNT 2 +#define FVP_TIMER_FRAMES_COUNT 2 +#define FVP_WATCHDOG_COUNT 1 + +#define FVP_GT_BLOCK_CTL_BASE 0x000000002A810000 +#define FVP_GT_BLOCK_FRAME0_CTL_BASE 0x000000002A820000 +#define FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define FVP_GT_BLOCK_FRAME0_GSIV 0x39 + +#define FVP_GT_BLOCK_FRAME1_CTL_BASE 0x000000002A830000 +#define FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define FVP_GT_BLOCK_FRAME1_GSIV 0x3A + +#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 + +#define FVP_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 + +#define FVP_GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_SECURE) + +#define FVP_SBSA_WATCHDOG_REFRESH_BASE 0x000000002a450000 +#define FVP_SBSA_WATCHDOG_CONTROL_BASE 0x000000002a440000 +#define FVP_SBSA_WATCHDOG_GSIV 0x3B + +#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 + +#define FVP_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED) #pragma pack (1) typedef struct { EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock; - EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[1]; + EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[FVP_TIMER_FRAMES_COUNT]; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[FVP_WATCHDOG_COUNT]; } FVP_GENERIC_TIMER_DESCRIPTION_TABLES; #pragma pack () @@ -45,27 +94,28 @@ FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { FVP_GENERIC_TIMER_DESCRIPTION_TABLES, EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), - 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress + FVP_SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress EFI_ACPI_RESERVED_DWORD, // UINT32 Reserved - SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 SecurePL1TimerFlags - NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 NonSecurePL1TimerFlags - VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 VirtualTimerFlags - NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 NonSecurePL2TimerFlags - 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress - 1, // UINT32 PlatformTimerCount + FVP_SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FVP_NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FVP_VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FVP_NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + FVP_CNT_READ_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress + FVP_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { EFI_ACPI_6_1_GTDT_GT_BLOCK, // UINT8 Type sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT16 Length - + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), + + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE) * + FVP_TIMER_FRAMES_COUNT, EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved - GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase - 1, // UINT32 GTBlockTimerCount + FVP_GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase + FVP_TIMER_FRAMES_COUNT, // UINT32 GTBlockTimerCount sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset }, { @@ -74,13 +124,37 @@ FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3] - GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX - 0xFFFFFFFFFFFFFFFF, // UINT64 CntEL0BaseX - GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV - 0, // UINT32 GTxPhysicalTimerFlags + FVP_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 CntBaseX + FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 CntEL0BaseX + FVP_GT_BLOCK_FRAME0_GSIV, // UINT32 GTxPhysicalTimerGSIV + FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags 0, // UINT32 GTxVirtualTimerGSIV 0, // UINT32 GTxVirtualTimerFlags - 0 // UINT32 GTxCommonFlags + FVP_GTX_COMMON_FLAGS // UINT32 GTxCommonFlags + }, + { + 1, // UINT8 GTFrameNumber + {EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3] + FVP_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX + FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 CntEL0BaseX + FVP_GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV + FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags + 0, // UINT32 GTxVirtualTimerGSIV + 0, // UINT32 GTxVirtualTimerFlags + FVP_GTX_COMMON_FLAGS // UINT32 GTxCommonFlags + } + }, + { + { + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof(EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), // UINT16 Length + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved + FVP_SBSA_WATCHDOG_REFRESH_BASE, // UINT64 RefreshFramePhysicalAddress + FVP_SBSA_WATCHDOG_CONTROL_BASE, // UINT64 WatchdogControlFramePhysicalAddress + FVP_SBSA_WATCHDOG_GSIV, // UINT32 WatchdogTimerGSIV + FVP_SBSA_WATCHDOG_FLAGS // UINT32 WatchdogTimerFlags } } }; -- 2.5.5

8 years, 4 months

SATA AHCI issue

by Shaveta Leekha

Hi, I have been working on support for AHCI controller for my ARMv8 platform. For that I have integrated my PciEmulation code and SataControllerDxe driver code with MdeModulePkg/Bus/Ata. But facing one issue, this is same issue reported by Jan Dabros(in To list) sometime back. Setting PxCMD.FRE bit of command register doesn't cause PxCMD.FR to be set to '1' even after "500msec" timeout. (As per AHCI spec 1.3 : When PxCMD.FRE is set, it causes PxCMD.FR to be set to '1' ) Is it correct to just comment out following code part from "MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c" file, "AhciModeInitialization" function: As Initialization timeouts is occurring in below part of code: // // Enable FIS Receive DMA engine for the first D2H FIS. // Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD; AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE); Status = AhciWaitMmioSet ( PciIo, Offset, EFI_AHCI_PORT_CMD_FR, EFI_AHCI_PORT_CMD_FR, EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT ); if (EFI_ERROR (Status)) { continue; } And if above code is commented out, then SATA stack works completely fine. What can be the problem? Thank you in advance for your time! Best regards, Shaveta

8 years, 4 months

[linaro-uefi] Two write to EOIR in a single interrupt

by Heyi Guo

Hi folks, We can see that in a single timer interrupt, there will be two writes to EOIR, one in timer interrupt handler, the other in GIC IRQ handler. The question is: does two writes to EOIR have any side effect? From GIC specification (ARM IHI 0069B (ID121715)), we can see below text about writing EOIR (page 205): A write to this register must correspond to the most recent valid read from an Interrupt Acknowledge Register for which there has not been a priority drop and that this identifier was read from ICC_IAR1_EL1 while operating in the same Security state as that in which the write occurs, otherwise the system behavior is UNPREDICTABLE. A valid read is a read that returns a valid interrupt ID, that is not a special INTID. For GICv2, we can also see below text about EOIR: For nested interrupts, the order of writes to this register must be the reverse of the order of interrupt acknowledgement. Behavior is UNPREDICTABLE if: • This ordering constraint is not maintained. *• The value written to this register does not match an active interrupt, or the ID of a spurious interrupt. * • The value written to this register does not match the last valid interrupt value read from GICC_IAR. When we issue the 1st EOIR, the interrupt will be deactivated, so it is not in active state anymore for the 2nd write of EOIR. Could anyone help to confirm whether it is OK to keep the 2nd write of EOIR? And how to explain the above paragraphs from GIC specification? Thanks and regards. Heyi

8 years, 4 months

[PATCH v2 0/8] Armada 7040 serdes support and network preparation

by Marcin Wojtas

Hi, Here is the second version of a patchset adding network preparation support for Armada 7040 SoC, i.e. SerDes, MDIO and PHY libraries. All comments from v1 are included, more details in changelog below. The patches are also available in the public github tree: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v1 -> v2 * ComPhyLib - Remove obsolete support for Z1 chip - delete SerDes init sequence, which isn't longer executed - Break up long functions with lanes' power up sequence into smaller (atomic) ones - Update documenatation - Minor changes in namings * MDIO and PHY Library - Change MdioRead interface (use better approach of error handling) - Renaming and sorting - Improve commit messages * Others - Rebase on top of 07/30 linaro-opp master branch Bartosz Szczepanek (6): Platforms/Marvell: Include common network modules on Armada SoC's Platforms/Marvell: Add MARVELL_MDIO_PROTOCOL Platforms/Marvell: Enable MDIO driver on Armada70x0 platform Platforms/Marvell: Add MARVELL_PHY_PROTOCOL Drivers/Net: Create PHY driver for Marvell platforms Platforms/Marvell: Enable PHY driver on Armada70x0 platform Jan Dąbroś (2): Platforms/Marvell: Create ComPhyLib Platforms/Marvell: Enable ComPhy Lib for Armada70x0 platform Documentation/Marvell/PortingGuide/ComPhy.txt | 85 ++ Documentation/Marvell/PortingGuide/Mdio.txt | 7 + Documentation/Marvell/PortingGuide/Phy.txt | 45 + Drivers/Net/MdioDxe/MvMdioDxe.c | 237 +++++ Drivers/Net/MdioDxe/MvMdioDxe.h | 57 ++ Drivers/Net/MdioDxe/MvMdioDxe.inf | 69 ++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 429 ++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 194 ++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 71 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 20 +- Platforms/Marvell/Armada/Armada70x0.dsc | 20 + Platforms/Marvell/Armada/Armada70x0.fdf | 14 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 4 +- .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 1 + Platforms/Marvell/Include/Library/MvComPhyLib.h | 43 + Platforms/Marvell/Include/Protocol/Mdio.h | 66 ++ Platforms/Marvell/Include/Protocol/MvPhy.h | 103 ++ Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 1023 ++++++++++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 275 ++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 452 +++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 109 +++ Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 +++ Platforms/Marvell/Marvell.dec | 60 ++ 23 files changed, 3513 insertions(+), 3 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/ComPhy.txt create mode 100644 Documentation/Marvell/PortingGuide/Mdio.txt create mode 100644 Documentation/Marvell/PortingGuide/Phy.txt create mode 100644 Drivers/Net/MdioDxe/MvMdioDxe.c create mode 100644 Drivers/Net/MdioDxe/MvMdioDxe.h create mode 100644 Drivers/Net/MdioDxe/MvMdioDxe.inf create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf create mode 100644 Platforms/Marvell/Include/Library/MvComPhyLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Mdio.h create mode 100644 Platforms/Marvell/Include/Protocol/MvPhy.h create mode 100755 Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c -- 1.8.3.1

8 years, 4 months

[PATCH] Platforms/ARM/Juno: limit ACPI support to v5.0 and higher

by Sudeep Holla

The ACPI spec predates the AARCH64 architecture by 5 versions, so there is no point in supporting anything below v5.0. So set the PCD that controls the ACPI table generation to the appropriate value. Based on the commit e0692789058e ("ArmVirtPkg/ArmVirtQemu: limit ACPI support to v5.0 and higher") in the upstream TianoCore by Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheu...(a)linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/ArmJuno.dsc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 45d9950decba..2e9ccfbad396 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -174,6 +174,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + [PcdsPatchableInModule] # Console Resolution (Full HD) gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920 -- 2.7.4

8 years, 4 months

[PATCH] Platforms/ARM/Juno: Add support for ACPI 6.0 LPI(Low Power Idle) states

by Sudeep Holla

ACPI 6.0 introduced LPI(Low Power Idle) states that provides an alternate method to describe processor idle states. LPI extensions leverages the processor container device(again introduced in ACPI 6.0) allowing to express which parts of the system are affected by a given LPI state. It defines the local power states for each node in a hierarchical processor topology. The OSPM can use _LPI object to select a local power state for each level of processor hierarchy in the system. This patch adds LPI support on Juno. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/AcpiTables/Dsdt.asl | 232 ++++++++++++++++++++++++++++++--- 1 file changed, 213 insertions(+), 19 deletions(-) Hi Lief, The support in the kernel is now added(latest mainline as of today) and is enabled in defconfig. It's easy to test, just examine the sysfs entries: /sys/devices/system/cpu/cpu*/cpuidle/state*/desc - Describes the cpuidle state /sys/devices/system/cpu/cpu*/cpuidle/state*/{usage,time} - Should keep ticking with time signifying that the idle states are entered and exited correctly Regards, Sudeep diff --git a/Platforms/ARM/Juno/AcpiTables/Dsdt.asl b/Platforms/ARM/Juno/AcpiTables/Dsdt.asl index c324ded471f2..07e32bae21f8 100644 --- a/Platforms/ARM/Juno/AcpiTables/Dsdt.asl +++ b/Platforms/ARM/Juno/AcpiTables/Dsdt.asl @@ -19,29 +19,223 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O // // A57x2-A53x4 Processor declaration // - Device(CPU0) { // A53-0: Cluster 1, Cpu 0 - Name(_HID, "ACPI0007") - Name(_UID, 0) + Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) { + If (!(Arg1 == One)) { + STS0 &= ~0x1F + STS0 |= 0x0A + } Else { + If ((CAP0 & 0x100)) { + CAP0 &= ~0x100 /* No support for OS Initiated LPI */ + STS0 &= ~0x1F + STS0 |= 0x12 + } + } + } Else { + STS0 &= ~0x1F + STS0 |= 0x06 + } + Return (Arg3) } - Device(CPU1) { // A53-1: Cluster 1, Cpu 1 - Name(_HID, "ACPI0007") + Device (CLU0) { // Cluster0 state + Name(_HID, "ACPI0010") Name(_UID, 1) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + Package() { // Power Gating state for Cluster + 2500, // Min residency (uS) + 1150, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No Parent State + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CluPwrDn" + }, + }) + Name(PLPI, Package() { + 0, // Version + 1, // Level Index + 2, // Count + Package() { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + Package() { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 1, // Parent node can be in any state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00010000, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CorePwrDn" + }, + }) + Device(CPU0) { // A57-0: Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 4) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU1) { // A57-1: Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 5) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } } - Device(CPU2) { // A53-2: Cluster 1, Cpu 2 - Name(_HID, "ACPI0007") + Device (CLU1) { // Cluster1 state + Name(_HID, "ACPI0010") Name(_UID, 2) - } - Device(CPU3) { // A53-3: Cluster 1, Cpu 3 - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - Device(CPU4) { // A57-0: Cluster 0, Cpu 0 - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - Device(CPU5) { // A57-1: Cluster 0, Cpu 1 - Name(_HID, "ACPI0007") - Name(_UID, 5) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + Package() { // Power Gating state for Cluster + 2500, // Min residency (uS) + 1150, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No Parent State + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CluPwrDn" + }, + }) + Name(PLPI, Package() { + 0, // Version + 1, // Level Index + 2, // Count + Package() { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + Package() { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 1, // Parent node can be in any state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00010000, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CorePwrDn" + }, + }) + Device(CPU2) { // A53-0: Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU3) { // A53-1: Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU4) { // A53-2: Cluster 1, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 2) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU5) { // A53-3: Cluster 1, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 3) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } } // -- 2.7.4

8 years, 4 months

[PATCH 0/8] Armada 7040 serdes support and network preparation

by Marcin Wojtas

Hi, Since basic support of Armada 7040 has been integrated to the tree, here is another part of the platform. Below commits comprise three parts: * ComPhy library - SerDes configuration and multiplexing * MDIO library * PHY library Altogether they are needed for enabling network on Armada 7040 (driver not included in this patchset). The patches are also available in the public github tree: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Bartosz Szczepanek (6): Platforms/Marvell: Include common network modules on Armada SoC's Platforms/Marvell: Add MARVELL_MDIO_PROTOCOL Platforms/Marvell: Enable MDIO driver on Armada70x0 platform Platforms/Marvell: Add MARVELL_PHY_PROTOCOL Drivers/Net: Create PHY driver for Marvell platforms Platforms/Marvell: Enable PHY driver on Armada70x0 platform Jan Dąbroś (2): Platforms/Marvell: Create ComPhyLib Platforms/Marvell: Enable ComPhy Lib for Armada70x0 platform Documentation/Marvell/PortingGuide/ComPhy.txt | 82 +++ Documentation/Marvell/PortingGuide/Mdio.txt | 7 + Documentation/Marvell/PortingGuide/Phy.txt | 45 ++ Drivers/Net/MdioDxe/MdioDxe.c | 235 ++++++ Drivers/Net/MdioDxe/MdioDxe.h | 57 ++ Drivers/Net/MdioDxe/MdioDxe.inf | 68 ++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 439 +++++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 194 +++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 71 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 20 +- Platforms/Marvell/Armada/Armada70x0.dsc | 21 + Platforms/Marvell/Armada/Armada70x0.fdf | 14 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 2 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 1 + Platforms/Marvell/Include/Library/ComPhyLib.h | 43 ++ Platforms/Marvell/Include/Protocol/Mdio.h | 65 ++ Platforms/Marvell/Include/Protocol/Phy.h | 103 +++ Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c | 290 ++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 812 +++++++++++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 277 +++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 457 ++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 111 +++ Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 ++++ Platforms/Marvell/Marvell.dec | 61 ++ 24 files changed, 3606 insertions(+), 1 deletion(-) create mode 100644 Documentation/Marvell/PortingGuide/ComPhy.txt create mode 100644 Documentation/Marvell/PortingGuide/Mdio.txt create mode 100644 Documentation/Marvell/PortingGuide/Phy.txt create mode 100644 Drivers/Net/MdioDxe/MdioDxe.c create mode 100644 Drivers/Net/MdioDxe/MdioDxe.h create mode 100644 Drivers/Net/MdioDxe/MdioDxe.inf create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf create mode 100644 Platforms/Marvell/Include/Library/ComPhyLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Mdio.h create mode 100644 Platforms/Marvell/Include/Protocol/Phy.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c create mode 100755 Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c -- 1.8.3.1

8 years, 4 months

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Linaro-uefi July 2016