Linaro-uefi July 2016

linaro-uefi@lists.linaro.org

17 participants
33 discussions

by Daniil Egranov

The patches are fixing issues with ARP messages and TX recycle buffer overflow. Daniil Egranov (2): OpenPlatformPkg/Lan91xDxe: Fixed ARP broadst message handling OpenPlatformPkg/Lan91xDxe: Fixed TX recycle buffer overflow Drivers/Net/Lan91xDxe/Lan91xDxe.c | 116 +++++++++++++++++++------------------- 1 file changed, 59 insertions(+), 57 deletions(-) -- 2.7.4

8 years, 5 months

[PATCHv4 0/2] ArmJuno: Correct AXI<->PCI translations

by Jeremy Linton

The PCIe PIO translation is incorrect on the Juno, correct that. While we are updating that module correct the comments to more accurately reflect the code and what is actually happening. Jeremy Linton (2): ArmJuno: fix Juno PIO host bridge mapping ArmJuno: Correct AXI->PCIe translation comments .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.4.11

8 years, 5 months

[PATCH] Platforms/Styx: add FvNameGuid to FvMain FV

by Ard Biesheuvel

This adds name GUIDs to the Styx FDFs so that DevicePath references to its contents (i.e., for the UiApp and Shell UEFI applications) are emitted unambiguously rather than as MemoryMapped()/ device path nodes, whose values may change between boots (e.g., if the amount of memory changes, or if the firmware image is updated). Having stable boot entries is preferable, given that the generic BDS code autogenerates entries for the UI app and the shell, but does not clean up the stale outdated ones. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf | 1 + Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf | 1 + 2 files changed, 2 insertions(+) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf index 148c0a694f16..3b2116756439 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf @@ -70,6 +70,7 @@ FV = STYX_EFI ################################################################################ [FV.FvMain] +FvNameGuid = 72b41709-8499-4841-a383-f432de6fce2a BlockSize = 0x40 NumBlocks = 0 # This FV gets compressed so make it just big enough FvAlignment = 16 # FV alignment and FV attributes setting. diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf index 04894d5aa2fd..02e92434813c 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf @@ -70,6 +70,7 @@ FV = STYX_EFI ################################################################################ [FV.FvMain] +FvNameGuid = 94f067ae-2aa6-4b30-aa07-4e47fe518bb8 BlockSize = 0x40 NumBlocks = 0 # This FV gets compressed so make it just big enough FvAlignment = 16 # FV alignment and FV attributes setting. -- 1.9.1

8 years, 5 months

[PATCH v3] ArmJuno: fix Juno PIO host bridge mapping

by Jeremy Linton

The Juno PIO mapping is 8M, so it should be using 32-bit PIO address translation. Further, PIO addresses should start at 0 and be translated to/from the ARM MMIO region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton(a)arm.com> --- .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index 06de6d5..1774e7d 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -72,7 +72,9 @@ HWPciRbInit ( PCI_TRACE ("PCIe Setting up Address Translation"); - PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); // Setup the PCI Configuration Registers // Offset 0a: SubClass 04 PCI-PCI Bridge @@ -82,7 +84,7 @@ HWPciRbInit ( PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations + // PCIE Window 0 -> AXI4 Master 0 Address Translations // TranslationTable = VEXPRESS_ATR_PCIE_WIN0; @@ -107,9 +109,9 @@ HWPciRbInit ( SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); TranslationTable += PCI_ATR_ENTRY_SIZE; - // PCI IO Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); + // PCI IO Support, the PIO space is translated from the ARM MMIO PCI_IO_BASE address to the PIO base address of 0 + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); TranslationTable += PCI_ATR_ENTRY_SIZE; // PCI MEM32 Support -- 2.4.11

8 years, 5 months

[PATCH] ArmJuno: fix Juno PIO host bridge mapping

by Jeremy Linton

The Juno PIO mapping is 8M, so it should be using 32-bit PIO address translation. Futher, PIO addresses should start at 0 and be translated to/from the ARM MMIO region. Signed-off-by: Jeremy Linton <jeremy.linton(a)arm.com> --- .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index 06de6d5..1774e7d 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -72,7 +72,9 @@ HWPciRbInit ( PCI_TRACE ("PCIe Setting up Address Translation"); - PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); // Setup the PCI Configuration Registers // Offset 0a: SubClass 04 PCI-PCI Bridge @@ -82,7 +84,7 @@ HWPciRbInit ( PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations + // PCIE Window 0 -> AXI4 Master 0 Address Translations // TranslationTable = VEXPRESS_ATR_PCIE_WIN0; @@ -107,9 +109,9 @@ HWPciRbInit ( SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); TranslationTable += PCI_ATR_ENTRY_SIZE; - // PCI IO Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); + // PCI IO Support, the PIO space is translated from the ARM MMIO PCI_IO_BASE address to the PIO base address of 0 + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); TranslationTable += PCI_ATR_ENTRY_SIZE; // PCI MEM32 Support -- 2.4.11

8 years, 5 months

[PATCH v2] ArmJuno: fix Juno PIO host bridge mapping

by Jeremy Linton

The Juno PIO mapping is 8M, so it should be using 32-bit PIO address translation. Futher, PIO addresses should start at 0 and be translated to/from the ARM MMIO region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton(a)arm.com> --- .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index 06de6d5..1774e7d 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -72,7 +72,9 @@ HWPciRbInit ( PCI_TRACE ("PCIe Setting up Address Translation"); - PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); // Setup the PCI Configuration Registers // Offset 0a: SubClass 04 PCI-PCI Bridge @@ -82,7 +84,7 @@ HWPciRbInit ( PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations + // PCIE Window 0 -> AXI4 Master 0 Address Translations // TranslationTable = VEXPRESS_ATR_PCIE_WIN0; @@ -107,9 +109,9 @@ HWPciRbInit ( SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); TranslationTable += PCI_ATR_ENTRY_SIZE; - // PCI IO Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); + // PCI IO Support, the PIO space is translated from the ARM MMIO PCI_IO_BASE address to the PIO base address of 0 + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); TranslationTable += PCI_ATR_ENTRY_SIZE; // PCI MEM32 Support -- 2.4.11

8 years, 5 months

[PATCH] Platforms: add resolution for new library class 'ArmMmuLib'

by Ard Biesheuvel

Now that the page table manipulation code has been split off from ArmLib into ArmMmuLib, we need a resolution for this new library class in all platforms. For most platforms, this is simply a matter of adding a new line ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf to a common [LibraryClass] section. For D02/D03, which were users of the special PEI_CORE/PEIM implementation of ArmLib, we drop the reference to this special version from the [LibraryClasses.PEI_CORE] section (since PEI core does use ArmLib but does not use the MMU code), and replace the one in [LibraryClasses.PEIM] with the new ArmMmuPeiLib.inf implementation, which is the new version that takes care not to issue cache maintenance ops on NOR flash. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- This change will be needed as soon as I commit the series 'ArmPkg: refactor MMU handling routines into separate ArmMmuLib', which is good to go from review perspective. If people are ok with this patch, I will merge it at the same time as the series (unless there are other reasons to wait) Since this change is not bisectable anyway (since the EDK2 change and the OPP change both need to occur at the same time), I saw little point in splitting this into several patches. Chips/Hisilicon/Pv660/Pv660.dsc.inc | 4 ++-- Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc | 1 + Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 1 + Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 1 + Platforms/ARM/Juno/ArmJuno.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 + Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc | 1 + 8 files changed, 9 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Pv660/Pv660.dsc.inc b/Chips/Hisilicon/Pv660/Pv660.dsc.inc index 2a0ffac9c72d..029608ceeb78 100644 --- a/Chips/Hisilicon/Pv660/Pv660.dsc.inc +++ b/Chips/Hisilicon/Pv660/Pv660.dsc.inc @@ -65,6 +65,7 @@ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf # Versatile Express Specific Libraries ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf @@ -166,7 +167,6 @@ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibPei.inf [LibraryClasses.common.PEIM] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf @@ -186,7 +186,7 @@ ## Fixed compile error after upgrade to 14.10 PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibPei.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc b/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc index f6606cafb849..2b15d7f5667b 100644 --- a/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc +++ b/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc @@ -34,6 +34,7 @@ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 437286876a31..6b9446a1387d 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -101,6 +101,7 @@ DEFINE DO_KCS = 0 ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index c73bd55c1558..0f8dd814ad15 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -104,6 +104,7 @@ DEFINE DO_KCS = 1 ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 490e08eb9248..4f41fb159f19 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -34,6 +34,7 @@ !include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress.dsc.inc [LibraryClasses.common] + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc index 9daf3c8ff512..ef8fd971e66b 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -39,6 +39,7 @@ [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index 1e871b541c6e..65b14eb793a8 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -42,6 +42,7 @@ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf diff --git a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc b/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc index e24df3b7a8df..3c2b767552fa 100644 --- a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc +++ b/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc @@ -32,6 +32,7 @@ [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardLib.inf ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf -- 1.9.1

8 years, 5 months

[PATCH 0/2] Platforms/ARM/Juno: tidy Acpi GTDT

by evan.lloyd＠arm.com

From: Evan Lloyd <evan.lloyd(a)arm.com> These patches make minor source updates to the Juno GTDT. There is no functional change, only source code improvements. Code available at: https://github.com/EvanLloyd/OpenPlatformPkg/tree/GTDTbis_v1 Alexei (1): Platforms/ARM/Juno: fix GTDT compilation error. Evan Lloyd (1): Platforms/ARM/Juno: ameliorate misleading GTDT name. Platforms/ARM/Juno/AcpiTables/Gtdt.aslc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

8 years, 5 months

[PATCH v4 0/4] arm64, xen: add xen_boot support into grup-mkconfig

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> This patchset add xen_boot support into grup-mkconfig for generating xen boot entrances automatically Also update the docs/grub.texi for new xen_boot commands. This patchset has been tested on Foudation model with a bug fix: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00205.html ChangeLog: v4: http://lists.gnu.org/archive/html/grub-devel/2016-05/ according to the XSM loading mechanism of Xen(upstreamed), update the introduction of xen_module commands in docs/grub.texi v3: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00314.html reorder the patches update the introduction of xen_module commands in docs/grub.texi v2: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00282.html add "--nounzip" option support in xen_module use "feature_xen_boot" instead of "grub_xen_boot" update the introduction of xen boot commands in docs/grub.texi v1 :first upstream patchset: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00264.html Fu Wei (4): i386,xen: Add xen_hypervisor and xen_module aliases for i386 arm64: add "--nounzip" option support in xen_module command * util/grub.d/20_linux_xen.in: Add xen_boot command support arm64: update the introduction of xen boot commands in docs/grub.texi docs/grub.texi | 33 ++++++++++----------------------- grub-core/loader/arm64/xen_boot.c | 17 +++++++++++++++++ grub-core/loader/i386/xen.c | 7 +++++++ grub-core/normal/main.c | 2 +- util/grub.d/20_linux_xen.in | 13 ++++++++++--- 5 files changed, 45 insertions(+), 27 deletions(-) -- 2.5.5

8 years, 5 months

[PATCH] Platforms/FVP: drop GICv2 support

by Ard Biesheuvel

Now that ARM Trusted Firmware has dropped support for the legacy VE memory map (which means it can only support the FVP Foundation model in GICv3 mode), and runs the GICv3 in native mode by default on the secure side (which prevents a GICv2 compatible GICv3 from being driven in v2 mode on the non-secure side), there is little point in keeping the GICv2 legacy ifdefs in the FVP dsc. So remove them. Note that we will still be able to support FVP Base in GICv2 mode after applying this patch, but running it will require a special build of ATF with FVP_GICV2 defined. Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 9 --------- 1 file changed, 9 deletions(-) diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index 1e871b541c6e..3d67823cf5db 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -82,10 +82,6 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE -!ifdef ARM_FVP_GICV3_WITH_V2_LEGACY - gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE -!endif - [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Fixed Virtual Platform" gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ARM-FVP" @@ -154,14 +150,9 @@ # # ARM General Interrupt Controller # -!ifdef ARM_FVP_LEGACY_GICV2_LOCATION - gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000 -!else gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x2f100000 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 -!endif # # ARM OS Loader -- 1.9.1

8 years, 5 months

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Linaro-uefi July 2016