On 2 May 2016 at 16:58, Duran, Leo leo.duran@amd.com wrote:
-----Original Message----- From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] Sent: Monday, May 02, 2016 9:45 AM To: Duran, Leo leo.duran@amd.com Cc: linaro-uefi@lists.linaro.org; leif.lindholm@linaro.org; ricardo.salveti@linaro.org Subject: Re: [RFC PATCH 6/7] Platforms/Styx/FdtDxe: boot secondaries straight into OS pen
On 2 May 2016 at 16:41, Duran, Leo leo.duran@amd.com wrote:
Ard, Wow... I do like the way this is going! Q: Have you booted all core using DO_PSCI=0?
Into the pen, yes, but not all the way into the OS. I was getting an SError which turned out to be unrelated to these changes.
All, BTW, I'd like to propose that we require PcdTrustedFWSupport = TRUE (for EL3 handling) This way, we could then can drop the ISCP code that
brings cores out of reset into UEFI.
Yes, I think that is reasonable. That would also allow us to move this to generic code, i.e., a generic DXE driver that implements ACPI parking protocol/spin-table on top of PSCI. For now, I would like to see it working first, especially since the MpCore stuff is somewhat broken if you run your XIP PEI code from DRAM
Ummh... the baseline code (prior this patch series) used to be able to boot secondary cores, using DO_PSCI=0 and the patched MainMPCore.c. However, the secondary boot path now gets a "Synchronous Exception" when it invokes GetMpCoreInfo().
I have not tried exercising the (DO_PSCI=0) code path in quite a while, so I don't know when it got broken. (I suspect due to change in EDK2, because the Styx code has not changed)
That's a shame. I don't have the bandwidth currently to dig deeper into this than I already have. In any case, using MpCore with SEC and PEI executing from RAM is a configuration we should stop using asap, so I think you should consider DO_PSCI=0 broken for now, even without the synchronous exception you reported.