Re: [Linaro-uefi] [PATCH 05/28] D02/D03/Dsdt/hns: fix the bug of serdes loopback

On Mon, Nov 14, 2016 at 07:29:32PM +0800, Heyi Guo wrote:

The register of Hilink needs to be configed, but the current procedure does not do that. The temporary variable to be set to register is wrong, it must be Local0 instead of Local1.

Review-by: Graeme Gregory graeme.gregory@linaro.org

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan yankejian@huawei.com

---

.../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 20 ++++++++++---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 12 ++++++------ 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index b62ee45..d8d453a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -126,16 +126,16 @@ Scope(_SB) OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) Field(H4LR, DWordAcc, NoLock, Preserve) { H4L0, 16, // port0

•      H4R0, 16,    //RESERVED
  

•      , 16,    //RESERVED
       Offset (0x400),
       H4L1, 16,    // port1
  

•      H4R1, 16,    //RESERVED
  

•      , 16,    //RESERVED
       Offset (0x800),
       H4L2, 16,    // port2
  

•      H4R2, 16,    //RESERVED
  

•      , 16,    //RESERVED
       Offset (0xc00),
       H4L3, 16,    // port3
  

•      H4R3, 16,    //RESERVED
  

•      , 16,    //RESERVED
     }
  

  OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) Field(H3LR, DWordAcc, NoLock, Preserve) {

@@ -266,42 +266,42 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)

•      Store (Local1, H4L0)
  

•      Store (Local0, H4L0)
     }
     case (0x1){
       Store (0, HSEL)
       Store (H4L1, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H4L1)
  

•      Store (Local0, H4L1)
     }
     case (0x2){
       Store (0, HSEL)
       Store (H4L2, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H4L2)
  

•      Store (Local0, H4L2)
     }
     case (0x3){
       Store (0, HSEL)
       Store (H4L3, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H4L3)
  

•      Store (Local0, H4L3)
     }
     case (0x4){
       Store (3, HSEL)
       Store (H3L2, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H3L2)
  

•      Store (Local0, H3L2)
     }
     case (0x5){
       Store (3, HSEL)
       Store (H3L3, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H3L3)
  

•      Store (Local0, H3L3)
     }
   }
  

  }

diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 2b08a1f..881aa14 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -250,37 +250,37 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)

•      Store (Local1, H4L0)
  

•      Store (Local0, H4L0)
     }
     case (0x1){
       Store (H4L1, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H4L1)
  

•      Store (Local0, H4L1)
     }
     case (0x2){
       Store (H4L2, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H4L2)
  

•      Store (Local0, H4L2)
     }
     case (0x3){
       Store (H4L3, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H4L3)
  

•      Store (Local0, H4L3)
     }
     case (0x4){
       Store (H3L2, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H3L2)
  

•      Store (Local0, H3L2)
     }
     case (0x5){
       Store (H3L3, Local1)
       And (Local1, 0xfffffbff, Local1)
       Or (Local0, Local1, Local0)
  

•      Store (Local1, H3L3)
  

•      Store (Local0, H3L3)
     }
   }
  

  }

-- 1.9.1