On 2 November 2016 at 21:52, Marcin Wojtas mw@semihalf.com wrote:
Hi Ard,
2016-11-02 21:55 GMT+01:00 Ard Biesheuvel ard.biesheuvel@linaro.org:
On 2 November 2016 at 20:02, Jan Dąbroś jsd@semihalf.com wrote:
Hi Ard,
I have a question regarding DmaLib implementation. We took a deeper look at AHCI controller and it will be coherent on newer SoC version - as for now, we have non-coherent one and it's not working with NullDmaLib, whereas everything is ok when ArmDmaLib is used. In the same time, tests show that XHCI works fine both with NullDmaLib and ArmDmaLib. My question is, what are the contraindications for using ArmDmaLib for coherent devices if it is working good on them also? This solution seems to be covering for every case (contrary to NullDmaLib).
No, ArmDmaLib is fundamentally incompatible with coherent devices. The code performs a cache invalidate for data written by the bus master, since on non-coherent systems, this may be necessary to get rid of stale cachelines that shadow the incoming data. On coherent devices, the device will write to the cache, not to main memory, and so this cache invalidation will discard the data coming from the device.
Could you help understand then, how come a coherent device (XHCI) can work both with ArmDmaLib/NullDmaLib, whereas non-coherent device (AHCI) can work only with ArmDmaLib? In other words, how do you suggest to proceed here?
In case we switch to NullDmaLib, what's suggested solution of handling non-coherent devices? Do you know of any reference PciEmulation driver that deals with such situation?
I am working on a generic solution for this: https://lists.01.org/pipermail/edk2-devel/2016-October/003842.html