Re: [Linaro-uefi] [PATCH edk2-platforms v3 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device.

On Thu, Sep 21, 2017 at 06:59:57PM +0800, Heyi Guo wrote:

From: Ming Huang waip23@foxmail.com

1. Because Hi161x chip doesn't support "ARI Forwarding Enable" function, BIOS will enumerate 32 same devices (Device Number 0~31) when attach a Non-ARI capable device in the RP. Hi161x chip will not fix it, need BIOS patch.
2. Just enlarge iatu for those root port with ARI capable device attached, Non-ARI capable device's RP, keep iatu limitation.
3. Remove previous temporary solution as below commit id: "7d157da88852cc91df2b11b10ade2edbbfbe77da"

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason zhang zhangjinsong2@huawei.com

Please adjust + add email addresses. The content below is fine.

/ Leif

---

Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 + Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++ Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 79 ++++++++++++++++++++ 3 files changed, 87 insertions(+)

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index e3d3988..9fa3f84 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -839,6 +839,7 @@ NotifyPhase( case EfiPciHostBridgeEndEnumeration: PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n");

• EnlargeAtuConfig0 (This); break;

case EfiPciHostBridgeBeginBusAllocation: diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index cddda6b..c04361f 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -401,6 +401,9 @@ PreprocessController ( #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL +#define INVALID_CAPABILITY_00 0x00 +#define INVALID_CAPABILITY_FF 0xFF +#define PCI_CAPABILITY_POINTER_MASK 0xFC // // Driver Instance Data Prototypes @@ -518,4 +521,8 @@ RootBridgeConstructor ( IN UINT32 Seg ); +VOID +EnlargeAtuConfig0 (

• IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This
• );

#endif diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 10d766a..b57bd51 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -14,6 +14,7 @@ **/ #include "PciHostBridge.h" +#include <IndustryStandard/PciExpress30.h> #include <Library/DevicePathLib.h> #include <Library/DmaLib.h> #include <Library/PciExpressLib.h> @@ -2322,3 +2323,81 @@ RootBridgeIoConfiguration ( return EFI_SUCCESS; } +BOOLEAN +PcieCheckAriFwdEn (

• UINTN PciBaseAddr
• )

+{

• UINT8 PciPrimaryStatus;
• UINT8 CapabilityOffset;
• UINT8 CapId;
• UINT8 TempData;
• PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET);
• if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) {
• CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET);
• CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK;
• while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) {

•  CapId = MmioRead8 (PciBaseAddr + CapabilityOffset);
  

•  if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) {
  

•    break;
  

•  }
  

•  CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1);
  

•  CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK;
  

• }
• } else {
• PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__);
• return FALSE;
• }
• if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) {
• PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__);
• return FALSE;
• }
• TempData = MmioRead16 (PciBaseAddr + CapabilityOffset +

•                      EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET);
  

• TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING;
• if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) {
• return TRUE;
• } else {
• return FALSE;
• }

+}

+VOID +EnlargeAtuConfig0 (

• IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This
• )

+{

• UINTN RbPciBase;
• UINT64 MemLimit;
• LIST_ENTRY *List;
• PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
• PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
• PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n");
• HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
• List = HostBridgeInstance->Head.ForwardLink;
• while (List != &HostBridgeInstance->Head) {
• PCIE_DEBUG ("HostBridge has data.\n");
• RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
• RbPciBase = RootBridgeInstance->RbPciBar;
• // Those ARI FWD Enable Root Bridge, need enlarge iatu window.
• if (PcieCheckAriFwdEn (RbPciBase)) {

•  MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam,
  

•                                RootBridgeInstance->BusBase + 2, 0, 0, 0)
  

•               - 1;
  

•  MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1);
  

•  MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
  

• }
• List = List->ForwardLink;
• }

+}

1.9.1