On Thu, Aug 11, 2016 at 11:51:38AM +0200, Marcin Wojtas wrote:
From: Bartosz Szczepanek bsz@semihalf.com
MvPhyDxe implements support for Marvell 1512 PHYs. MARVELL_PHY_PROTOCOL is produced in order to provide Status and Initialize functions to network controller drivers. This driver requires MARVELL_MDIO_PROTOCOL to communicate with PHY device.
Several PCDs were added to enable PHY ids and connection types configuration. These are described in attached documentation.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bartosz Szczepanek bsz@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/Phy.txt | 45 +++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 432 +++++++++++++++++++++++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 194 +++++++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 71 +++++ Platforms/Marvell/Marvell.dec | 5 + 5 files changed, 747 insertions(+) create mode 100644 Documentation/Marvell/PortingGuide/Phy.txt create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
diff --git a/Documentation/Marvell/PortingGuide/Phy.txt b/Documentation/Marvell/PortingGuide/Phy.txt new file mode 100644 index 0000000..69dae02 --- /dev/null +++ b/Documentation/Marvell/PortingGuide/Phy.txt @@ -0,0 +1,45 @@ +PHY driver configuration +------------------------ +MvPhyDxe provides basic initialization and status routines for Marvell PHYs. +Currently only 1512 series PHYs are supported. Following PCDs are required:
- gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
- (list of values corresponding to PHY_CONNECTION enum)
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
- (boolean - if true, driver waits for autonegotiation on startup)
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds
- (list of values corresponding to MV_PHY_DEVICE_ID enum)
+PHY_CONNECTION enum type is defined as follows:
- typedef enum {
+0 PHY_CONNECTION_RGMII, +1 PHY_CONNECTION_RGMII_ID, +2 PHY_CONNECTION_RGMII_TXID, +3 PHY_CONNECTION_RGMII_RXID, +4 PHY_CONNECTION_SGMII, +5 PHY_CONNECTION_RTBI, +6 PHY_CONNECTION_XAUI, +7 PHY_CONNECTION_RXAUI
- } PHY_CONNECTION;
+MV_PHY_DEVICE_ID:
- typedef enum {
+0 MV_PHY_DEVICE_1512,
- } MV_PHY_DEVICE_ID;
+It should be extended when adding support for other PHY +models.
+Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be:
- gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 }
+with disabled autonegotiation:
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+assuming, that PHY models are 1512:
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
diff --git a/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c new file mode 100644 index 0000000..fb96d8b --- /dev/null +++ b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c @@ -0,0 +1,432 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd.
+Marvell BSD License Option
+If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#include <Protocol/DriverBinding.h> +#include <Protocol/Mdio.h> +#include <Protocol/MvPhy.h>
+#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h>
+#include "MvPhyDxe.h"
+#define TIMEOUT 500
+STATIC MARVELL_MDIO_PROTOCOL *Mdio;
+STATIC MV_PHY_DEVICE MvPhyDevices[] = {
- { MV_PHY_DEVICE_1512, MvPhyInit1512 },
- { 0, NULL }
+};
+EFI_STATUS +MvPhyStatus (
- IN CONST MARVELL_PHY_PROTOCOL *This,
- IN PHY_DEVICE *PhyDev
- );
+EFI_STATUS +MvPhyReset (
- IN UINT32 PhyAddr
- )
+{
- UINT32 Reg = 0;
- INTN timeout = TIMEOUT;
- Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg);
- Reg |= BMCR_RESET;
- Mdio->Write(Mdio, PhyAddr, MII_BMCR, Reg);
- while ((Reg & BMCR_RESET) && timeout--) {
- Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg);
- gBS->Stall(1000);
- }
- if (Reg & BMCR_RESET) {
- DEBUG((DEBUG_ERROR, "PHY reset timed out\n"));
- return EFI_TIMEOUT;
- }
- return EFI_SUCCESS;
+}
+/* Marvell 88E1111S */ +EFI_STATUS +MvPhyM88e1111sConfig (
- IN PHY_DEVICE *PhyDev
- )
+{
- UINT32 Reg;
- if ((PhyDev->Connection == PHY_CONNECTION_RGMII) ||
(PhyDev->Connection == PHY_CONNECTION_RGMII_ID) ||(PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) ||(PhyDev->Connection == PHY_CONNECTION_RGMII_TXID)) {- Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg);
- if ((PhyDev->Connection == PHY_CONNECTION_RGMII) ||
(PhyDev->Connection == PHY_CONNECTION_RGMII_ID)) {Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);- } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) {
Reg &= ~MIIM_88E1111_TX_DELAY;Reg |= MIIM_88E1111_RX_DELAY;- } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID) {
Reg &= ~MIIM_88E1111_RX_DELAY;Reg |= MIIM_88E1111_TX_DELAY;- }
- Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg);
- Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg);
- Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
- if (Reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
Reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;- else
Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;- Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg);
- }
- if (PhyDev->Connection == PHY_CONNECTION_SGMII) {
- Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg);
- Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
- Reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
- Reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
- Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg);
- }
- if (PhyDev->Connection == PHY_CONNECTION_RTBI) {
- Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg);
- Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
- Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg);
- Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg);
- Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
MIIM_88E1111_HWCFG_FIBER_COPPER_RES);- Reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
- Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg);
- /* soft reset */
- MvPhyReset(PhyDev->Addr);
- Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg);
- Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
MIIM_88E1111_HWCFG_FIBER_COPPER_RES);- Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;- Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg);
- }
- Mdio->Read(Mdio, PhyDev->Addr, MII_BMCR, &Reg);
- Reg |= (BMCR_ANENABLE | BMCR_ANRESTART);
- Reg &= ~BMCR_ISOLATE;
- Mdio->Write(Mdio, PhyDev->Addr, MII_BMCR, Reg);
- /* soft reset */
- MvPhyReset(PhyDev->Addr);
- MvPhyReset(PhyDev->Addr);
- return EFI_SUCCESS;
+}
+EFI_STATUS +MvPhyParseStatus (
- IN PHY_DEVICE *PhyDev
- )
+{
- UINT32 Data;
- UINT32 Speed;
- Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data);
- if ((Data & MIIM_88E1xxx_PHYSTAT_LINK) &&
- !(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
- INTN i = 0;
- DEBUG((DEBUG_ERROR,"MvPhyDxe: Waiting for PHY realtime link"));
- while (!(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {DEBUG((DEBUG_ERROR," TIMEOUT !\n"));PhyDev->LinkUp = FALSE;break;}if ((i++ % 1000) == 0)DEBUG((DEBUG_ERROR, "."));gBS->Stall(1000);Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data);- }
- DEBUG((DEBUG_ERROR," done\n"));
- gBS->Stall(500000);
- } else {
- if (Data & MIIM_88E1xxx_PHYSTAT_LINK) {
DEBUG((DEBUG_ERROR, "MvPhyDxe: link up, "));PhyDev->LinkUp = TRUE;- } else {
DEBUG((DEBUG_ERROR, "MvPhyDxe: link down, "));PhyDev->LinkUp = FALSE;- }
- }
- if (Data & MIIM_88E1xxx_PHYSTAT_DUPLEX) {
- DEBUG((DEBUG_ERROR, "full duplex, "));
- PhyDev->FullDuplex = TRUE;
- } else {
- DEBUG((DEBUG_ERROR, "half duplex, "));
- PhyDev->FullDuplex = FALSE;
- }
- Speed = Data & MIIM_88E1xxx_PHYSTAT_SPEED;
- switch (Speed) {
- case MIIM_88E1xxx_PHYSTAT_GBIT:
- DEBUG((DEBUG_ERROR, "speed 1000\n"));
- PhyDev->Speed = SPEED_1000;
- break;
- case MIIM_88E1xxx_PHYSTAT_100:
- DEBUG((DEBUG_ERROR, "speed 100\n"));
- PhyDev->Speed = SPEED_100;
- break;
- default:
- DEBUG((DEBUG_ERROR, "speed 10\n"));
- PhyDev->Speed = SPEED_10;
- break;
- }
- return EFI_SUCCESS;
+}
+STATIC +VOID +MvPhy1512WriteBits (
- IN UINT32 PhyAddr,
- IN UINT8 RegNum,
- IN UINT16 Offset,
- IN UINT16 Len,
- IN UINT16 Data)
+{
- UINT32 Reg, Mask;
- if ((Len + Offset) >= 16)
- Mask = 0 - (1 << Offset);
- else
- Mask = (1 << (Len + Offset)) - (1 << Offset);
- Mdio->Read(Mdio, PhyAddr, RegNum, &Reg);
- Reg &= ~Mask;
- Reg |= Data << Offset;
- Mdio->Write(Mdio, PhyAddr, RegNum, Reg);
+}
+STATIC +EFI_STATUS +MvPhyInit1512 (
- IN CONST MARVELL_PHY_PROTOCOL *Snp,
- IN UINT32 PhyAddr,
- IN OUT PHY_DEVICE *PhyDev
- )
+{
- UINT32 Data;
- INTN i;
Extra blank line inserted.
- /* Phy configuration */
I could really do with some more description than that. Since we only have numeric values of both the registers being written to and the values being written ... this either needs a high-level description of _what_ is being configured in the PHY, or it needs to have symbolic constants defined.
- if (PhyDev->Connection == PHY_CONNECTION_SGMII) {
- Mdio->Write(Mdio, PhyAddr, 22, 0x00ff);
- Mdio->Write(Mdio, PhyAddr, 17, 0x214B);
- Mdio->Write(Mdio, PhyAddr, 16, 0x2144);
- Mdio->Write(Mdio, PhyAddr, 17, 0x0C28);
- Mdio->Write(Mdio, PhyAddr, 16, 0x2146);
- Mdio->Write(Mdio, PhyAddr, 17, 0xB233);
- Mdio->Write(Mdio, PhyAddr, 16, 0x214D);
- Mdio->Write(Mdio, PhyAddr, 17, 0xCC0C);
- Mdio->Write(Mdio, PhyAddr, 16, 0x2159);
- Mdio->Write(Mdio, PhyAddr, 22, 0x0000);
- Mdio->Write(Mdio, PhyAddr, 22, 0x0012);
- /* Write HWCFG_MODE = SGMII to Copper */
- MvPhy1512WriteBits(PhyAddr, 20, 0, 3, 1);
- /* Phy reset */
- MvPhy1512WriteBits(PhyAddr, 20, 15, 1, 1);
- Mdio->Write(Mdio, PhyAddr, 22, 0);
Make it 0x0000 to match the cases above please.
Best Regards,
Leif