Thanks Great Jan!
I am still struggling to make it work.
In my case also "PxCMD.FR stay unset" so I have removed that test code (as suggested for the time being). Similarly In my case EFI_AHCI_CAP_SAM was set and writing to EFI_AHCI_GHC_ENABLE wasn't not getting performed. So I have "ENABLED AE" also. So the code so far is installing "gEfiAtaPassThruProtocolGuid" Protocol.
But somehow, in " AtaBusDriverBindingSupported" , this protocol is not getting opened. Status = gBS->OpenProtocol ( Controller, &gEfiAtaPassThruProtocolGuid, (VOID **) &AtaPassThru, This->DriverBindingHandle, Controller, EFI_OPEN_PROTOCOL_BY_DRIVER );
Above code throws an error.
Any idea about that?
Thanks and Regards, Shaveta
-----Original Message----- From: Jan Dąbroś [mailto:jsd@semihalf.com] Sent: Friday, May 06, 2016 8:10 PM To: Shaveta Leekha shaveta.leekha@nxp.com Cc: Ard Biesheuvel ard.biesheuvel@linaro.org; Linaro UEFI Mailman List linaro-uefi@lists.linaro.org; Haim Boot hayim@marvell.com; Neta Zur Hershkovits neta@marvell.com Subject: Re: [Linaro-uefi] PciEmulation - problem with AHCI
I am finally able to run SATA on my platform. It turned out that bad working was caused by two independent factors.
1. PxCMD.FR staying unset, what was discussed here It isn't necessary to wait for above bit being set, only necessity is to set PxCMD.FRE, which enable FIS transfers. I didn't find in AHCI Spec anything about polling for PxCMD.FR, but need to dig into deeper.
2. Conditional setting AE bit Below code checks in CAP register if it is necessary to set AE.
Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
if ((Capability & EFI_AHCI_CAP_SAM) == 0) { AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); }
In my case EFI_AHCI_CAP_SAM was set and writing to EFI_AHCI_GHC_ENABLE wasn't performed. This caused defective work of whole controller. AHCI Spec says that setting AE bit should be performed *before* any other writes to AHCI registers, so I think it will be better to perform it before reading CAP registers (and remove 'if' statements). Reference drivers in Linux and Uboot always set AE bit, without any additional conditions.
Patch with above fixes will be submitted for edk2 RFC next week.
Thanks and Regards, Jan
2016-05-06 12:55 GMT+02:00 Jan Dąbroś jsd@semihalf.com:
Let me clear our discussion a little bit.
Checking PxCMD.FR is performed even if there is no device at port.
Because "When PxCMD.FRE is set, it cause PxCMD.FR to be set to ‘1’. Only then HBA receives FISes from the device and copies them into system memory."
In my case, FR is not getting set.
Exactly the same is in my case, setting PxCMD.FRE doesn't cause PxCMD.FR to be set to ‘1’. Since reference driver in Linux doesn't check PxCMD.FR, I assume that it isn't necessary for receiving FISes (I mean that it is enough to set PxCMD.FRE. BTW: "Only then HBA receives FISes from the device and copies them into system memory." is this sentence taken from AHCI Spec?). This assumption lets me comment-out above code, but further in init sequence I have another problem that, data from device isn't copied into system memory.
Do you think that even though PxCMD.FRE is set, receiving FISes is blocked? Do you know what may cause PxCMD.FR to stay unset?
Thanks, Jan