Re: [Linaro-uefi] [PATCH 02/27] Hisilicon/PCIe: extend support for maximum 8 root ports

On Thu, Nov 10, 2016 at 09:51:04PM +0800, Heyi Guo wrote:

1.Hi1616 has 8 root ports for each SOC (Host bridge), so we first extend PCIe related modules to support maximum 8 root ports. And the Pcie related base addresses are different between Hi1610 and Hi1616, so we move the Pcie address definitions to PlatformPciLib which is a platform lib. 2.PCIE_MAX_ROOTBRIDGE and PCIE_MAX_PORT_NUM are duplicated macro difinitions; unify to use PCIE_MAX_ROOTBRIDGE only. 3.PCIE_MAX_HOSTBRIDGE and PCIE_HOST_BRIDGE_NUM are duplicated; unify to use PCIE_MAX_HOSTBRIDGE.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org

Thanks Heyi - this is a major improvement, not just against the previous version, but of the existing code.

Reviewed-by: Leif Lindholm leif.lindholm@linaro.org

---

.../Drivers/PciHostBridgeDxe/PciHostBridge.c | 216 ++++++++++++++++++++- .../Hi1610/Drivers/PcieInit1610/PcieInit.c | 59 +++++- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 120 ++++++------ .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 13 +- .../Hi1610/Drivers/PcieInit1610/PcieKernelApi.h | 2 - Chips/Hisilicon/HisiPkg.dec | 110 +++++++++++ Chips/Hisilicon/Include/Library/PlatformPciLib.h | 140 +++++++++++-- .../D02/Library/PlatformPciLib/PlatformPciLib.inf | 118 ++++++++++- .../D03/Library/PlatformPciLib/PlatformPciLib.c | 8 + .../D03/Library/PlatformPciLib/PlatformPciLib.inf | 118 ++++++++++- 10 files changed, 791 insertions(+), 113 deletions(-)

diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index ccc263e..a970da6 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -30,12 +30,20 @@ UINT64 RootBridgeAttribute[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE,

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

  }, { //Host Bridge1 EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE,

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

  } };

@@ -136,6 +144,102 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] 0 } }

• },
• /* Port 4 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A07),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 5 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A08),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 6 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A09),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 7 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A0A),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

  }

}, { // Host Bridge1 @@ -150,7 +254,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) } },

•    EISA_PNP_ID(0x0A07),
  

•    EISA_PNP_ID(0x0A0B),
     0
   },
  

@@ -174,7 +278,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) } },

•    EISA_PNP_ID(0x0A08),
  

•    EISA_PNP_ID(0x0A0C),
     0
   },
  

@@ -198,7 +302,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) } },

•    EISA_PNP_ID(0x0A09),
  

•    EISA_PNP_ID(0x0A0D),
     0
   },
  

@@ -222,7 +326,103 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) } },

•    EISA_PNP_ID(0x0A0A),
  

•    EISA_PNP_ID(0x0A0E),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 4 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A0F),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 5 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A10),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 6 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A11),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 7 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A12),
     0
   },
  

@@ -286,7 +486,6 @@ InitializePciHostBridge ( if (!OemIsMpBoot()) { PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);

• PcieRootBridgeMask &= 0xf; } else {

@@ -297,9 +496,10 @@ InitializePciHostBridge ( // // Create Host Bridge Device Handle //

• //Each Host Bridge have 8 Root Bridges max, every bits of 0xFF(8 bit) stands for the according PCIe Port
• //is enable or not for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) {

• if (((PcieRootBridgeMask >> (4 * Loop1)) & 0xF ) == 0) {

• if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) { continue; }

@@ -326,7 +526,7 @@ InitializePciHostBridge ( // Create Root Bridge Device Handle in this Host Bridge // for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {

•  if (!(((PcieRootBridgeMask >> (4 * Loop1)) >> Loop2 ) & 0x01)) {
  

•  if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) {
     continue;
   }
  

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c index 284fa3f..5fc0ead 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c @@ -17,13 +17,14 @@ #include <Library/UefiBootServicesTableLib.h> #include <Library/PcdLib.h> #include <Library/OemMiscLib.h> +#include <Library/PlatformPciLib.h> extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value); extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port); extern EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg); -PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] = +PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_ROOTBRIDGE] = { //Port 0 { @@ -69,6 +70,46 @@ PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] = }, },

• //Port 4
• {

•    0x4,                        //Portindex
  

•    {
  

•        PCIE_ROOT_COMPLEX,      //PortType
  

•        PCIE_WITDH_X8,          //PortWidth
  

•        PCIE_GEN3_0,            //PortGen
  

•    },
  

• },
• //Port 5
• {

•    0x5,                        //Portindex
  

•    {
  

•        PCIE_ROOT_COMPLEX,      //PortType
  

•        PCIE_WITDH_X8,          //PortWidth
  

•        PCIE_GEN3_0,            //PortGen
  

•    },
  

• },
• //Port 6
• {

•    0x6,                        //Portindex
  

•    {
  

•        PCIE_ROOT_COMPLEX,      //PortType
  

•        PCIE_WITDH_X8,          //PortWidth
  

•        PCIE_GEN3_0,            //PortGen
  

•    },
  

• },
• //Port 7
• {

•    0x7,                        //Portindex
  

•    {
  

•        PCIE_ROOT_COMPLEX,      //PortType
  

•        PCIE_WITDH_X8,          //PortWidth
  

•        PCIE_GEN3_0,            //PortGen
  

•    },
  

• },

}; EFI_STATUS @@ -88,7 +129,6 @@ PcieInitEntry ( if (!OemIsMpBoot()) { PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);

•    PcieRootBridgeMask &= 0xf;
  

  } else {

@@ -96,12 +136,15 @@ PcieInitEntry ( } soctype = PcdGet32(Pcdsoctype);

• for (HostBridgeNum = 0; HostBridgeNum < PCIE_HOST_BRIDGE_NUM; HostBridgeNum++)
• {

•    for (Port = 0; Port < PCIE_MAX_PORT_NUM; Port++)
  

•    {
  

•        if (!(((( PcieRootBridgeMask >> (4 * HostBridgeNum))) >> Port) & 0x1))
  

•        {
  

• for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) {

•    for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) {
  

•        /*
  

•           Host Bridge may contain lots of root bridges.
  

•           Each Host bridge have PCIE_MAX_ROOTBRIDGE root bridges
  

•           PcieRootBridgeMask have PCIE_MAX_ROOTBRIDGE*HostBridgeNum bits,
  

•           and each bit stands for this PCIe Port is enable or not
  

•        */
  

•        if (!(((( PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * HostBridgeNum))) >> Port) & 0x1)) {
             continue;
         }
  

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 39b9ea7..e58d87c 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -19,23 +19,20 @@ #include <Library/BaseLib.h> #include <Library/BaseMemoryLib.h> #include <Library/IoLib.h> +#include <Library/PlatformPciLib.h> #include <Library/TimerLib.h> #define PCIE_SYS_REG_OFFSET 0x1000 static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; -UINT64 pcie_subctrl_base_1610[2] = {0xa0000000, 0xb0000000}; UINT64 io_sub0_base = 0xa0000000; UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000}; #define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000)) -UINT64 PCIE_APB_SLAVE_BASE_1610[2][4] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000},

•                                     {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}};
  

-UINT64 PCIE_PHY_BASE_1610[2][4] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000},

•                                {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}};
  

UINT32 loop_test_flag[4] = {0,0,0,0}; UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR; #define PcieMaxLanNum 8 +#define PCIE_PORT_NUM_IN_SICL 4 //SICL: Super IO Cluster extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg; @@ -158,8 +155,7 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) PCIE_CTRL_7_U pcie_ctrl7; UINT32 Value = 0;

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• if (Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }

@@ -236,8 +232,7 @@ EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) PCIE_CTRL_7_U pcie_ctrl7; UINT32 Value = 0;

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• if(Port >= PCIE_MAX_ROOTBRIDGE) { return PCIE_ERR_PARAM_INVALID; }

@@ -269,8 +264,7 @@ EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed) { PCIE_EP_PCIE_CAP12_U pcie_cap12;

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }

@@ -293,8 +287,7 @@ EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width) PCIE_EP_PORT_LOGIC4_U pcie_logic4; PCIE_EP_PORT_LOGIC22_U logic22;

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• if(Port >= PCIE_MAX_ROOTBRIDGE) { return PCIE_ERR_PARAM_INVALID; }

@@ -353,8 +346,7 @@ EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width) PCIE_EP_PORT_LOGIC22_U logic22; PCIE_EEP_PCI_CFG_HDR15_U hdr15; UINT32 Value = 0;

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }

@@ -440,8 +432,7 @@ EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_P { PCIE_CTRL_0_U str_pcie_ctrl_0;

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }

@@ -622,8 +613,8 @@ EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) {

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• UINT32 PortIndexInSicl;
• if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }

@@ -634,14 +625,14 @@ EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port if (0x1610 == soctype) {

•    if(Port <= 2)
  

•    {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x3);
  

•    PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
  

•    if (PortIndexInSicl <= 2) {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
         MicroSecondDelay(0x1000);
     }
     else
     {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
         MicroSecondDelay(0x1000);
     }
  

  }

@@ -664,8 +655,8 @@ EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) {

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• UINT32 PortIndexInSicl;
• if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }

@@ -676,14 +667,14 @@ EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Po if (0x1610 == soctype) {

•    if(Port <= 2)
  

•    {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x3);
  

•    PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
  

•    if (PortIndexInSicl <= 2) {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
         MicroSecondDelay(0x1000);
     }
     else
     {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x3);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG, 0x3);
         MicroSecondDelay(0x1000);
     }
  

  }

@@ -707,20 +698,21 @@ EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Po EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { u_sc_pcie_hilink_pcs_reset_req reset_req;

• UINT32 PortIndexInSicl; if (0x1610 == soctype) {

•    if(Port <= 3)
  

•    {
  

•        reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
  

•        reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
  

•        MicroSecondDelay(0x1000);
  

•    }
  

•    PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
  

•    reset_req.UInt32 = 0;
  

•    reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
  

•    RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
  

•    RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
  

•    reset_req.UInt32 = 0;
  

•    reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
  

•    RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
  

•    //0x1000 microseconds delay comes from experiment and
  

•    //should be fairly enough for this operation.
  

•    MicroSecondDelay(0x1000);
  

  } else {

@@ -742,20 +734,21 @@ EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) EFI_STATUS DeassertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { u_sc_pcie_hilink_pcs_reset_req reset_req;

• UINT32 PortIndexInSicl; if (0x1610 == soctype) {

•    if(Port <= 3)
  

•    {
  

•        reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + 0xacc, reset_req.UInt32);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
  

•        reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
  

•        MicroSecondDelay(0x1000);
  

•    }
  

•    PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
  

•    reset_req.UInt32 = 0;
  

•    reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
  

•    RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32);
  

•    RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
  

•    reset_req.UInt32 = 0;
  

•    reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
  

•    RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
  

•    //0x1000 microseconds delay comes from experimenti
  

•    // and should be fairly enough for this operation.
  

•    MicroSecondDelay(0x1000);
  

  } else {

@@ -779,21 +772,22 @@ EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, { UINT32 reg_clock_disable; UINT32 reg_clock_enable;

• if (Port == 3) {

• UINT32 PortIndexInSicl;
• PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
• if (PortIndexInSicl == 3) { reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG; reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG; } else {

•    reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port);
  

•    reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port);
  

•    reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(PortIndexInSicl);
  

•    reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(PortIndexInSicl);
  

  }

if (0x1610 == soctype) { if (Clock)

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + reg_clock_enable, 0x7);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_enable, 0x7);
     else
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + reg_clock_disable, 0x7);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_disable, 0x7);
  

  } else {

@@ -933,15 +927,14 @@ PciePortInit ( UINT16 Count = 0; UINT32 PortIndex = PcieCfg->PortIndex;

• if(PortIndex >= PCIE_MAX_PORT_NUM)
  

• {
  

• if (PortIndex >= PCIE_MAX_ROOTBRIDGE) {
     return EFI_INVALID_PARAMETER;
  }
  

if (0x1610 == soctype) { mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex];

•     DEBUG((EFI_D_INFO, "Soc type is 1610\n"));
  

•     DEBUG((DEBUG_INFO, "Soc type is 161x\n"));
  }
  else
  {
  

@@ -1024,8 +1017,7 @@ EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable) { PCIE_SYS_CTRL20_U dbi_ro_enable;

• if(Port >= PCIE_MAX_PORT_NUM)
• {

• if (Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 5824b1a..1e8db97 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -19,6 +19,7 @@ #include <Uefi.h> #include <Library/IoLib.h> +#include <Library/PlatformPciLib.h> #include <Regs/HisiPcieV1RegOffset.h> #include "PcieKernelApi.h" @@ -147,12 +148,12 @@ typedef struct { } PCIE_MAPPED_IATU_ADDR; typedef struct {

• BOOLEAN PortIsInitilized[PCIE_MAX_PORT_NUM];
• DRIVER_CFG_U Dev[PCIE_MAX_PORT_NUM];
• VOID *DmaResource[PCIE_MAX_PORT_NUM];
• UINT32 DmaChannel[PCIE_MAX_PORT_NUM][2];
• VOID *RegResource[PCIE_MAX_PORT_NUM];
• VOID *CfgResource[PCIE_MAX_PORT_NUM];

• BOOLEAN PortIsInitilized[PCIE_MAX_ROOTBRIDGE];
• DRIVER_CFG_U Dev[PCIE_MAX_ROOTBRIDGE];
• VOID *DmaResource[PCIE_MAX_ROOTBRIDGE];
• UINT32 DmaChannel[PCIE_MAX_ROOTBRIDGE][PCIE_DMA_CHANNEL_NUM];
• VOID *RegResource[PCIE_MAX_ROOTBRIDGE];
• VOID *CfgResource[PCIE_MAX_ROOTBRIDGE];

} PCIE_INIT_CFG; typedef enum { diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h index d1ba1c8..db89597 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h @@ -16,8 +16,6 @@ #ifndef __PCIE_KERNEL_API_H__ #define __PCIE_KERNEL_API_H__ -#define PCIE_HOST_BRIDGE_NUM (1) -#define PCIE_MAX_PORT_NUM (4) #define PCIE_MAX_OUTBOUND (6) #define PCIE_MAX_INBOUND (4) #define PCIE3_MAX_OUTBOUND (16) diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 2ce60d9..fca0b70 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -121,40 +121,150 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0|UINT64|0x00000057 gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000058 gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0|UINT64|0x00000059

• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000152
• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0|UINT64|0x00000153
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000154
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0|UINT64|0x00000155
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000156
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0|UINT64|0x00000157
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000158
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0|UINT64|0x00000159
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0|UINT64|0x00000252
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0|UINT64|0x00000253
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0|UINT64|0x00000254
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0|UINT64|0x00000255
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0|UINT64|0x00000256
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0|UINT64|0x00000257
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000258
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0|UINT64|0x00000259
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000352
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0|UINT64|0x00000353
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000354
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0|UINT64|0x00000355
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000356
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0|UINT64|0x00000357
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000358
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0|UINT64|0x00000359

gHisiTokenSpaceGuid.PciHb0Rb0Base|0|UINT64|0x0000005a gHisiTokenSpaceGuid.PciHb0Rb1Base|0|UINT64|0x0000005b gHisiTokenSpaceGuid.PciHb0Rb2Base|0|UINT64|0x0000005c gHisiTokenSpaceGuid.PciHb0Rb3Base|0|UINT64|0x0000005d

• gHisiTokenSpaceGuid.PciHb0Rb4Base|0|UINT64|0x0100005a
• gHisiTokenSpaceGuid.PciHb0Rb5Base|0|UINT64|0x0100005b
• gHisiTokenSpaceGuid.PciHb0Rb6Base|0|UINT64|0x0100005c
• gHisiTokenSpaceGuid.PciHb0Rb7Base|0|UINT64|0x0100005d
• gHisiTokenSpaceGuid.PciHb1Rb0Base|0|UINT64|0x0200005a
• gHisiTokenSpaceGuid.PciHb1Rb1Base|0|UINT64|0x0200005b
• gHisiTokenSpaceGuid.PciHb1Rb2Base|0|UINT64|0x0200005c
• gHisiTokenSpaceGuid.PciHb1Rb3Base|0|UINT64|0x0200005d
• gHisiTokenSpaceGuid.PciHb1Rb4Base|0|UINT64|0x0300005a
• gHisiTokenSpaceGuid.PciHb1Rb5Base|0|UINT64|0x0300005b
• gHisiTokenSpaceGuid.PciHb1Rb6Base|0|UINT64|0x0300005c
• gHisiTokenSpaceGuid.PciHb1Rb7Base|0|UINT64|0x0300005d
• gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0|UINT64|0x8000005a gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0|UINT64|0x8000005b gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0|UINT64|0x8000005c gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0|UINT64|0x8000005d
• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0|UINT64|0x8000005e
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0|UINT64|0x8000005f
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0|UINT64|0x80000060
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0|UINT64|0x80000061
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0|UINT64|0x80000062
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0|UINT64|0x80000063
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0|UINT64|0x80000064
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0|UINT64|0x80000065
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0|UINT64|0x80000066
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0|UINT64|0x80000067
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0|UINT64|0x80000068
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0|UINT64|0x80000069

gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0|UINT64|0x6000005a gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0|UINT64|0x6000005b gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0|UINT64|0x6000005c gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0|UINT64|0x6000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0|UINT64|0x6000005e
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0|UINT64|0x6000005f
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0|UINT64|0x60000060
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0|UINT64|0x60000061
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0|UINT64|0x60000062
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0|UINT64|0x60000063
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0|UINT64|0x60000064
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0|UINT64|0x60000065
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0|UINT64|0x60000066
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0|UINT64|0x60000067
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0|UINT64|0x60000068
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0|UINT64|0x60000069

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0|UINT64|0x7000005a gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0|UINT64|0x7000005b gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0|UINT64|0x7000005c gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0|UINT64|0x7000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0|UINT64|0x7000005e
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0|UINT64|0x7000005f
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0|UINT64|0x70000060
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0|UINT64|0x70000061
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0|UINT64|0x70000062
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0|UINT64|0x70000063
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0|UINT64|0x70000064
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0|UINT64|0x70000065
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0|UINT64|0x70000066
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0|UINT64|0x70000067
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0|UINT64|0x70000068
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0|UINT64|0x70000069

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0|UINT64|0x3000005a gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0|UINT64|0x3000005b gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0|UINT64|0x3000005c gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0|UINT64|0x3000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0|UINT64|0x3000005e
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0|UINT64|0x30000070
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0|UINT64|0x30000061
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0|UINT64|0x30000062
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0|UINT64|0x30000063
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0|UINT64|0x30000064
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0|UINT64|0x30000065
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0|UINT64|0x30000066
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0|UINT64|0x30000067
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0|UINT64|0x30000068
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0|UINT64|0x30000069
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0|UINT64|0x3000006a

gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0|UINT64|0x9000005a gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0|UINT64|0x9000005b gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0|UINT64|0x9000005c gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0|UINT64|0x9000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0|UINT64|0x9100005a
• gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0|UINT64|0x9100005b
• gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0|UINT64|0x9100005c
• gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0|UINT64|0x9100005d
• gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0|UINT64|0x9010005a
• gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0|UINT64|0x9010005b
• gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0|UINT64|0x9010005c
• gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0|UINT64|0x9010005d
• gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0|UINT64|0x9110005a
• gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0|UINT64|0x9110005b
• gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0|UINT64|0x9110005c
• gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0|UINT64|0x9110005d

gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0|UINT64|0x2000005a gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0|UINT64|0x2000005b gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0|UINT64|0x2000005c gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0|UINT64|0x2000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0|UINT64|0x2100005a
• gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0|UINT64|0x2100005b
• gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0|UINT64|0x2100005c
• gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0|UINT64|0x2100005d
• gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0|UINT64|0x2010005a
• gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0|UINT64|0x2010005b
• gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0|UINT64|0x2010005c
• gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0|UINT64|0x2010005d
• gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0|UINT64|0x2110005a
• gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0|UINT64|0x2110005b
• gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0|UINT64|0x2110005c
• gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d

gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061 gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064 diff --git a/Chips/Hisilicon/Include/Library/PlatformPciLib.h b/Chips/Hisilicon/Include/Library/PlatformPciLib.h index 72d2d21..e3228db 100644 --- a/Chips/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformPciLib.h @@ -17,17 +17,31 @@ #define _PLATFORM_PCI_LIB_H_ #define PCIE_MAX_HOSTBRIDGE 2 -#define PCIE_MAX_ROOTBRIDGE 4 +#define PCIE_MAX_ROOTBRIDGE 8 +//The extern pcie addresses will be initialized by oemmisclib +extern UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; +extern UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; +extern UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; +extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];

#define PCI_HB0RB0_PCI_BASE FixedPcdGet64(PciHb0Rb0Base) #define PCI_HB0RB1_PCI_BASE FixedPcdGet64(PciHb0Rb1Base) #define PCI_HB0RB2_PCI_BASE FixedPcdGet64(PciHb0Rb2Base) #define PCI_HB0RB3_PCI_BASE FixedPcdGet64(PciHb0Rb3Base) +#define PCI_HB0RB4_PCI_BASE FixedPcdGet64(PciHb0Rb4Base) +#define PCI_HB0RB5_PCI_BASE FixedPcdGet64(PciHb0Rb5Base) +#define PCI_HB0RB6_PCI_BASE FixedPcdGet64(PciHb0Rb6Base) +#define PCI_HB0RB7_PCI_BASE FixedPcdGet64(PciHb0Rb7Base) -#define PCI_HB1RB0_PCI_BASE 0xb0090000 -#define PCI_HB1RB1_PCI_BASE 0xb0200000 -#define PCI_HB1RB2_PCI_BASE 0xb00a0000 -#define PCI_HB1RB3_PCI_BASE 0xb00b0000 +#define PCI_HB1RB0_PCI_BASE FixedPcdGet64(PciHb1Rb0Base) +#define PCI_HB1RB1_PCI_BASE FixedPcdGet64(PciHb1Rb1Base) +#define PCI_HB1RB2_PCI_BASE FixedPcdGet64(PciHb1Rb2Base) +#define PCI_HB1RB3_PCI_BASE FixedPcdGet64(PciHb1Rb3Base) +#define PCI_HB1RB4_PCI_BASE FixedPcdGet64(PciHb1Rb4Base) +#define PCI_HB1RB5_PCI_BASE FixedPcdGet64(PciHb1Rb5Base) +#define PCI_HB1RB6_PCI_BASE FixedPcdGet64(PciHb1Rb6Base) +#define PCI_HB1RB7_PCI_BASE FixedPcdGet64(PciHb1Rb7Base) #define PCI_HB0RB0_ECAM_BASE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceBaseAddress) #define PCI_HB0RB0_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceSize) @@ -37,15 +51,32 @@ #define PCI_HB0RB2_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceSize) #define PCI_HB0RB3_ECAM_BASE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceBaseAddress) #define PCI_HB0RB3_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceSize) +#define PCI_HB0RB4_ECAM_BASE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB4_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceSize) +#define PCI_HB0RB5_ECAM_BASE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB5_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceSize) +#define PCI_HB0RB6_ECAM_BASE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB6_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceSize) +#define PCI_HB0RB7_ECAM_BASE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB7_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceSize)

+#define PCI_HB1RB0_ECAM_BASE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB0_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceSize) +#define PCI_HB1RB1_ECAM_BASE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB1_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceSize) +#define PCI_HB1RB2_ECAM_BASE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB2_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceSize) +#define PCI_HB1RB3_ECAM_BASE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB3_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceSize) +#define PCI_HB1RB4_ECAM_BASE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB4_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceSize) +#define PCI_HB1RB5_ECAM_BASE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB5_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceSize) +#define PCI_HB1RB6_ECAM_BASE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB6_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceSize) +#define PCI_HB1RB7_ECAM_BASE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB7_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceSize) -#define PCI_HB1RB0_ECAM_BASE (FixedPcdGet64 (PcdHb1BaseAddress) + PCI_HB0RB0_ECAM_BASE) -#define PCI_HB1RB0_ECAM_SIZE PCI_HB0RB0_ECAM_SIZE -#define PCI_HB1RB1_ECAM_BASE (FixedPcdGet64 (PcdHb1BaseAddress) + PCI_HB0RB1_ECAM_BASE) -#define PCI_HB1RB1_ECAM_SIZE PCI_HB0RB1_ECAM_SIZE -#define PCI_HB1RB2_ECAM_BASE 0xb8000000 -#define PCI_HB1RB2_ECAM_SIZE 0x4000000 -#define PCI_HB1RB3_ECAM_BASE 0xbc000000 -#define PCI_HB1RB3_ECAM_SIZE 0x4000000 #define PCI_HB0RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb0PciRegionBaseAddress)) #define PCI_HB0RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb0PciRegionSize)) #define PCI_HB0RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb1PciRegionBaseAddress)) @@ -54,26 +85,109 @@ #define PCI_HB0RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb2PciRegionSize)) #define PCI_HB0RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb3PciRegionBaseAddress)) #define PCI_HB0RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb3PciRegionSize)) +#define PCI_HB0RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb4PciRegionBaseAddress)) +#define PCI_HB0RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb4PciRegionSize)) +#define PCI_HB0RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb5PciRegionBaseAddress)) +#define PCI_HB0RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb5PciRegionSize)) +#define PCI_HB0RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb6PciRegionBaseAddress)) +#define PCI_HB0RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb6PciRegionSize)) +#define PCI_HB0RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb7PciRegionBaseAddress)) +#define PCI_HB0RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb7PciRegionSize))

+#define PCI_HB1RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb0PciRegionBaseAddress)) +#define PCI_HB1RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb0PciRegionSize)) +#define PCI_HB1RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb1PciRegionBaseAddress)) +#define PCI_HB1RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb1PciRegionSize)) +#define PCI_HB1RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb2PciRegionBaseAddress)) +#define PCI_HB1RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb2PciRegionSize)) +#define PCI_HB1RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb3PciRegionBaseAddress)) +#define PCI_HB1RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb3PciRegionSize)) +#define PCI_HB1RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb4PciRegionBaseAddress)) +#define PCI_HB1RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb4PciRegionSize)) +#define PCI_HB1RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb5PciRegionBaseAddress)) +#define PCI_HB1RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb5PciRegionSize)) +#define PCI_HB1RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb6PciRegionBaseAddress)) +#define PCI_HB1RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb6PciRegionSize)) +#define PCI_HB1RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb7PciRegionBaseAddress)) +#define PCI_HB1RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb7PciRegionSize))

#define PCI_HB0RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuMemRegionBase)) #define PCI_HB0RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuMemRegionBase)) #define PCI_HB0RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuMemRegionBase)) #define PCI_HB0RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuMemRegionBase)) +#define PCI_HB0RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuMemRegionBase)) +#define PCI_HB0RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuMemRegionBase)) +#define PCI_HB0RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuMemRegionBase)) +#define PCI_HB0RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuMemRegionBase))

+#define PCI_HB1RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuMemRegionBase)) +#define PCI_HB1RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuMemRegionBase)) +#define PCI_HB1RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuMemRegionBase)) +#define PCI_HB1RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuMemRegionBase)) +#define PCI_HB1RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuMemRegionBase)) +#define PCI_HB1RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuMemRegionBase)) +#define PCI_HB1RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuMemRegionBase)) +#define PCI_HB1RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuMemRegionBase))

#define PCI_HB0RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuIoRegionBase)) #define PCI_HB0RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuIoRegionBase)) #define PCI_HB0RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuIoRegionBase)) #define PCI_HB0RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuIoRegionBase)) +#define PCI_HB0RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuIoRegionBase)) +#define PCI_HB0RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuIoRegionBase)) +#define PCI_HB0RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuIoRegionBase)) +#define PCI_HB0RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuIoRegionBase))

+#define PCI_HB1RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuIoRegionBase)) +#define PCI_HB1RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuIoRegionBase)) +#define PCI_HB1RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuIoRegionBase)) +#define PCI_HB1RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuIoRegionBase)) +#define PCI_HB1RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuIoRegionBase)) +#define PCI_HB1RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuIoRegionBase)) +#define PCI_HB1RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuIoRegionBase)) +#define PCI_HB1RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuIoRegionBase))

#define PCI_HB0RB0_IO_BASE (FixedPcdGet64 (PcdHb0Rb0IoBase)) #define PCI_HB0RB1_IO_BASE (FixedPcdGet64 (PcdHb0Rb1IoBase)) #define PCI_HB0RB2_IO_BASE (FixedPcdGet64 (PcdHb0Rb2IoBase)) #define PCI_HB0RB3_IO_BASE (FixedPcdGet64 (PcdHb0Rb3IoBase)) +#define PCI_HB0RB4_IO_BASE (FixedPcdGet64 (PcdHb0Rb4IoBase)) +#define PCI_HB0RB5_IO_BASE (FixedPcdGet64 (PcdHb0Rb5IoBase)) +#define PCI_HB0RB6_IO_BASE (FixedPcdGet64 (PcdHb0Rb6IoBase)) +#define PCI_HB0RB7_IO_BASE (FixedPcdGet64 (PcdHb0Rb7IoBase))

+#define PCI_HB1RB0_IO_BASE (FixedPcdGet64 (PcdHb1Rb0IoBase)) +#define PCI_HB1RB1_IO_BASE (FixedPcdGet64 (PcdHb1Rb1IoBase)) +#define PCI_HB1RB2_IO_BASE (FixedPcdGet64 (PcdHb1Rb2IoBase)) +#define PCI_HB1RB3_IO_BASE (FixedPcdGet64 (PcdHb1Rb3IoBase)) +#define PCI_HB1RB4_IO_BASE (FixedPcdGet64 (PcdHb1Rb4IoBase)) +#define PCI_HB1RB5_IO_BASE (FixedPcdGet64 (PcdHb1Rb5IoBase)) +#define PCI_HB1RB6_IO_BASE (FixedPcdGet64 (PcdHb1Rb6IoBase)) +#define PCI_HB1RB7_IO_BASE (FixedPcdGet64 (PcdHb1Rb7IoBase)) #define PCI_HB0RB0_IO_SIZE (FixedPcdGet64 (PcdHb0Rb0IoSize)) #define PCI_HB0RB1_IO_SIZE (FixedPcdGet64 (PcdHb0Rb1IoSize)) #define PCI_HB0RB2_IO_SIZE (FixedPcdGet64 (PcdHb0Rb2IoSize)) #define PCI_HB0RB3_IO_SIZE (FixedPcdGet64 (PcdHb0Rb3IoSize)) +#define PCI_HB0RB4_IO_SIZE (FixedPcdGet64 (PcdHb0Rb4IoSize)) +#define PCI_HB0RB5_IO_SIZE (FixedPcdGet64 (PcdHb0Rb5IoSize)) +#define PCI_HB0RB6_IO_SIZE (FixedPcdGet64 (PcdHb0Rb6IoSize)) +#define PCI_HB0RB7_IO_SIZE (FixedPcdGet64 (PcdHb0Rb7IoSize))

+#define PCI_HB1RB0_IO_SIZE (FixedPcdGet64 (PcdHb1Rb0IoSize)) +#define PCI_HB1RB1_IO_SIZE (FixedPcdGet64 (PcdHb1Rb1IoSize)) +#define PCI_HB1RB2_IO_SIZE (FixedPcdGet64 (PcdHb1Rb2IoSize)) +#define PCI_HB1RB3_IO_SIZE (FixedPcdGet64 (PcdHb1Rb3IoSize)) +#define PCI_HB1RB4_IO_SIZE (FixedPcdGet64 (PcdHb1Rb4IoSize)) +#define PCI_HB1RB5_IO_SIZE (FixedPcdGet64 (PcdHb1Rb5IoSize)) +#define PCI_HB1RB6_IO_SIZE (FixedPcdGet64 (PcdHb1Rb6IoSize)) +#define PCI_HB1RB7_IO_SIZE (FixedPcdGet64 (PcdHb1Rb7IoSize))

typedef struct { UINT64 Ecam; diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf index 5040a04..c9ce45f 100644 --- a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf @@ -40,37 +40,143 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize

• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize gHisiTokenSpaceGuid.PciHb0Rb0Base gHisiTokenSpaceGuid.PciHb0Rb1Base gHisiTokenSpaceGuid.PciHb0Rb2Base gHisiTokenSpaceGuid.PciHb0Rb3Base
• gHisiTokenSpaceGuid.PciHb0Rb4Base
• gHisiTokenSpaceGuid.PciHb0Rb5Base
• gHisiTokenSpaceGuid.PciHb0Rb6Base
• gHisiTokenSpaceGuid.PciHb0Rb7Base
• gHisiTokenSpaceGuid.PciHb1Rb0Base
• gHisiTokenSpaceGuid.PciHb1Rb1Base
• gHisiTokenSpaceGuid.PciHb1Rb2Base
• gHisiTokenSpaceGuid.PciHb1Rb3Base
• gHisiTokenSpaceGuid.PciHb1Rb4Base
• gHisiTokenSpaceGuid.PciHb1Rb5Base
• gHisiTokenSpaceGuid.PciHb1Rb6Base
• gHisiTokenSpaceGuid.PciHb1Rb7Base gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress

gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize

• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb2IoSize gHisiTokenSpaceGuid.PcdHb0Rb0IoBase gHisiTokenSpaceGuid.PcdHb0Rb0IoSize gHisiTokenSpaceGuid.PcdHb0Rb1IoBase gHisiTokenSpaceGuid.PcdHb0Rb1IoSize gHisiTokenSpaceGuid.PcdHb0Rb2IoBase gHisiTokenSpaceGuid.PcdHb0Rb2IoSize

• gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb7IoSize

diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index 5ce7731..a08b461 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -15,6 +15,14 @@ #include <Library/PcdLib.h> #include <Library/PlatformPciLib.h> +UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000},

•                                    {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000}};
  

+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000},

•                                  {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}};
  

+UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000},

•                              {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}};
  

+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040},

•                              {0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}};
  

PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { {// HostBridge 0 diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf index 5040a04..c9ce45f 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf @@ -40,37 +40,143 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize

• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize gHisiTokenSpaceGuid.PciHb0Rb0Base gHisiTokenSpaceGuid.PciHb0Rb1Base gHisiTokenSpaceGuid.PciHb0Rb2Base gHisiTokenSpaceGuid.PciHb0Rb3Base
• gHisiTokenSpaceGuid.PciHb0Rb4Base
• gHisiTokenSpaceGuid.PciHb0Rb5Base
• gHisiTokenSpaceGuid.PciHb0Rb6Base
• gHisiTokenSpaceGuid.PciHb0Rb7Base
• gHisiTokenSpaceGuid.PciHb1Rb0Base
• gHisiTokenSpaceGuid.PciHb1Rb1Base
• gHisiTokenSpaceGuid.PciHb1Rb2Base
• gHisiTokenSpaceGuid.PciHb1Rb3Base
• gHisiTokenSpaceGuid.PciHb1Rb4Base
• gHisiTokenSpaceGuid.PciHb1Rb5Base
• gHisiTokenSpaceGuid.PciHb1Rb6Base
• gHisiTokenSpaceGuid.PciHb1Rb7Base gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress

gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize

• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb2IoSize gHisiTokenSpaceGuid.PcdHb0Rb0IoBase gHisiTokenSpaceGuid.PcdHb0Rb0IoSize gHisiTokenSpaceGuid.PcdHb0Rb1IoBase gHisiTokenSpaceGuid.PcdHb0Rb1IoSize gHisiTokenSpaceGuid.PcdHb0Rb2IoBase gHisiTokenSpaceGuid.PcdHb0Rb2IoSize

• gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb7IoSize

-- 1.9.1