From: Bartosz Szczepanek bsz@semihalf.com
Armada 7040 development board comprise three different ports: eth0: SFP cage with fixed link to 1G eth1: Optional 8-port switch with fixed link to 2.5G eth2: 1G RGMII port with autonegotiation enabled
This change also required MPP setting modification.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bartosz Szczepanek bsz@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Platforms/Marvell/Armada/Armada.dsc.inc | 1 + Platforms/Marvell/Armada/Armada7040.fdf | 1 + Platforms/Marvell/Armada/Armada7040_rz.dsc | 24 ++++++++++++++++++++---- 3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc index d12dfe6..29be6aa 100644 --- a/Platforms/Marvell/Armada/Armada.dsc.inc +++ b/Platforms/Marvell/Armada/Armada.dsc.inc @@ -409,6 +409,7 @@ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + OpenPlatformPkg/Drivers/Net/Pp2Dxe/Pp2Dxe.inf OpenPlatformPkg/Drivers/Net/MdioDxe/MdioDxe.inf OpenPlatformPkg/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
diff --git a/Platforms/Marvell/Armada/Armada7040.fdf b/Platforms/Marvell/Armada/Armada7040.fdf index 80e2a0e..48e34f5 100644 --- a/Platforms/Marvell/Armada/Armada7040.fdf +++ b/Platforms/Marvell/Armada/Armada7040.fdf @@ -135,6 +135,7 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF OpenPlatformPkg/Drivers/Net/Pp2Dxe/Pp2Dxe.inf INF OpenPlatformPkg/Drivers/Net/MdioDxe/MdioDxe.inf INF OpenPlatformPkg/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
diff --git a/Platforms/Marvell/Armada/Armada7040_rz.dsc b/Platforms/Marvell/Armada/Armada7040_rz.dsc index 42b6c2e..049dbb3 100644 --- a/Platforms/Marvell/Armada/Armada7040_rz.dsc +++ b/Platforms/Marvell/Armada/Armada7040_rz.dsc @@ -67,8 +67,8 @@ gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA } gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x0, 0x6, 0x2, 0x2, 0x0 } gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } @@ -130,7 +130,7 @@ gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110"
gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;1250;5000;5000;5000" + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000"
#UtmiPhy gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 @@ -143,6 +143,22 @@ gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200
#PHY - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x4, 0x4, 0x0 } gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + #NET + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortNumber|3 + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000 + gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0xf2130e00 + gMarvellTokenSpaceGuid.PcdPp2GmacObjSize|0x1000 + gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0xf2130f00 + gMarvellTokenSpaceGuid.PcdPp2XlgObjSize|0x1000 + gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0xf2441000 + gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0xf212A200 + gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333