On Fri, Apr 14, 2017 at 01:23:25PM +0100, Ard Biesheuvel wrote:
On 13 April 2017 at 19:43, Leif Lindholm leif.lindholm@linaro.org wrote:
On Thu, Apr 13, 2017 at 05:49:04PM +0100, Ard Biesheuvel wrote:
Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space.
This is not a problem for the onboard devices, but it would be useful if we could support random PCIe plug-in cards, even if they are only 32-bit DMA capable.
Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table.
While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Looks sensible to me. If you get a nod from Graeme: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Thanks. But as it turns out, i will need to respin it since the SMMU config of the B1 silicon deviates from B0. I tested it on Cello while under the assumption that it is B1 silicon, but it turns out to be B0, and on my B1 overdrive, only the PCIe SMMU works (which is arguably the most important one anyway)
That might explain why when I asked AMD to add this they were not interested. But yes would be good to get the SMMU's turned on if they work.
Graeme