PE test case 15 flow: Primary core(cacheable shareable) and slave cores(non-cacheable) access the same memory area for communication. For each slave core{ 1 Turn on slave core; 2 run the payload function; 3 Write result in memory to notify primary core and follow clean and invalidate instruction; 4 Slave core turn off itself; } The result in DDR may rewrite by cache data. The essence of this problem is that primary core and slave core access the same area with different cache attribute. Configure L3T register to fix this issue;
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPkg:6e91ea20fda TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 230784 -> 232832 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index 8b6d740..e32c056 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ