Re: [Linaro-uefi] [PATCH v2 06/24] Hisilicon/PCIe: support different memory address in PCIe domain

On Tue, Oct 18, 2016 at 09:09:50PM +0800, Heyi Guo wrote:

Most of PCIe memory BARs can only be mapped to 4G above system address, for there is not enough address space under 4G. However, some legacy PCIe devices may require to be mapped into 32bit address. To support such devices, a pair of new parameters is introduced to expose memory address under 4G in PCIe domain, which can be different from the address in system domain, by setting iATU accordingly.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org

Reviewed-by: Leif Lindholm leif.lindholm@linaro.org

---

.../Drivers/PciHostBridgeDxe/PciHostBridge.h | 2 ++ .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 6 ++-- Chips/Hisilicon/Include/Library/PlatformPciLib.h | 2 ++ .../D02/Library/PlatformPciLib/PlatformPciLib.c | 32 +++++++++++++++------ .../D03/Library/PlatformPciLib/PlatformPciLib.c | 33 ++++++++++++++++------ 5 files changed, 57 insertions(+), 18 deletions(-)

diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index 99c97cf..cddda6b 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -478,6 +478,8 @@ typedef struct { UINT32 SocType; UINT64 CpuMemRegionBase; UINT64 CpuIoRegionBase;

• UINT64 PciRegionBase;
• UINT64 PciRegionLimit;

EFI_DEVICE_PATH_PROTOCOL *DevicePath; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 01aa1e0..03edcf1 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -730,7 +730,7 @@ void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT6 VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private) {

• SetAtuMemRW (Private->RbPciBar, Private->MemBase, Private->MemLimit, Private->CpuMemRegionBase, 0);

• SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0); SetAtuConfig0RW (Private, 1); SetAtuConfig1RW (Private, 2); SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);

@@ -800,6 +800,8 @@ RootBridgeConstructor ( PrivateData->Ecam = ResAppeture->Ecam; PrivateData->CpuMemRegionBase = ResAppeture->CpuMemRegionBase; PrivateData->CpuIoRegionBase = ResAppeture->CpuIoRegionBase;

• PrivateData->PciRegionBase = ResAppeture->PciRegionBase;
• PrivateData->PciRegionLimit = ResAppeture->PciRegionLimit;

// // Bus Appeture for this Root Bridge (Possible Range) @@ -1058,7 +1060,7 @@ RootBridgeIoMemRW ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); /* Address is bus resource */

• Address -= PrivateData->MemBase;

• Address -= PrivateData->PciRegionBase; Address += PrivateData->CpuMemRegionBase;

PCIE_DEBUG("RootBridgeIoMemRW Address:0x%llx\n", Address); diff --git a/Chips/Hisilicon/Include/Library/PlatformPciLib.h b/Chips/Hisilicon/Include/Library/PlatformPciLib.h index ace444f..f478ef8 100644 --- a/Chips/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformPciLib.h @@ -194,6 +194,8 @@ typedef struct { UINT64 CpuMemRegionBase; UINT64 CpuIoRegionBase; UINT64 RbPciBar;

• UINT64 PciRegionBase;
• UINT64 PciRegionLimit;

} PCI_ROOT_BRIDGE_RESOURCE_APPETURE; extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c index b487b5f..797163a 100644 --- a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c @@ -29,7 +29,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB0RB0_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB0_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 1 */ {

@@ -42,7 +44,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1, //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, PCI_HB0RB2_CPUIOREGIONBASE,

•  (PCI_HB0RB1_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB1_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB1_PCIREGION_BASE,
  

•  PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1
  

  }, /* Port 2 */ {

@@ -55,7 +59,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1, //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, PCI_HB0RB2_CPUIOREGIONBASE,

•  (PCI_HB0RB2_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB2_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB2_PCIREGION_BASE ,
  

•  PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1
  

  },

/* Port 3 */ @@ -69,7 +75,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB0RB3_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB3_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  } },

{// HostBridge 1 @@ -84,7 +92,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB0_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB0_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 1 */ {

@@ -97,7 +107,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB1_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB1_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 2 */ {

@@ -110,7 +122,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB2_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB2_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  },

/* Port 3 */ @@ -124,7 +138,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB3_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB3_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  } }

}; diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index 5ce7731..2f7d158 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -29,7 +29,10 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase

•  (PCI_HB0RB0_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB0_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase
  

•  PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit
  

• }, /* Port 1 */ {

@@ -42,7 +45,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase

•  (PCI_HB0RB1_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB1_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase
  

•  PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit
  

  }, /* Port 2 */ {

@@ -55,7 +60,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase

•  (PCI_HB0RB2_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB2_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase
  

•  PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit
  

  },

/* Port 3 */ @@ -69,7 +76,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB0RB3_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB3_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  } },

{// HostBridge 1 @@ -84,7 +93,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB0_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB0_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 1 */ {

@@ -97,7 +108,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB1_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB1_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 2 */ {

@@ -110,7 +123,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB2_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB2_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  },

/* Port 3 */ @@ -124,7 +139,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB3_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB3_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  } }

};

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