On 1 June 2017 at 13:40, Leif Lindholm leif.lindholm@linaro.org wrote:
On Thu, Jun 01, 2017 at 09:43:50AM +0000, Ard Biesheuvel wrote:
Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space.
This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable.
Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table.
While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Did we want a comment from Graeme on this? (added to cc)
He did comment on it tangentially, by observing that AMD never contributed an IORT table, probably because the Stream IDs are different between B0 and B1 silicon. This table works on both, though.