14 Nov
2018
14 Nov
'18
5:27 p.m.
On Wed, Nov 14, 2018 at 08:53:55AM +0000, Prasanth Pulla wrote:
The result in DDR may rewrite by cache data. The essence of this problem is that primary core and slave core access the same area with different cache attribute. Configure L3T register to fix this issue;
Does this change have any performance implications?
Prasanth: would PE test 15 not be _expected_ to fail if primary and secondary cores access the buffers with different cachability attributes?
No this is not expected. I will work with the team and see if we can enhance the ACS code to detect this and work in this scenario.
But the architecture itself does not guarantee this scenario should work?
/ Leif