From: Heyi Guo heyi.guo@linaro.org
Each PCI root bridge has its own macro definitions for its resource aperture, so that one root bridge should not use macro definitions of other root bridges.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo heyi.guo@linaro.org Cc: Ard Biesheuvel ard.biesheuvel@linaro.org Cc: Leif Lindholm leif.lindholm@linaro.org Cc: Michael D Kinney michael.d.kinney@intel.com --- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index ed6c4ac321..c0b756ccfb 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -159,7 +159,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB0_ECAM_BASE), //MemBase (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB0_IO_BASE, //IoBase - (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB0_CPUIOREGIONBASE + PCI_HB1RB0_IO_SIZE - 1), //IoLimit PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB0_PCI_BASE), //RbPciBar @@ -174,7 +174,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB1_ECAM_BASE), //MemBase (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB1_IO_BASE, //IoBase - (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB1_CPUIOREGIONBASE + PCI_HB1RB1_IO_SIZE - 1), //IoLimit PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB1_PCI_BASE), //RbPciBar @@ -189,7 +189,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB2_IO_BASE, //IoBase - (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB2_CPUIOREGIONBASE + PCI_HB1RB2_IO_SIZE - 1), //IoLimit PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB2_PCI_BASE), //RbPciBar @@ -205,7 +205,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB3_ECAM_BASE), //MemBase (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB3_IO_BASE, //IoBase - (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB3_CPUIOREGIONBASE + PCI_HB1RB3_IO_SIZE - 1), //IoLimit PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB3_PCI_BASE), //RbPciBar @@ -220,7 +220,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB4_IO_BASE, //IoBase - (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB4_CPUIOREGIONBASE + PCI_HB1RB4_IO_SIZE - 1), //IoLimit PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB4_PCI_BASE), //RbPciBar @@ -235,7 +235,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB5_IO_BASE, //IoBase - (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB5_CPUIOREGIONBASE + PCI_HB1RB5_IO_SIZE - 1), //IoLimit PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB5_PCI_BASE), //RbPciBar @@ -250,12 +250,12 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB6_ECAM_BASE), //MemBase PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB6_IO_BASE, //IoBase - (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB6_CPUIOREGIONBASE + PCI_HB1RB6_IO_SIZE - 1), //IoLimit PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB6_PCI_BASE), //RbPciBar PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit + PCI_HB1RB6_PCIREGION_BASE + PCI_HB1RB6_PCIREGION_SIZE - 1 //PciRegionlimit },
/* Port 7 */ @@ -266,7 +266,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB7_ECAM_BASE), //MemBase PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB7_IO_BASE, //IoBase - (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB7_CPUIOREGIONBASE + PCI_HB1RB7_IO_SIZE - 1), //IoLimit PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB7_PCI_BASE), //RbPciBar