Re: [Linaro-uefi] [PATCH 3/6] Platform/Marvell: ComPhyLib: Configure analog parameters for SATA

On Fri, Apr 07, 2017 at 05:58:41PM +0200, Marcin Wojtas wrote:

This patch adds analog parameters configuration for SATA with the values defined during electrical tests of the interface.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com

---

Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 177 ++++++++++++++++++++- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 179 +++++++++++++++++++++- 2 files changed, 346 insertions(+), 10 deletions(-)

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c index ee3ce99..e3f6d45 100755 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -608,9 +608,182 @@ ComPhySataPhyConfiguration ( STATIC VOID ComPhySataSetAnalogParameters (

• IN EFI_PHYSICAL_ADDRESS HpipeAddr

• IN EFI_PHYSICAL_ADDRESS HpipeAddr,
• IN EFI_PHYSICAL_ADDRESS SdIpAddr

) {

• UINT32 Data, Mask;
• /* G1 settings */

What's G1? No need to abbreviate in comments.

• Mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
• Data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
• Mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
• Data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
• Mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
• Data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
• Mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
• Data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
• Mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
• Data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
• RegSet (HpipeAddr + HPIPE_G1_SET_1_REG, Data, Mask);

Obviously, this isn't really something I can review properly. Nevertheless, is there any way we can get rid of the last remaining magic numbers in the .c file? Those 0x0, 0x1 and 0x3 make no sense without already knowing the internal formats of those registers.

• Mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
• Data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
• Mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
• Data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
• Mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
• Data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
• Mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK;
• Data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET;
• Mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK;
• Data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET;
• RegSet (HpipeAddr + HPIPE_G1_SETTINGS_3_REG, Data, Mask);
• /* G2 settings */
• Mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
• Data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
• Mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
• Data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
• Mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
• Data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
• Mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
• Data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET;
• Mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK;
• Data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET;
• RegSet (HpipeAddr + HPIPE_G2_SET_1_REG, Data, Mask);
• /* G3 settings */
• Mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
• Data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
• Mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
• Data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
• Mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK;
• Data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET;
• Mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK;
• Data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET;
• Mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK;
• Data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET;
• Mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK;
• Data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET;
• Mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
• Data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
• RegSet (HpipeAddr + HPIPE_G3_SET_1_REG, Data, Mask);
• /* DTL Control */
• Mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK;
• Data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET;
• Mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK;
• Data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET;
• Mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
• Data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
• Mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK;
• Data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET;
• Mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK;
• Data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET;
• Mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK;
• Data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET;
• Mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
• Data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET;
• RegSet (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, Data, Mask);
• /* Trigger sampler enable pulse (by toggleing the bit) */
• Mask = HPIPE_SAMPLER_MASK;
• Data = 0x1 << HPIPE_SAMPLER_OFFSET;
• RegSet (HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, Data, Mask);
• Mask = HPIPE_SAMPLER_MASK;
• Data = 0x0 << HPIPE_SAMPLER_OFFSET;
• RegSet (HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, Data, Mask);
• /* VDD Calibration Control 3 */
• Mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
• Data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
• RegSet (HpipeAddr + HPIPE_VDD_CAL_CTRL_REG, Data, Mask);
• /* DFE Resolution Control */
• Mask = HPIPE_DFE_RES_FORCE_MASK;
• Data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
• RegSet (HpipeAddr + HPIPE_DFE_REG0, Data, Mask);
• /* DFE F3-F5 Coefficient Control */
• Mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
• Data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
• Mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
• Data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
• RegSet (HpipeAddr + HPIPE_DFE_F3_F5_REG, Data, Mask);
• /* G3 Setting 3 */
• Mask = HPIPE_G3_FFE_CAP_SEL_MASK;
• Data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET;
• Mask |= HPIPE_G3_FFE_RES_SEL_MASK;
• Data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET;
• Mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK;
• Data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET;
• Mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
• Data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
• Mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
• Data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
• RegSet (HpipeAddr + HPIPE_G3_SETTING_3_REG, Data, Mask);
• /* G3 Setting 4 */
• Mask = HPIPE_G3_DFE_RES_MASK;
• Data = 0x2 << HPIPE_G3_DFE_RES_OFFSET;
• RegSet (HpipeAddr + HPIPE_G3_SETTING_4_REG, Data, Mask);
• /* Offset Phase Control */
• Mask = HPIPE_OS_PH_OFFSET_MASK;
• Data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET;
• Mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK;
• Data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET;
• RegSet (HpipeAddr + HPIPE_PHASE_CONTROL_REG, Data, Mask);
• Mask = HPIPE_OS_PH_VALID_MASK;
• Data = 0x1 << HPIPE_OS_PH_VALID_OFFSET;
• RegSet (HpipeAddr + HPIPE_PHASE_CONTROL_REG, Data, Mask);
• Mask = HPIPE_OS_PH_VALID_MASK;
• Data = 0x0 << HPIPE_OS_PH_VALID_OFFSET;
• RegSet (HpipeAddr + HPIPE_PHASE_CONTROL_REG, Data, Mask);
• /* Set G1 TX amplitude and TX post emphasis value */
• Mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
• Data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
• Mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
• Data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET;
• Mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
• Data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
• Mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
• Data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET;
• RegSet (HpipeAddr + HPIPE_G1_SET_0_REG, Data, Mask);
• /* Set G2 TX amplitude and TX post emphasis value */
• Mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK;
• Data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET;
• Mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK;
• Data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET;
• Mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK;
• Data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET;
• Mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK;
• Data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET;
• RegSet (HpipeAddr + HPIPE_G2_SET_0_REG, Data, Mask);
• /* Set G3 TX amplitude and TX post emphasis value */
• Mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK;
• Data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET;
• Mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK;
• Data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET;
• Mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK;
• Data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET;
• Mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK;
• Data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET;
• Mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK;
• Data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET;
• Mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK;
• Data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET;
• RegSet (HpipeAddr + HPIPE_G3_SET_0_REG, Data, Mask);
• /* SERDES External Configuration 2 register */
• Mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK;
• Data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET;
• RegSet (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, Data, Mask);

There looks to be a spectacular amount of duplication, looking for example at the RX_DIGCK_DIV_OFFSET definitions. Is there any difference whatsoever between the internal structures of G1, G2 and G2? If not, please cut away the redundancy.

In general, the additions in this patch looks like a transposition of raw assembly into C. While this will never be a highly readable function, we should try to make it as readable as possible.

/ Leif

/* DFE reset sequence */ RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); @@ -738,7 +911,7 @@ ComPhySataPowerUp ( DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));

• ComPhySataSetAnalogParameters (HpipeAddr);

• ComPhySataSetAnalogParameters (HpipeAddr, SdIpAddr);

DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h index 24839b2..463e542 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -143,6 +143,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) +#define SD_EXTERNAL_CONFIG2_REG 0x8 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) #define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 @@ -177,18 +182,82 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) #define HPIPE_G1_SET_0_REG 0x034 +#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 +#define HPIPE_G1_SET_0_G1_TX_AMP_MASK (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) #define HPIPE_G1_SET_1_REG 0x038 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 +#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 +#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)

-#define HPIPE_G2_SETTINGS_1_REG 0x040 +#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)

+#define HPIPE_G2_SET_0_REG 0x3c +#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 +#define HPIPE_G2_SET_0_G2_TX_AMP_MASK (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 +#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)

+#define HPIPE_G2_SET_1_REG 0x040 +#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 +#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 +#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 +#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 +#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 +#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)

+#define HPIPE_G3_SET_0_REG 0x44 +#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 +#define HPIPE_G3_SET_0_G3_TX_AMP_MASK (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 +#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 +#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 +#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)

+#define HPIPE_G3_SET_1_REG 0x048 +#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 +#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 +#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 +#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 +#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 +#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) +#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 +#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) #define HPIPE_LOOPBACK_REG 0x08c #define HPIPE_LOOPBACK_SEL_OFFSET 1 @@ -210,6 +279,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 +#define HPIPE_VDD_CAL_CTRL_REG 0x114 +#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 +#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)

+#define HPIPE_VDD_CAL_0_REG 0x108 +#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 +#define HPIPE_CAL_VDD_CONT_MODE_MASK (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)

#define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 #define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) @@ -244,11 +321,57 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_PLLINTP_REG1 0x150 -#define HPIPE_PWR_CTR_DTL_REG 0x184 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 0x2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)

-#define HPIPE_RX_REG3 0x188 +#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C +#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 +#define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) +#define HPIPE_SAMPLER_OFFSET 12 +#define HPIPE_SAMPLER_MASK (0x1 << HPIPE_SAMPLER_OFFSET)

+#define HPIPE_TX_REG1_REG 0x174 +#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_OFFSET 10 +#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)

+#define HPIPE_PWR_CTR_DTL_REG 0x184 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)

+#define HPIPE_PHASE_CONTROL_REG 0x188 +#define HPIPE_OS_PH_OFFSET_OFFSET 0 +#define HPIPE_OS_PH_OFFSET_MASK (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) +#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 +#define HPIPE_OS_PH_OFFSET_FORCE_MASK (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) +#define HPIPE_OS_PH_VALID_OFFSET 8 +#define HPIPE_OS_PH_VALID_MASK (0x1 << HPIPE_OS_PH_VALID_OFFSET)

+#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 +#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 +#define HPIPE_TRAIN_PAT_NUM_MASK (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)

+#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)

+#define HPIPE_DME_REG 0x228 +#define HPIPE_DME_ETHERNET_MODE_OFFSET 7 +#define HPIPE_DME_ETHERNET_MODE_MASK (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)

+#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 +#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) #define HPIPE_TX_TRAIN_CTRL_REG 0x26C #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 @@ -267,10 +390,50 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) -#define HPIPE_G1_SETTINGS_3_REG 0x440 +#define HPIPE_G1_SETTINGS_3_REG 0x440 +#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 +#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 +#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 +#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 +#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 +#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 +#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)

#define HPIPE_G1_SETTINGS_4_REG 0x444 #define HPIPE_G2_SETTINGS_3_REG 0x448

#define HPIPE_G2_SETTINGS_4_REG 0x44C +#define HPIPE_G2_DFE_RES_OFFSET 8 +#define HPIPE_G2_DFE_RES_MASK (0x3 << HPIPE_G2_DFE_RES_OFFSET)

+#define HPIPE_G3_SETTING_3_REG 0x450 +#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 +#define HPIPE_G3_FFE_CAP_SEL_MASK (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) +#define HPIPE_G3_FFE_RES_SEL_OFFSET 4 +#define HPIPE_G3_FFE_RES_SEL_MASK (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) +#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 +#define HPIPE_G3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 +#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)

+#define HPIPE_G3_SETTING_4_REG 0x454 +#define HPIPE_G3_DFE_RES_OFFSET 8 +#define HPIPE_G3_DFE_RES_MASK (0x3 << HPIPE_G3_DFE_RES_OFFSET)

+#define HPIPE_TX_PRESET_INDEX_REG 0x468 +#define HPIPE_TX_PRESET_INDEX_OFFSET 0 +#define HPIPE_TX_PRESET_INDEX_MASK (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)

+#define HPIPE_DFE_CONTROL_REG 0x470 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) #define HPIPE_DFE_CTRL_28_REG 0x49C

#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7

1.8.3.1