[Linaro-uefi] [RFC 18/21] Platforms/Marvell: Create ComPhyLib

From: Jan Dąbroś jsd@semihalf.com

Marvell SoC's comprise multiplexed pins for SerDes lanes (XHCI, AHCI, SGMII, PCIe) called ComPhy.

ComPhyLib initialize ComPhy and ComPhy Mux. All configurable parameters are provided via set of PCDs.

In order to satisfy preprocessor demands, there are ComPhy PCDs for all of 4 possible chips.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Documentation/Marvell/PortingGuide/ComPhy.txt | 77 ++ Documentation/Marvell/UserGuide.txt | 1 + Platforms/Marvell/Include/Library/ComPhyLib.h | 43 ++ Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c | 290 ++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 811 ++++++++++++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 277 ++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 457 ++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 110 +++ Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 ++++ Platforms/Marvell/Marvell.dec | 47 ++ 10 files changed, 2245 insertions(+) create mode 100644 Documentation/Marvell/PortingGuide/ComPhy.txt create mode 100644 Platforms/Marvell/Include/Library/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c

diff --git a/Documentation/Marvell/PortingGuide/ComPhy.txt b/Documentation/Marvell/PortingGuide/ComPhy.txt new file mode 100644 index 0000000..29383d4 --- /dev/null +++ b/Documentation/Marvell/PortingGuide/ComPhy.txt @@ -0,0 +1,77 @@ +COMPHY configuration +--------------------------- +In order to configure ComPhy library, following PCDs are available: + + gMarvellTokenSpaceGuid.PcdComPhyChipCount + +Indicates how many different chips are placed on board. So far, up to 4 chips +are supported. + +Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not +important, but configuration will be set for first PcdComPhyChipCount chips). + +Every chip has 8 ComPhy PCDs and three of them concern lanes settings for this +chip. Below is example for the first chip (Chip0). + +General PCDs: + + gMarvellTokenSpaceGuid.PcdChip0Compatible + +Unicode string indicating type of chip - currently supported are +{ L"Ap806", L"Cp110"} + + gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress + +Indicates COMPHY unit base address. + + gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress + +Indicates Hpipe3 unit base address. + + gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount + +Indicates number of bits that are allocated for every MUX in the +COMPHY-selector register. + + gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes + +Indicates maximum ComPhy lanes number. + +Next three PCDs are in unicode string format containing settings for up to 10 +lanes. Setting for each one is separated with semicolon. Below is example for +the first chip (Chip0). + + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + +Unicode string indicating PHY types. Currently supported are: + +{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", +L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", +L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", +L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", +L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", +L"RXAUI1", L"KR" } + + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds + +Indicates PHY speeds in MHz. Currently supported are: + +{ 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 1031 } + + gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + +Indicates lane polarity invert. + +Example +------- + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyChipCount|1 + + gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6 + gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000 + gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000 + gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4 + gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110" + + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2" + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;1250;5000;5000;5000" diff --git a/Documentation/Marvell/UserGuide.txt b/Documentation/Marvell/UserGuide.txt index 6def7d8..cb9838a 100644 --- a/Documentation/Marvell/UserGuide.txt +++ b/Documentation/Marvell/UserGuide.txt @@ -7,6 +7,7 @@ Table of contents: Build.txt

2. Porting guide + comphy - PortingGuide/ComPhy.txt i2c - PortingGuide/I2c.txt icu - PortingGuide/IcuLib.txt mpp - PortingGuide/Mpp.txt diff --git a/Platforms/Marvell/Include/Library/ComPhyLib.h b/Platforms/Marvell/Include/Library/ComPhyLib.h new file mode 100644 index 0000000..d63a19d --- /dev/null +++ b/Platforms/Marvell/Include/Library/ComPhyLib.h @@ -0,0 +1,43 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __COMPHYLIB_H__ +#define __COMPHYLIB_H__ + +EFI_STATUS +ComPhyInit ( + VOID + ); + +#endif diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c new file mode 100644 index 0000000..d0fad1e --- /dev/null +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c @@ -0,0 +1,290 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ComPhyLib.h" + +#define HPIPE_ADDR(base, lane) (base + 0x800 * lane) +#define COMPHY_RESET_REG 0x120 + +#define COMPHY_RESET_SW_OFFSET 14 +#define COMPHY_RESET_SW_MASK (1 << COMPHY_RESET_SW_OFFSET) +#define COMPHY_RESET_CORE_OFFSET 13 +#define COMPHY_RESET_CORE_MASK (1 << COMPHY_RESET_CORE_OFFSET) + +#define COMPHY_PCI_MAC_CTRL 0x200 + +#define COMPHY_PCI_EN_OFFSET 0 +#define COMPHY_PCI_EN_MASK (0x1 << COMPHY_PCI_EN_OFFSET) +#define COMPHY_PCI_AXI_CACHE_OFFSET 8 +#define COMPHY_PCI_AXI_CACHE_MASK (0xF << COMPHY_PCI_AXI_CACHE_OFFSET) +#define COMPHY_PCI_COHERENT 0x7 +#define COMPHY_PCI_X1_EN_OFFSET 14 +#define COMPHY_PCI_X1_EN_MASK (0x1 << COMPHY_PCI_X1_EN_OFFSET) + +STATIC +VOID +ComPhyPcieReleaseSoftReset ( + IN EFI_PHYSICAL_ADDRESS HpipeAddr + ) +{ + /* Set MAX PLL Calibration */ + RegSet (HpipeAddr + HPIPE_KVCO_CALIB_CTRL_REG, + 0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET, + HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK); + RegSet (HpipeAddr + HPIPE_LANE_CONFIG0_REG, + 0x1 << HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET, + HPIPE_LANE_CONFIG0_MAX_PLL_MASK); + RegSet (HpipeAddr + HPIPE_LANE_CONFIG0_REG, + 0x1 << HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET, + HPIPE_LANE_CONFIG0_GEN2_PLL_MASK); + + /* DFE reset sequence */ + RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, + 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + MicroSecondDelay (10); + RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, + 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + + /* SW reset for interrupt logic */ + RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, + 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + MicroSecondDelay (10); + RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, + 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); +} + +STATIC +EFI_STATUS +ComPhyPciePowerUp ( + IN UINT32 Lane, + IN UINT32 PcieBy4, + IN EFI_PHYSICAL_ADDRESS HpipeAddr + ) +{ + UINT32 StartVal, BreakVal, MasterVal; + + /* Enable CLK 500 */ + RegSet (HpipeAddr + HPIPE_MISC_REG, 0x1 << HPIPE_MISC_CLK500_EN_OFFSET, + HPIPE_MISC_CLK500_EN_MASK); + /* Clear lane align off */ + if (PcieBy4) + RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG, + 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET, HPIPE_LANE_ALIGN_OFF_MASK); + /* Reference Frequency Select set 0 (for PCIe 0 = 100Mhz) */ + RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET, + HPIPE_PWR_PLL_REF_FREQ_MASK); + /* PHY Mode Select (set PCIe = 0x3) */ + RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET, + HPIPE_PWR_PLL_PHY_MODE_MASK); + /* Set PIPE RESET - SW reset for the PIPE */ + RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, + 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); + /* Set PCIe fixed mode to 8 bit @ 250 Mhz */ + RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, + 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET, + HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK); + /* Set 5Gbps for RX and TX */ + RegSet (HpipeAddr + HPIPE_ISOLATE_MODE_REG, + 0x1 << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET, HPIPE_ISOLATE_MODE_GEN_RX_MASK); + RegSet (HpipeAddr + HPIPE_ISOLATE_MODE_REG, + 0x1 << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET, HPIPE_ISOLATE_MODE_GEN_TX_MASK); + /* Set Max PHY generation setting - 5GBps */ + RegSet (HpipeAddr + HPIPE_INTERFACE_REG, + 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK); + /* + * Set Lane Break/Start/Master: + * master - Provide RefClock to MAC + * start - Start of providing RefClock + * break - Stop passing the RefClock + */ + if (PcieBy4) { + /* + * If By4 Lane 0 - is master and start PHY + * Lane 1-2 - pass refclock to next phy + * Lane 3 - stop passing refclock + */ + if (Lane == 0) { + StartVal = 0x1; + BreakVal = 0x0; + MasterVal = 0x1; + } else if (Lane == 3) { + StartVal = 0x0; + BreakVal = 0x1; + MasterVal = 0x0; + } else { + StartVal = 0x0; + BreakVal = 0x0; + MasterVal = 0x0; + } + } else { + StartVal = 0x1; + BreakVal = 0x1; + MasterVal = 0x1; + } + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, + StartVal << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET, + HPIPE_CLK_SRC_HI_LANE_STRT_MASK); + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, + BreakVal << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET, + HPIPE_CLK_SRC_HI_LANE_BREAK_MASK); + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, + MasterVal << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET, + HPIPE_CLK_SRC_HI_LANE_MASTER_MASK); + + /* For PCIe by4 need to reset after configure all 4 Lanes */ + if (PcieBy4) { + return EFI_SUCCESS; + } + + ComPhyPcieReleaseSoftReset(HpipeAddr); + /* Release PIPE RESET - release PHY from reset */ + RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, + 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); + + MicroSecondDelay (20000); + + /* Return the status of the PLL */ + return (EFI_STATUS) (MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG) & + HPIPE_LANE_STATUS0_PCLK_EN_MASK); +} + +EFI_STATUS +ComPhyAp806Init ( + IN CHIP_COMPHY_CONFIG *PtrChipCfg + ) +{ + EFI_STATUS Status; + COMPHY_MAP *PtrComPhyMap, *SerdesMap; + EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; + UINT32 ComPhyMaxCount, Lane; + UINT32 PcieBy4 = 1; + + ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr; + ComPhyMaxCount = PtrChipCfg->LanesCount; + HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr; + SerdesMap = PtrChipCfg->MapData; + + /* Set PHY to Normal mode */ + RegSet (ComPhyBaseAddr + COMPHY_RESET_REG, 1 << COMPHY_RESET_SW_OFFSET, + COMPHY_RESET_SW_MASK); + RegSet (ComPhyBaseAddr + COMPHY_RESET_REG, 1 << COMPHY_RESET_CORE_OFFSET, + COMPHY_RESET_CORE_MASK); + + /* Check if the first 4 Lanes configured as By-4 */ + for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) { + if (PtrComPhyMap->Type != PHY_TYPE_PCIE0) { + PcieBy4 = 0; + break; + } + } + + for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount; + Lane++, PtrComPhyMap++) { + DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane)); + DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type)); + switch (PtrComPhyMap->Type) { + case PHY_TYPE_UNCONNECTED: + continue; + break; + case PHY_TYPE_PCIE0: + case PHY_TYPE_PCIE1: + case PHY_TYPE_PCIE2: + case PHY_TYPE_PCIE3: + Status = ComPhyPciePowerUp (Lane, PcieBy4, HPIPE_ADDR(HpipeBaseAddr, + Lane)); + MicroSecondDelay (20); + break; + default: + DEBUG((DEBUG_INFO, "ComPhy: Unknown SerDes Type, skip initialize " + "SerDes %d\n", Lane)); + break; + } + if (EFI_ERROR(Status)) + DEBUG((DEBUG_ERROR, "ComPhy: PLL is not locked - Failed to initialize " + "Lane %d\n", Lane)); + } + + /* SW reset for PCIe for all Lanes after power up */ + if (PcieBy4) { + for (Lane = 0; Lane < 4; Lane++) { + ComPhyPcieReleaseSoftReset (HPIPE_ADDR(HpipeBaseAddr, Lane)); + } + + /* + * Release PIPE RESET - release PHY from reset + * need to release the Lanes without delay between them + */ + DEBUG((DEBUG_INFO, "ComPhy: Release PIPE reset for PCIe-By4, write to " + "Reset Clock control register\n")); + for (Lane = 0; Lane < 4; Lane++) { + RegSetSilent(HPIPE_ADDR(HpipeBaseAddr, Lane) + HPIPE_RST_CLK_CTRL_REG, + 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); + } + + MicroSecondDelay (20000); + for (Lane = 0; Lane < 4; Lane++) { + Status = (EFI_STATUS) MmioRead32 (HPIPE_ADDR(HpipeBaseAddr, Lane) + + HPIPE_LANE_STATUS0_REG) & HPIPE_LANE_STATUS0_PCLK_EN_MASK; + if (EFI_ERROR(Status)) + DEBUG((DEBUG_ERROR, "ComPhy: PLL is not locked - Failed to initialize " + "Lane %d\n", Lane)); + } + } + + /* + * Set PCIe transactions towards A2 as: + * - read allocate + * - write non alocate + * - outer sharable + */ + RegSet (ComPhyBaseAddr + COMPHY_PCI_MAC_CTRL, COMPHY_PCI_COHERENT << + COMPHY_PCI_AXI_CACHE_OFFSET, COMPHY_PCI_AXI_CACHE_MASK); + + /* Set the Port x1 */ + if (PcieBy4) + RegSet (ComPhyBaseAddr + COMPHY_PCI_MAC_CTRL, 0 << COMPHY_PCI_X1_EN_OFFSET, + COMPHY_PCI_X1_EN_MASK); + else + RegSet (ComPhyBaseAddr + COMPHY_PCI_MAC_CTRL, 1 << COMPHY_PCI_X1_EN_OFFSET, + COMPHY_PCI_X1_EN_MASK); + + /* Enable PCIe unit */ + RegSet (ComPhyBaseAddr + COMPHY_PCI_MAC_CTRL, 1 << COMPHY_PCI_EN_OFFSET, + COMPHY_PCI_EN_MASK); + + return EFI_SUCCESS; +} diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c new file mode 100644 index 0000000..b500064 --- /dev/null +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -0,0 +1,811 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ComPhyLib.h" + +#define SD_ADDR(base, Lane) (base + 0x1000 * Lane) +#define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + 0x800) +#define COMPHY_ADDR(base, Lane) (base + 0x28 * Lane) + +/* + * For CP-110 we have 2 Selector registers "PHY Selectors" + * and " PIPE Selectors". + * PIPE selector include USB and PCIe options. + * PHY selector include the Ethernet and SATA options, every Ethernet option + * has different options, for example: serdes Lane2 had option Eth_port_0 + * that include (SGMII0, XAUI0, RXAUI0, KR) + */ +COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { + /* Lane 0 */ + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, + {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + /* Lane 1 */ + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, + {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + /* Lane 2 */ + {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, + {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, + {PHY_TYPE_SATA0, 0x4} } }, + /* Lane 3 */ + {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, + {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, + {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + /* Lane 4 */ + {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, + {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, + {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, + /* Lane 5 */ + {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, + {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, {PHY_TYPE_XAUI3, 0x1}, + {PHY_TYPE_SATA1, 0x4} } }, +}; + +COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = { + /* Lane 0 */ + {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE0, 0x4} } }, + /* Lane 1 */ + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1}, + {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE0, 0x4} } }, + /* Lane 2 */ + {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1}, + {PHY_TYPE_PCIE0, 0x4} } }, + /* Lane 3 */ + {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1}, + {PHY_TYPE_PCIE0, 0x4} } }, + /* Lane 4 */ + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1}, + {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE1, 0x4} } }, + /* Lane 5 */ + {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE2, 0x4} } }, +}; + +STATIC +EFI_STATUS +ComPhyPciePowerUp ( + IN UINT32 Lane, + IN UINT32 PcieBy4, + IN EFI_PHYSICAL_ADDRESS HpipeBase, + IN EFI_PHYSICAL_ADDRESS ComPhyBase + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Mask, Data, PcieClk = 0; + EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane); + + DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset " + "ComPhy\n")); + /* RFU configurations - hard reset ComPhy */ + Mask = COMMON_PHY_CFG1_PWR_UP_MASK; + Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; + Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; + Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; + Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; + Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; + Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; + Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; + Mask |= COMMON_PHY_PHY_MODE_MASK; + Data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; + RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); + + /* Release from hard reset */ + Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; + Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; + Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; + Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; + RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); + + /* Wait 1ms - until band gap and ref clock ready */ + MicroSecondDelay (1000); + + /* Start ComPhy Configuration */ + DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); + /* Set PIPE soft reset */ + Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; + Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; + /* Set PHY Datapath width mode for V0 */ + Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; + Data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; + /* Set Data bus width USB mode for V0 */ + Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; + Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; + /* Set CORE_CLK output frequency for 250Mhz */ + Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; + Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; + RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask); + /* Set PLL ready delay for 0x2 */ + RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, + 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, + HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); + /* Set PIPE mode interface to PCIe3 - 0x1 */ + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, + 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET, HPIPE_CLK_SRC_HI_MODE_PIPE_MASK); + /* Config update polarity equalization */ + RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG, + 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, HPIPE_CFG_UPDATE_POLARITY_MASK); + /* Set PIPE version 4 to mode enable */ + RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG, + 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK); + + /* Enable PIN clock 100M_125M */ + Mask = HPIPE_MISC_CLK100M_125M_MASK; + Data = 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; + /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */ + Mask |= HPIPE_MISC_TXDCLK_2X_MASK; + Data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; + /* Enable 500MHz Clock */ + Mask |= HPIPE_MISC_CLK500_EN_MASK; + Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; + if (PcieClk) { + /* Set reference clock comes from group 1 */ + Mask |= HPIPE_MISC_REFCLK_SEL_MASK; + Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; + } else { + /* Set reference clock comes from group 2 */ + Mask |= HPIPE_MISC_REFCLK_SEL_MASK; + Data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; + } + RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask); + if (PcieClk) { + /* Set reference frequcency select - 0x2 for 25MHz*/ + Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; + Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; + } else { + /* Set reference frequcency select - 0x0 for 100MHz*/ + Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; + Data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; + } + /* Set PHY mode to PCIe */ + Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; + Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; + RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); + /* + * Set the amount of time spent in the LoZ state - set + * for 0x7 only if the PCIe clock is output + */ + if (PcieClk) + RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL, + 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, + HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); + + /* Set Maximal PHY Generation Setting (8Gbps) */ + Mask = HPIPE_INTERFACE_GEN_MAX_MASK; + Data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; + /* Set Link Train Mode (Tx training control pins are used) */ + Mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; + Data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; + RegSet (HpipeAddr + HPIPE_INTERFACE_REG, Data, Mask); + + /* Set Idle_sync enable */ + Mask = HPIPE_PCIE_IDLE_SYNC_MASK; + Data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; + /* Select bits for PCIE Gen3(32bit) */ + Mask |= HPIPE_PCIE_SEL_BITS_MASK; + Data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; + RegSet (HpipeAddr + HPIPE_PCIE_REG0, Data, Mask); + + /* Enable Tx_adapt_g1 */ + Mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; + Data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; + /* Enable Tx_adapt_gn1 */ + Mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; + Data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; + /* Disable Tx_adapt_g0 */ + Mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; + Data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; + RegSet (HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG, Data, Mask); + + /* Set reg_tx_train_chk_init */ + Mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; + Data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; + /* Enable TX_COE_FM_PIN_PCIE3_EN */ + Mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; + Data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; + RegSet (HpipeAddr + HPIPE_TX_TRAIN_REG, Data, Mask); + + DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); + /* Release from PIPE soft reset */ + RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, + 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); + + /* Wait 15ms - for ComPhy calibration done */ + MicroSecondDelay (15000); + + DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); + /* Read Lane status */ + Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG); + if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) { + DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n", + HpipeAddr + HPIPE_LANE_STATUS0_REG, Data)); + DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n")); + Status = EFI_D_ERROR; + } + + return Status; +} + +STATIC +UINTN +ComphyUsb3PowerUp ( + UINT32 Lane, + EFI_PHYSICAL_ADDRESS HpipeBase, + EFI_PHYSICAL_ADDRESS ComPhyBase + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Mask, Data; + EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane); + + DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset " + "ComPhy\n")); + /* RFU configurations - hard reset ComPhy */ + Mask = COMMON_PHY_CFG1_PWR_UP_MASK; + Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; + Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; + Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; + Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; + Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; + Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; + Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; + Mask |= COMMON_PHY_PHY_MODE_MASK; + Data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; + RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); + + /* Release from hard reset */ + Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; + Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; + Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; + Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; + RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); + + /* Wait 1ms - until band gap and ref clock ready */ + MicroSecondDelay (1000); + + /* Start ComPhy Configuration */ + DEBUG((DEBUG_INFO, "stage: Comphy configuration\n")); + /* Set PIPE soft reset */ + Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; + Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; + /* Set PHY Datapath width mode for V0 */ + Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; + Data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; + /* Set Data bus width USB mode for V0 */ + Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; + Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; + /* Set CORE_CLK output frequency for 250Mhz */ + Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; + Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; + RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask); + /* Set PLL ready delay for 0x2 */ + RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, + 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, + HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); + /* Set reference clock to come from group 1 - 25Mhz */ + RegSet (HpipeAddr + HPIPE_MISC_REG, 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, + HPIPE_MISC_REFCLK_SEL_MASK); + /* Set reference frequcency select - 0x2 */ + Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; + Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; + /* Set PHY mode to USB - 0x5 */ + Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; + Data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; + RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); + /* Set the amount of time spent in the LoZ state - set for 0x7 */ + RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL, + 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, + HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); + /* Set max PHY generation setting - 5Gbps */ + RegSet (HpipeAddr + HPIPE_INTERFACE_REG, + 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK); + /* Set select Data width 20Bit (SEL_BITS[2:0]) */ + RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, + 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); + + /* Start analog paramters from ETP(HW) */ + DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); + /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ + Mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; + Data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; + /* Set Override PHY DFE control pins for 0x1 */ + Mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; + Data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; + /* Set Spread Spectrum Clock Enable fot 0x1 */ + Mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; + Data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; + RegSet (HpipeAddr + HPIPE_LANE_CFG4_REG, Data, Mask); + /* End of analog parameters */ + + DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy power up\n")); + /* Release from PIPE soft reset */ + RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, + 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); + + /* Wait 15ms - for ComPhy calibration done */ + MicroSecondDelay (15000); + + DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); + /* Read Lane status */ + Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG); + if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) { + DEBUG((DEBUG_ERROR, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n")); + Status = EFI_D_ERROR; + } + + return Status; +} + +STATIC +UINT32 +PollingWithTimeout ( + IN EFI_PHYSICAL_ADDRESS addr, + IN UINT32 val, + IN UINT32 mask, + IN UINT64 usec_timeout + ) +{ + UINT32 data; + + do { + MicroSecondDelay(1); + data = MmioRead32(addr) & mask; + } while (data != val && --usec_timeout > 0); + + if (usec_timeout == 0) + return data; + return 0; +} + +STATIC +UINTN +ComPhySataPowerUp ( + IN UINT32 Lane, + IN EFI_PHYSICAL_ADDRESS HpipeBase, + IN EFI_PHYSICAL_ADDRESS ComPhyBase + ) +{ + EFI_STATUS Status; + UINT32 Mask, Data; + EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane); + EFI_PHYSICAL_ADDRESS SataBase; + + SataBase = PcdGet32 (PcdSataBaseAddress); + if (SataBase == 0) { + DEBUG((DEBUG_INFO, "ComPhy: SATA address not found in FDT\n")); + return EFI_D_ERROR; + } + + DEBUG((DEBUG_INFO, "ComPhy: stage: MAC configuration - power down " + "ComPhy\n")); + /* + * MAC configuration - power down ComPhy + * Use indirect address for vendor specific SATA control register + */ + RegSet (SataBase + SATA3_VENDOR_ADDRESS, + SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, SATA3_VENDOR_ADDR_MASK); + /* SATA 0 power down */ + Mask = SATA3_CTRL_SATA0_PD_MASK; + Data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; + /* SATA 1 power down */ + Mask |= SATA3_CTRL_SATA1_PD_MASK; + Data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; + /* SATA SSU disable */ + Mask |= SATA3_CTRL_SATA1_ENABLE_MASK; + Data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; + /* SATA port 1 disable */ + Mask |= SATA3_CTRL_SATA_SSU_MASK; + Data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; + RegSet (SataBase + SATA3_VENDOR_DATA, Data, Mask); + + DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset " + "ComPhy\n")); + /* RFU configurations - hard reset ComPhy */ + Mask = COMMON_PHY_CFG1_PWR_UP_MASK; + Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; + Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; + Data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; + Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; + Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; + Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; + Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; + RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); + + /* Set select Data width 40Bit - SATA mode only */ + RegSet (ComPhyAddr + COMMON_PHY_CFG6_REG, + 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, COMMON_PHY_CFG6_IF_40_SEL_MASK); + + /* Release from hard reset in SD external */ + Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; + Data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; + Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; + Data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; + RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask); + + /* Wait 1ms - until band gap and ref clock ready */ + MicroSecondDelay (1000); + + DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy configuration\n")); + /* Start ComPhy Configuration */ + /* Set reference clock to comes from group 1 - choose 25Mhz */ + RegSet (HpipeAddr + HPIPE_MISC_REG, + 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, HPIPE_MISC_REFCLK_SEL_MASK); + /* Reference frequency select set 1 (for SATA = 25Mhz) */ + Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; + Data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; + /* PHY mode select (set SATA = 0x0 */ + Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; + Data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; + RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); + /* Set max PHY generation setting - 6Gbps */ + RegSet (HpipeAddr + HPIPE_INTERFACE_REG, + 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK); + /* Set select Data width 40Bit (SEL_BITS[2:0]) */ + RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, + 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); + + DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); + + /* DFE reset sequence */ + RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, + 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, + 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + /* SW reset for interupt logic */ + RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, + 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, + 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + + DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); + /* + * MAC configuration - power up ComPhy - power up PLL/TX/RX + * Use indirect address for vendor specific SATA control register + */ + RegSet (SataBase + SATA3_VENDOR_ADDRESS, + SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, SATA3_VENDOR_ADDR_MASK); + /* SATA 0 power up */ + Mask = SATA3_CTRL_SATA0_PD_MASK; + Data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; + /* SATA 1 power up */ + Mask |= SATA3_CTRL_SATA1_PD_MASK; + Data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; + /* SATA SSU enable */ + Mask |= SATA3_CTRL_SATA1_ENABLE_MASK; + Data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; + /* SATA port 1 enable */ + Mask |= SATA3_CTRL_SATA_SSU_MASK; + Data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; + RegSet (SataBase + SATA3_VENDOR_DATA, Data, Mask); + + /* Wait 15ms - Wait for ComPhy calibration done */ + MicroSecondDelay (15000); + + /* + * Reduce read & write burst size to 64 byte due to bug in + * AP-806-Z Aurora 2 that prohibits writes larger than 64 byte + */ + MmioWrite32(SataBase + SATA3_VENDOR_ADDRESS, 0x4); + Mask = 0x77; + Data = 0x44; /* 4 = 64 bytes burst */ + RegSet (SataBase + SATA3_VENDOR_DATA, Data, Mask); + + /* MBUS request size and interface select register */ + RegSet (SataBase + SATA3_VENDOR_ADDRESS, + SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, + SATA3_VENDOR_ADDR_MASK); + /* Mbus regret enable */ + RegSet (SataBase + SATA3_VENDOR_DATA, 0x1 << SATA_MBUS_REGRET_EN_OFFSET, + SATA_MBUS_REGRET_EN_MASK); + + DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); + Data = MmioRead32(SdIpAddr + SD_EXTERNAL_STATUS0_REG); + + /* Check the PLL TX */ + if ((Data & SD_EXTERNAL_STATUS0_PLL_TX_MASK) == 0) { + DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_TX is 0\n")); + Status = EFI_D_ERROR; + } + + /* Check the PLL RX */ + if ((Data & SD_EXTERNAL_STATUS0_PLL_RX_MASK) == 0) { + DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_RX is 0\n")); + Status = EFI_D_ERROR; + } + + return Status; +} + +STATIC +UINTN +ComPhySgmiiPowerUp ( + IN UINT32 Lane, + IN UINT32 SgmiiSpeed, + IN EFI_PHYSICAL_ADDRESS HpipeBase, + IN EFI_PHYSICAL_ADDRESS ComPhyBase + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Mask, Data; + EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane); + EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane); + EFI_PHYSICAL_ADDRESS Addr; + + DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset " + "ComPhy\n")); + /* RFU configurations - hard reset ComPhy */ + Mask = COMMON_PHY_CFG1_PWR_UP_MASK; + Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; + Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; + Data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; + RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); + + /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ + Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; + Data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; + Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; + Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; + if (SgmiiSpeed == PHY_SPEED_1_25G) { + Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; + Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; + } else { + /* 3.125G */ + Data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; + Data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; + } + Mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; + Data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; + Mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; + Data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; + Mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; + Data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; + RegSet (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, Data, Mask); + + /* Release from hard reset */ + Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; + Data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; + Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; + Data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; + Mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; + Data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; + RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask); + + /* Release from hard reset */ + Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; + Data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; + Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; + Data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; + RegSet (SdIpAddr+ SD_EXTERNAL_CONFIG1_REG, Data, Mask); + + /* Wait 1ms - until band gap and ref clock ready */ + MicroSecondDelay (1000); + + /* Start ComPhy Configuration */ + DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); + /* Set reference clock */ + Mask = HPIPE_MISC_REFCLK_SEL_MASK; + Data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; + RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask); + /* Power and PLL Control */ + Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; + Data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; + Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; + Data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; + RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); + /* Loopback register */ + Mask = HPIPE_LOOPBACK_SEL_MASK; + Data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; + RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, Data, Mask); + /* Rx control 1 */ + Mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; + Data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; + Mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; + Data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; + RegSet (HpipeAddr + HPIPE_RX_CONTROL_1_REG, Data, Mask); + /* DTL Control */ + Mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; + Data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; + RegSet (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, Data, Mask); + + /* Set analog paramters from ETP(HW) - for now use the default data */ + DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); + + RegSet (HpipeAddr + HPIPE_G1_SET_0_REG, + 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); + + DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up " + "PLL,Tx,Rx\n")); + /* SerDes External Configuration */ + Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; + Data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; + Mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; + Data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; + Mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; + Data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; + RegSet (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, Data, Mask); + + /* Check PLL rx & tx ready */ + Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG; + Data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | SD_EXTERNAL_STATUS0_PLL_TX_MASK; + Mask = Data; + Data = PollingWithTimeout (Addr, Data, Mask, 15000); + if (Data != 0) { + DEBUG((DEBUG_ERROR, "ComPhy: Read from reg = %p - value = 0x%x\n", + SdIpAddr + SD_EXTERNAL_STATUS0_REG, Data)); + DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_RX is %d, " + "SD_EXTERNAL_STATUS0_PLL_TX is %d\n", + (Data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), + (Data & SD_EXTERNAL_STATUS0_PLL_TX_MASK))); + Status = EFI_D_ERROR; + } + + /* RX init */ + Mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; + Data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; + RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask); + + /* Check that RX init done */ + Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG; + Data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; + Mask = Data; + Data = PollingWithTimeout (Addr, Data, Mask, 100); + if (Data != 0) { + DEBUG((DEBUG_ERROR, "ComPhy: Read from reg = %p - value = 0x%x\n", + SdIpAddr + SD_EXTERNAL_STATUS0_REG, Data)); + DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_RX_INIT is 0\n")); + Status = EFI_D_ERROR; + } + Mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; + Data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; + Mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; + Data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; + RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask); + return Status; +} + +STATIC +VOID +ComPhyMuxCp110 ( + IN CHIP_COMPHY_CONFIG *PtrChipCfg, + IN COMPHY_MAP *SerdesMap + ) +{ + EFI_PHYSICAL_ADDRESS ComPhyBaseAddr; + COMPHY_MAP ComPhyMapPipeData[MAX_LANE_OPTIONS]; + COMPHY_MAP ComPhyMapPhyData[MAX_LANE_OPTIONS]; + UINT32 Lane, ComPhyMaxCount; + + ComPhyMaxCount = PtrChipCfg->LanesCount; + ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr; + + /* + * Copy the SerDes map configuration for PIPE map and PHY map. + * The ComPhyMuxInit modifies the Type of the Lane if the Type is not valid. + * Because we have 2 selectors, run the ComPhyMuxInit twice and after + * that, update the original SerdesMap. + */ + for (Lane = 0; Lane < ComPhyMaxCount; Lane++) { + ComPhyMapPipeData[Lane].Type = SerdesMap[Lane].Type; + ComPhyMapPipeData[Lane].Speed = SerdesMap[Lane].Speed; + ComPhyMapPhyData[Lane].Type = SerdesMap[Lane].Type; + ComPhyMapPhyData[Lane].Speed = SerdesMap[Lane].Speed; + } + PtrChipCfg->MuxData = Cp110ComPhyMuxData; + ComPhyMuxInit(PtrChipCfg, ComPhyMapPhyData, ComPhyBaseAddr + + COMMON_SELECTOR_PHY_OFFSET); + + PtrChipCfg->MuxData = Cp110ComPhyPipeMuxData; + ComPhyMuxInit(PtrChipCfg, ComPhyMapPipeData, ComPhyBaseAddr + + COMMON_SELECTOR_PIPE_OFFSET); + + /* Fix the Type after check the PHY and PIPE configuration */ + for (Lane = 0; Lane < ComPhyMaxCount; Lane++) + if ((ComPhyMapPipeData[Lane].Type == PHY_TYPE_UNCONNECTED) && + (ComPhyMapPhyData[Lane].Type == PHY_TYPE_UNCONNECTED)) + SerdesMap[Lane].Type = PHY_TYPE_UNCONNECTED; +} + +EFI_STATUS +ComPhyCp110Init ( + IN CHIP_COMPHY_CONFIG *PtrChipCfg + ) +{ + EFI_STATUS Status; + COMPHY_MAP *PtrComPhyMap, *SerdesMap; + EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; + UINT32 ComPhyMaxCount, Lane; + UINT32 PcieBy4 = 1; + + ComPhyMaxCount = PtrChipCfg->LanesCount; + ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr; + HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr; + SerdesMap = PtrChipCfg->MapData; + + /* Config Comphy mux configuration */ + ComPhyMuxCp110(PtrChipCfg, SerdesMap); + + /* Check if the first 4 Lanes configured as By-4 */ + for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) { + if (PtrComPhyMap->Type != PHY_TYPE_PCIE0) { + PcieBy4 = 0; + break; + } + } + + for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount; + Lane++, PtrComPhyMap++) { + DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane)); + DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type)); + switch (PtrComPhyMap->Type) { + case PHY_TYPE_UNCONNECTED: + continue; + break; + case PHY_TYPE_PCIE0: + case PHY_TYPE_PCIE1: + case PHY_TYPE_PCIE2: + case PHY_TYPE_PCIE3: + Status = ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBaseAddr); + break; + case PHY_TYPE_SATA0: + case PHY_TYPE_SATA1: + case PHY_TYPE_SATA2: + case PHY_TYPE_SATA3: + Status = ComPhySataPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); + break; + case PHY_TYPE_USB3_HOST0: + case PHY_TYPE_USB3_HOST1: + Status = ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); + break; + case PHY_TYPE_SGMII0: + case PHY_TYPE_SGMII1: + case PHY_TYPE_SGMII2: + Status = ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAddr, + ComPhyBaseAddr); + break; + default: + DEBUG((DEBUG_ERROR, "Unknown SerDes Type, skip initialize SerDes %d\n", + Lane)); + break; + } + if (EFI_ERROR(Status)) + DEBUG((DEBUG_ERROR, "PLL is not locked - Failed to initialize Lane %d\n", + Lane)); + } + + return EFI_SUCCESS; +} diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c new file mode 100644 index 0000000..12b7d73 --- /dev/null +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -0,0 +1,277 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ComPhyLib.h" + +CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", + L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3", + L"SGMII0", L"SGMII1", L"SGMII2", L"SGMII3", + L"QSGMII", L"USB3_HOST0", L"USB3_HOST1", + L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2", + L"XAUI3", L"RXAUI0", L"RXAUI1", L"KR"}; + +CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps", + L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", + L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"}; + +CHIP_COMPHY_CONFIG ChipCfgTbl[] = { + { + .ChipType = L"Ap806", + .Init = ComPhyAp806Init + }, + { + .ChipType = L"Cp110", + .Init = ComPhyCp110Init + } +}; + +VOID +RegSet ( + IN EFI_PHYSICAL_ADDRESS Addr, + IN UINT32 Data, + IN UINT32 Mask + ) +{ + DEBUG((DEBUG_INFO, "Write to address = %10x, data = %10x (mask = %10x)" + "- ", Addr, Data, Mask)); + DEBUG((DEBUG_INFO, "old value = %10x ==> ", MmioRead32 (Addr))); + RegSetSilent (Addr, Data, Mask); + DEBUG((DEBUG_INFO, "new value %10x\n", MmioRead32 (Addr))); +} + +VOID +RegSetSilent ( + IN EFI_PHYSICAL_ADDRESS Addr, + IN UINT32 Data, + IN UINT32 Mask + ) +{ + UINT32 RegData; + + RegData = MmioRead32 (Addr); + RegData &= ~Mask; + RegData |= Data; + MmioWrite32 (Addr, RegData); +} + +VOID +RegSet16 ( + IN EFI_PHYSICAL_ADDRESS Addr, + IN UINT16 Data, + IN UINT16 Mask + ) +{ + DEBUG((DEBUG_INFO, "Write to address = %#010lx, Data = %#06x (mask = %#06x)" + "- ", Addr, Data, Mask)); + DEBUG((DEBUG_INFO, "old value = %#06x ==> ", MmioRead16 (Addr))); + RegSetSilent16 (Addr, Data, Mask); + DEBUG((DEBUG_INFO, "new value %#06x\n", MmioRead16 (Addr))); +} + +VOID +RegSetSilent16( + IN EFI_PHYSICAL_ADDRESS Addr, + IN UINT16 Data, + IN UINT16 Mask + ) +{ + UINT16 RegData; + RegData = MmioRead16(Addr); + RegData &= ~Mask; + RegData |= Data; + MmioWrite16 (Addr, RegData); +} + +/* This function returns enum with SerDesType */ +UINT32 +ParseSerdesTypeString ( + CHAR16* String + ) +{ + UINT32 i; + + if (String == NULL) + return PHY_TYPE_INVALID; + + for (i = 0; i < PHY_TYPE_MAX; i++) { + if (StrCmp (String, TypeStringTable[i]) == 0) { + return i; + } + } + + /* PCD string doesn't match any supported SerDes Type */ + return PHY_TYPE_INVALID; +} + +/* This function converts SerDes speed in MHz to enum with SerDesSpeed */ +UINT32 +ParseSerdesSpeed ( + UINT32 Value + ) +{ + UINT32 i; + UINT32 ValueTable [] = {0, 1250, 1500, 2500, 3000, 3125, + 5000, 6000, 6250, 1031}; + + for (i = 0; i < 10; i++) { + if (Value == ValueTable[i]) { + return i; + } + } + + /* PCD SerDes speed value doesn't match any supported SerDes speed */ + return PHY_SPEED_INVALID; +} + +CHAR16 * +GetTypeString ( + UINT32 Type + ) +{ + + if (Type < 0 || Type > PHY_TYPE_MAX) { + return L"invalid"; + } + + return TypeStringTable[Type]; +} + +CHAR16 * +GetSpeedString ( + UINT32 Speed + ) +{ + + if (Speed < 0 || Speed > 10) { + return L"invalid"; + } + + return SpeedStringTable[Speed]; +} + +VOID +ComPhyPrint ( + IN CHIP_COMPHY_CONFIG *PtrChipCfg + ) +{ + UINT32 Lane; + CHAR16 *SpeedStr, *TypeStr; + + for (Lane = 0; Lane < PtrChipCfg->LanesCount; Lane++) { + SpeedStr = GetSpeedString(PtrChipCfg->MapData[Lane].Speed); + TypeStr = GetTypeString(PtrChipCfg->MapData[Lane].Type); + DEBUG((DEBUG_ERROR, "Comphy-%d: %-13s %-10s\n", Lane, TypeStr, SpeedStr)); + } + + DEBUG((DEBUG_ERROR, "\n")); +} + +EFI_STATUS +GetChipComPhyInit ( + IN CHIP_COMPHY_CONFIG *PtrChipCfg + ) +{ + UINTN i, TblSize; + + + TblSize = sizeof(ChipCfgTbl) / sizeof(ChipCfgTbl[0]); + + for (i = 0; i < TblSize ; i++) { + if (StrCmp (PtrChipCfg->ChipType, ChipCfgTbl[i].ChipType) == 0) { + PtrChipCfg->Init = ChipCfgTbl[i].Init; + return EFI_SUCCESS; + } + } + + DEBUG((DEBUG_ERROR, "ComPhy: Empty ChipType string\n")); + return EFI_D_ERROR; +} + +EFI_STATUS +ComPhyInit ( + VOID + ) +{ + EFI_STATUS Status; + CHIP_COMPHY_CONFIG ChipConfig[MAX_CHIPS], *PtrChipCfg; + PCD_LANE_MAP LaneData[MAX_CHIPS]; + UINT32 Lane, ChipCount, i, MaxComphyCount; + + ChipCount = PcdGet32 (PcdComPhyChipCount); + + GetComPhyPcd(0); + GetComPhyPcd(1); + GetComPhyPcd(2); + GetComPhyPcd(3); + + if (ChipCount <= 0) + return EFI_INVALID_PARAMETER; + + for (i = 0; i < ChipCount ; i++) { + PtrChipCfg = &ChipConfig[i]; + + /* Get the count of the SerDes of the specific chip */ + MaxComphyCount = PtrChipCfg->LanesCount; + for (Lane = 0; Lane < MaxComphyCount; Lane++) { + /* Parse PCD with string indicating SerDes Type */ + PtrChipCfg->MapData[Lane].Type = + ParseSerdesTypeString (LaneData[i].TypeStr[Lane]); + PtrChipCfg->MapData[Lane].Speed = + ParseSerdesSpeed (LaneData[i].SpeedValue[Lane]); + PtrChipCfg->MapData[Lane].Invert = (UINT32) LaneData[i].InvFlag[Lane]; + + if ((PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_INVALID) || + (PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_ERROR) || + (PtrChipCfg->MapData[Lane].Type == PHY_TYPE_INVALID)) { + DEBUG((DEBUG_ERROR, "ComPhy: No valid phy speed or type for lane %d, " + "setting lane as unconnected\n", Lane + 1)); + PtrChipCfg->MapData[Lane].Type = PHY_TYPE_UNCONNECTED; + PtrChipCfg->MapData[Lane].Speed = PHY_SPEED_INVALID; + } + }; + + Status = GetChipComPhyInit (PtrChipCfg); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "ComPhy: Invalid Chip%dType name\n", i)); + return Status; + } + + ComPhyPrint (PtrChipCfg); + + /* PHY power UP sequence */ + PtrChipCfg->Init (PtrChipCfg); + } + + return EFI_SUCCESS; +} diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h new file mode 100644 index 0000000..51a3e42 --- /dev/null +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -0,0 +1,457 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __COMPHY_H__ +#define __COMPHY_H__ + +#include <Library/ArmLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> +#include <Library/TimerLib.h> +#include <Library/ParsePcdLib.h> + +#define MAX_LANE_OPTIONS 10 +#define MAX_CHIPS 4 + +/***** Parsing PCD *****/ +#define GET_TYPE_STRING(id) _PCD_GET_MODE_PTR_PcdChip##id##Compatible +#define GET_LANE_TYPE(id) _PCD_GET_MODE_PTR_PcdChip##id##ComPhyTypes +#define GET_LANE_SPEED(id) _PCD_GET_MODE_PTR_PcdChip##id##ComPhySpeeds +#define GET_LANE_INV(id) _PCD_GET_MODE_PTR_PcdChip##id##ComPhyInvFlags +#define GET_COMPHY_BASE_ADDR(id) _PCD_GET_MODE_64_PcdChip##id##ComPhyBaseAddress +#define GET_HPIPE3_BASE_ADDR(id) _PCD_GET_MODE_64_PcdChip##id##Hpipe3BaseAddress +#define GET_MUX_BIT_COUNT(id) _PCD_GET_MODE_32_PcdChip##id##ComPhyMuxBitCount +#define GET_MAX_LANES(id) _PCD_GET_MODE_32_PcdChip##id##ComPhyMaxLanes + +#define FillLaneMap(id) { \ + ParsePcdString((CHAR16 *) GET_LANE_TYPE(id), ChipConfig[id].LanesCount, NULL, LaneData[id].TypeStr); \ + ParsePcdString((CHAR16 *) GET_LANE_SPEED(id), ChipConfig[id].LanesCount, LaneData[id].SpeedValue, NULL); \ + ParsePcdString((CHAR16 *) GET_LANE_INV(id), ChipConfig[id].LanesCount, LaneData[id].InvFlag, NULL); \ +} + +#define GetComPhyPcd(id) { \ + ChipConfig[id].ChipType = (CHAR16 *) GET_TYPE_STRING(id); \ + ChipConfig[id].ComPhyBaseAddr = GET_COMPHY_BASE_ADDR(id); \ + ChipConfig[id].Hpipe3BaseAddr = GET_HPIPE3_BASE_ADDR(id); \ + ChipConfig[id].MuxBitCount = GET_MUX_BIT_COUNT(id); \ + ChipConfig[id].LanesCount = GET_MAX_LANES(id); \ + FillLaneMap(id); \ +} + +/***** ComPhy *****/ +#define PHY_SPEED_ERROR 0 +#define PHY_SPEED_1_25G 1 +#define PHY_SPEED_1_5G 2 +#define PHY_SPEED_2_5G 3 +#define PHY_SPEED_3G 4 +#define PHY_SPEED_3_125G 5 +#define PHY_SPEED_5G 6 +#define PHY_SPEED_6G 7 +#define PHY_SPEED_6_25G 8 +#define PHY_SPEED_10_3125G 9 +#define PHY_SPEED_MAX 10 +#define PHY_SPEED_INVALID 0xff + +#define PHY_TYPE_UNCONNECTED 0 +#define PHY_TYPE_PCIE0 1 +#define PHY_TYPE_PCIE1 2 +#define PHY_TYPE_PCIE2 3 +#define PHY_TYPE_PCIE3 4 +#define PHY_TYPE_SATA0 5 +#define PHY_TYPE_SATA1 6 +#define PHY_TYPE_SATA2 7 +#define PHY_TYPE_SATA3 8 +#define PHY_TYPE_SGMII0 9 +#define PHY_TYPE_SGMII1 10 +#define PHY_TYPE_SGMII2 11 +#define PHY_TYPE_SGMII3 12 +#define PHY_TYPE_QSGMII 13 +#define PHY_TYPE_USB3_HOST0 14 +#define PHY_TYPE_USB3_HOST1 15 +#define PHY_TYPE_USB3_DEVICE 16 +#define PHY_TYPE_XAUI0 17 +#define PHY_TYPE_XAUI1 18 +#define PHY_TYPE_XAUI2 19 +#define PHY_TYPE_XAUI3 20 +#define PHY_TYPE_RXAUI0 21 +#define PHY_TYPE_RXAUI1 22 +#define PHY_TYPE_KR 23 +#define PHY_TYPE_MAX 24 +#define PHY_TYPE_INVALID 0xff + +#define PHY_POLARITY_NO_INVERT 0 +#define PHY_POLARITY_TXD_INVERT 1 +#define PHY_POLARITY_RXD_INVERT 2 +#define PHY_POLARITY_ALL_INVERT (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) + +/***** SerDes IP registers *****/ +#define SD_EXTERNAL_CONFIG0_REG 0 +#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 +#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 +#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 +#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) +#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 +#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) + +#define SD_EXTERNAL_CONFIG1_REG 0x4 +#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 +#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) +#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 +#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) +#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 +#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) +#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 +#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) + + +#define SD_EXTERNAL_STATUS0_REG 0x18 +#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 +#define SD_EXTERNAL_STATUS0_PLL_TX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) +#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 +#define SD_EXTERNAL_STATUS0_PLL_RX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) +#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 +#define SD_EXTERNAL_STATUS0_RX_INIT_MASK (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) + +/***** HPIPE registers *****/ +#define HPIPE_PWR_PLL_REG 0x4 +#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 +#define HPIPE_PWR_PLL_REF_FREQ_MASK (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) +#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 +#define HPIPE_PWR_PLL_PHY_MODE_MASK (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) + +#define HPIPE_KVCO_CALIB_CTRL_REG 0x8 +#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 +#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) + +#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 + +#define HPIPE_DFE_REG0 0x01C +#define HPIPE_DFE_RES_FORCE_OFFSET 15 +#define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) + + +#define HPIPE_DFE_F3_F5_REG 0x028 +#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 +#define HPIPE_DFE_F3_F5_DFE_EN_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) +#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 +#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) + +#define HPIPE_G1_SET_0_REG 0x034 +#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 +#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) + +#define HPIPE_G1_SET_1_REG 0x038 +#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 +#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 +#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 +#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) + +#define HPIPE_G2_SETTINGS_1_REG 0x040 + +#define HPIPE_LOOPBACK_REG 0x08c +#define HPIPE_LOOPBACK_SEL_OFFSET 1 +#define HPIPE_LOOPBACK_SEL_MASK (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) + +#define HPIPE_SYNC_PATTERN_REG 0x090 + +#define HPIPE_INTERFACE_REG 0x94 +#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 +#define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 +#define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) + +#define HPIPE_ISOLATE_MODE_REG 0x98 +#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 +#define HPIPE_ISOLATE_MODE_GEN_RX_MASK (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) +#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 +#define HPIPE_ISOLATE_MODE_GEN_TX_MASK (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) + +#define HPIPE_VTHIMPCAL_CTRL_REG 0x104 + +#define HPIPE_PCIE_REG0 0x120 +#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 +#define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) +#define HPIPE_PCIE_SEL_BITS_OFFSET 13 +#define HPIPE_PCIE_SEL_BITS_MASK (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) + +#define HPIPE_LANE_ALIGN_REG 0x124 +#define HPIPE_LANE_ALIGN_OFF_OFFSET 12 +#define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) + +#define HPIPE_MISC_REG 0x13C +#define HPIPE_MISC_CLK100M_125M_OFFSET 4 +#define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) +#define HPIPE_MISC_TXDCLK_2X_OFFSET 6 +#define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) +#define HPIPE_MISC_CLK500_EN_OFFSET 7 +#define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) +#define HPIPE_MISC_REFCLK_SEL_OFFSET 10 +#define HPIPE_MISC_REFCLK_SEL_MASK (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) + +#define HPIPE_RX_CONTROL_1_REG 0x140 +#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 +#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) +#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 +#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) + +#define HPIPE_PWR_CTR_REG 0x148 +#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 +#define HPIPE_PWR_CTR_RST_DFE_MASK (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) +#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 +#define HPIPE_PWR_CTR_SFT_RST_MASK (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) + +#define HPIPE_PLLINTP_REG1 0x150 + +#define HPIPE_PWR_CTR_DTL_REG 0x184 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 0x2 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) + +#define HPIPE_RX_REG3 0x188 + +#define HPIPE_TX_TRAIN_CTRL_REG 0x26C +#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 +#define HPIPE_TX_TRAIN_CTRL_G1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 +#define HPIPE_TX_TRAIN_CTRL_GN1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 +#define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) + +#define HPIPE_PCIE_REG1 0x288 +#define HPIPE_PCIE_REG3 0x290 + +#define HPIPE_TX_TRAIN_REG 0x31C +#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 +#define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) + +#define HPIPE_G1_SETTINGS_3_REG 0x440 +#define HPIPE_G1_SETTINGS_4_REG 0x444 +#define HPIPE_G2_SETTINGS_3_REG 0x448 +#define HPIPE_G2_SETTINGS_4_REG 0x44C + +#define HPIPE_DFE_CTRL_28_REG 0x49C +#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 +#define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) + +#define HPIPE_LANE_CONFIG0_REG 0x604 +#define HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET 9 +#define HPIPE_LANE_CONFIG0_MAX_PLL_MASK (0x1 << HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET) +#define HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET 10 +#define HPIPE_LANE_CONFIG0_GEN2_PLL_MASK (0x1 << HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET) + +#define HPIPE_LANE_STATUS0_REG 0x60C +#define HPIPE_LANE_STATUS0_PCLK_EN_OFFSET 0 +#define HPIPE_LANE_STATUS0_PCLK_EN_MASK (0x1 << HPIPE_LANE_STATUS0_PCLK_EN_OFFSET) + +#define HPIPE_LANE_CFG4_REG 0x620 +#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 +#define HPIPE_LANE_CFG4_DFE_CTRL_MASK (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 +#define HPIPE_LANE_CFG4_DFE_OVER_MASK (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) +#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 +#define HPIPE_LANE_CFG4_SSC_CTRL_MASK (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) + +#define HPIPE_LANE_EQ_CFG1_REG 0x6a0 +#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 +#define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) + +#define HPIPE_RST_CLK_CTRL_REG 0x704 +#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 +#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) + +#define HPIPE_CLK_SRC_LO_REG 0x70c +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) + +#define HPIPE_CLK_SRC_HI_REG 0x710 +#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 +#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 +#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 +#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) +#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 +#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) + +#define HPIPE_GLOBAL_MISC_CTRL 0x718 +#define HPIPE_GLOBAL_PM_CTRL 0x740 +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) + +/***** COMPHY registers *****/ +#define COMMON_PHY_CFG1_REG 0x0 +#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 +#define COMMON_PHY_CFG1_PWR_UP_MASK (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) +#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 +#define COMMON_PHY_CFG1_PIPE_SELECT_MASK (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) +#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13 +#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) +#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14 +#define COMMON_PHY_CFG1_CORE_RSTN_MASK (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) +#define COMMON_PHY_PHY_MODE_OFFSET 15 +#define COMMON_PHY_PHY_MODE_MASK (0x1 << COMMON_PHY_PHY_MODE_OFFSET) + +#define COMMON_PHY_CFG6_REG 0x14 +#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 +#define COMMON_PHY_CFG6_IF_40_SEL_MASK (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) + +#define COMMON_SELECTOR_PHY_OFFSET 0x140 +#define COMMON_SELECTOR_PIPE_OFFSET 0x144 + +/***** SATA registers *****/ +#define SATA3_VENDOR_ADDRESS 0xA0 +#define SATA3_VENDOR_ADDR_OFSSET 0 +#define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET) +#define SATA3_VENDOR_DATA 0xA4 + +#define SATA_CONTROL_REG 0x0 +#define SATA3_CTRL_SATA0_PD_OFFSET 6 +#define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET) +#define SATA3_CTRL_SATA1_PD_OFFSET 14 +#define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET) +#define SATA3_CTRL_SATA1_ENABLE_OFFSET 22 +#define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET) +#define SATA3_CTRL_SATA_SSU_OFFSET 23 +#define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET) + +#define SATA_MBUS_SIZE_SELECT_REG 0x4 +#define SATA_MBUS_REGRET_EN_OFFSET 7 +#define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET) + +/***************************/ + +typedef struct _CHIP_COMPHY_CONFIG CHIP_COMPHY_CONFIG; + +typedef struct { + UINT32 Type; + UINT32 MuxValue; +} COMPHY_MUX_OPTIONS; + +typedef struct { + UINT32 MaxLaneValues; + COMPHY_MUX_OPTIONS MuxValues[MAX_LANE_OPTIONS]; +} COMPHY_MUX_DATA; + +typedef struct { + UINT32 Type; + UINT32 Speed; + UINT32 Invert; +} COMPHY_MAP; + +typedef struct { + CHAR16 *TypeStr[MAX_LANE_OPTIONS]; + UINTN SpeedValue[MAX_LANE_OPTIONS]; + UINTN InvFlag[MAX_LANE_OPTIONS]; +} PCD_LANE_MAP; + +typedef +EFI_STATUS +(*COMPHY_CHIP_INIT) ( + IN CHIP_COMPHY_CONFIG *PtrChipCfg + ); + +struct _CHIP_COMPHY_CONFIG { + CHAR16* ChipType; + COMPHY_MAP MapData[MAX_LANE_OPTIONS]; + COMPHY_MUX_DATA *MuxData; + EFI_PHYSICAL_ADDRESS ComPhyBaseAddr; + EFI_PHYSICAL_ADDRESS Hpipe3BaseAddr; + COMPHY_CHIP_INIT Init; + UINT32 LanesCount; + UINT32 MuxBitCount; +}; + +VOID +ComPhyMuxInit ( + IN CHIP_COMPHY_CONFIG *PtrChipCfg, + IN COMPHY_MAP *ComPhyMapData, + IN EFI_PHYSICAL_ADDRESS SelectorBase + ); + +EFI_STATUS +ComPhyAp806Init ( + IN CHIP_COMPHY_CONFIG * First + ); + +EFI_STATUS +ComPhyCp110Init ( + IN CHIP_COMPHY_CONFIG * First + ); + +VOID +RegSet ( + IN EFI_PHYSICAL_ADDRESS Addr, + IN UINT32 Data, + IN UINT32 Mask + ); + +VOID +RegSetSilent ( + IN EFI_PHYSICAL_ADDRESS Addr, + IN UINT32 Data, + IN UINT32 Mask + ); + +VOID +RegSet16 ( + IN EFI_PHYSICAL_ADDRESS Addr, + IN UINT16 Data, + IN UINT16 Mask + ); + +VOID +RegSetSilent16( + IN EFI_PHYSICAL_ADDRESS Addr, + IN UINT16 Data, + IN UINT16 Mask + ); +#endif // __COMPHY_H__ diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf new file mode 100644 index 0000000..80f7d34 --- /dev/null +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -0,0 +1,110 @@ +# Copyright (C) 2016 Marvell International Ltd. +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute and/or +# modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MarvellComPhyLib + FILE_GUID = 3314541a-9647-4a37-b8c6-24e000900e4e + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ComPhyLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec + +[LibraryClasses] + ArmLib + DebugLib + MemoryAllocationLib + PcdLib + IoLib + ParsePcdLib + +[Sources.common] + ComPhyLib.c + ComPhyCp110.c + ComPhyAp806.c + ComPhyMux.c + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdComPhyChipCount + + #Chip0 + gMarvellTokenSpaceGuid.PcdChip0Compatible + gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress + gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress + gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount + gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes + + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds + gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + + #Chip1 + gMarvellTokenSpaceGuid.PcdChip1Compatible + gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress + gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress + gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount + gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes + + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds + gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags + + #Chip2 + gMarvellTokenSpaceGuid.PcdChip2Compatible + gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress + gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress + gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount + gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes + + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds + gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags + + #Chip3 + gMarvellTokenSpaceGuid.PcdChip3Compatible + gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress + gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress + gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount + gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes + + gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes + gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds + gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags + + #SATA + gMarvellTokenSpaceGuid.PcdSataBaseAddress diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c new file mode 100644 index 0000000..595745b --- /dev/null +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c @@ -0,0 +1,132 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ComPhyLib.h" + +STATIC +VOID +ComPhyMuxCheckConfig ( + IN COMPHY_MUX_DATA *MuxData, + IN COMPHY_MAP *ComPhyMapData, + IN UINTN ComPhyMaxLanes + ) +{ + COMPHY_MUX_OPTIONS *PtrMuxOpt; + UINTN Lane, Opt, Valid; + + for (Lane = 0; Lane < ComPhyMaxLanes; Lane++, ComPhyMapData++, MuxData++) { + PtrMuxOpt = MuxData->MuxValues; + for (Opt = 0, Valid = 0; Opt < MuxData->MaxLaneValues; Opt++, PtrMuxOpt++) { + if (PtrMuxOpt->Type == ComPhyMapData->Type) { + Valid = 1; + break; + } + } + if (Valid == 0) { + DEBUG((DEBUG_INFO, "Lane number %d, had invalid Type %d\n", Lane, + ComPhyMapData->Type)); + DEBUG((DEBUG_INFO, "Set Lane %d as Type %d\n", Lane, + PHY_TYPE_UNCONNECTED)); + ComPhyMapData->Type = PHY_TYPE_UNCONNECTED; + } else { + DEBUG((DEBUG_INFO, "Lane number %d, has Type %d\n", Lane, + ComPhyMapData->Type)); + } + } +} + +STATIC +UINT32 +ComPhyMuxGetMuxValue ( + IN COMPHY_MUX_DATA *MuxData, + IN UINT32 Type, + IN UINTN Lane + ) +{ + COMPHY_MUX_OPTIONS *PtrMuxOpt; + UINTN Opt; + UINT32 Value = 0; + + PtrMuxOpt = MuxData->MuxValues; + for (Opt = 0 ; Opt < MuxData->MaxLaneValues; Opt++, PtrMuxOpt++) + if (PtrMuxOpt->Type == Type) { + Value = PtrMuxOpt->MuxValue; + break; + } + + return Value; +} + +STATIC +VOID +ComPhyMuxRegWrite ( + IN COMPHY_MUX_DATA *MuxData, + IN COMPHY_MAP *ComPhyMapData, + IN UINTN ComPhyMaxLanes, + IN EFI_PHYSICAL_ADDRESS SelectorBase, + IN UINT32 BitCount + ) +{ + UINT32 Lane, Value, Offset, Mask; + + for (Lane = 0; Lane < ComPhyMaxLanes; Lane++, ComPhyMapData++, MuxData++) { + Offset = Lane * BitCount; + Mask = (((1 << BitCount) - 1) << Offset); + Value = (ComPhyMuxGetMuxValue (MuxData, ComPhyMapData->Type, Lane) << + Offset); + RegSet (SelectorBase, Value, Mask); + } +} + +VOID +ComPhyMuxInit ( + IN CHIP_COMPHY_CONFIG *PtrChipCfg, + IN COMPHY_MAP *ComPhyMapData, + IN EFI_PHYSICAL_ADDRESS SelectorBase + ) +{ + COMPHY_MUX_DATA *MuxData; + UINT32 MuxBitCount; + UINT32 ComPhyMaxLanes; + + ComPhyMaxLanes = PtrChipCfg->LanesCount; + MuxData = PtrChipCfg->MuxData; + MuxBitCount = PtrChipCfg->MuxBitCount; + + /* Check if the configuration is valid */ + ComPhyMuxCheckConfig (MuxData, ComPhyMapData, ComPhyMaxLanes); + /* Init COMPHY selectors */ + ComPhyMuxRegWrite (MuxData, ComPhyMapData, ComPhyMaxLanes, SelectorBase, + MuxBitCount); +} diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 6df6268..3876249 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -149,6 +149,53 @@ gMarvellTokenSpaceGuid.PcdSataBaseAddress|0|UINT32|0x4000052 gMarvellTokenSpaceGuid.PcdSataMapPortAddress|FALSE|BOOLEAN|0x4000053

+#ComPhy + #Chip0 + gMarvellTokenSpaceGuid.PcdComPhyChipCount|0|UINT32|0x30000098 + + gMarvellTokenSpaceGuid.PcdChip0Compatible|{ 0 }|VOID*|0x30000064 + gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0|UINT64|0x30000065 + gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0|UINT64|0x30000066 + gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|0|UINT32|0x30000067 + gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|0|UINT32|0x30001267 + + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0 }|VOID*|0x30000068 + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0 }|VOID*|0x30000069 + gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0 }|VOID*|0x30000070 + + #Chip1 + gMarvellTokenSpaceGuid.PcdChip1Compatible|{ 0 }|VOID*|0x30000100 + gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress|0|UINT64|0x30000101 + gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress|0|UINT64|0x30000102 + gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount|0|UINT32|0x30000103 + gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes|0|UINT32|0x30001304 + + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0 }|VOID*|0x30000105 + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0 }|VOID*|0x30000106 + gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0 }|VOID*|0x30000107 + + #Chip2 + gMarvellTokenSpaceGuid.PcdChip2Compatible|{ 0 }|VOID*|0x30000135 + gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress|0|UINT64|0x30000136 + gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress|0|UINT64|0x30000137 + gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount|0|UINT32|0x30000138 + gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes|0|UINT32|0x30000139 + + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0 }|VOID*|0x30000140 + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0 }|VOID*|0x30000141 + gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0 }|VOID*|0x30000142 + + #Chip3 + gMarvellTokenSpaceGuid.PcdChip3Compatible|{ 0 }|VOID*|0x30000170 + gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress|0|UINT64|0x30000171 + gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress|0|UINT64|0x30000172 + gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount|0|UINT32|0x30000173 + gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes|0|UINT32|0x30000174 + + gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0 }|VOID*|0x30000175 + gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0 }|VOID*|0x30000176 + gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0 }|VOID*|0x30000177 + [Protocols] gEfiEepromProtocolGuid = { 0xcd728a1f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} gEfiSpiMasterProtocolGuid = { 0x23de66a3, 0xf666, 0x4b3e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }}