The pcie device should be disable for chip's reason before EC and the pcie device should be enable after EC for OS. EC: Engineering change, silicon minor upgrade. Enable all the pcie device, because it is ok for bios.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 33 ++++++++++++++++++---- Platforms/Hisilicon/D05/D05.dsc | 3 +- 2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 8574648..f9b4722 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -19,6 +19,27 @@ //#include "ArmPlatform.h" Scope(_SB) { + /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */ + OperationRegion (ECRA, SystemMemory, 0xD000E014, 0x4) + Field (ECRA, AnyAcc, NoLock, Preserve) + { + VECA, 32, + } + + /* RBYV:Return by chip version + * the pcie device should be disable for chip's reason before EC, + * and the pcie device should be enable after EC for OS */ + Method (RBYV) + { + Store(VECA, local0) + And (local0, 0xFFF00, local1) + If (LEqual (local1, 0x10200)) { + Return (0xf) + } Else { + Return (0x0) + } + } + // 1P NA PCIe2 Device (PCI2) { @@ -147,7 +168,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) }
} // Device(PCI4) @@ -220,7 +241,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI5)
@@ -292,7 +313,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI6) // 1P NB PCIe3 @@ -363,7 +384,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI7) // 2P NA PCIe2 @@ -505,7 +526,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCIc)
@@ -577,7 +598,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCId) } diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 3242b29..1f5e084 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -167,7 +167,8 @@
gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + ## enable all the pcie device, because it is ok for bios + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
## SP805 Watchdog - Motherboard Watchdog