On Sat, Apr 08, 2017 at 06:14:51PM +0100, Ard Biesheuvel wrote:
Update the DTS and ACPI descriptions with correct information about the routing of legacy interrupts.
For DT, this comes down to updating the interrupt-map with distinct sets of 4 GIC interrupt lines per PCIe slot.
For ACPI, we need to update the PNP0A08 node and add three companion devices, one for each slot, whose _PRT methods describe the legacy interrupt routing of each respective slot. The _PRT method at the root of the PCI ACPI hierarchy is updated to map INTA (which is shared by all functions of the bridge device) to GIC interrupt #320. With this change, the boot log is free of warnings and non-MSI capable devices work as expected.
Tested on Cello with xhci_hcd.quirks=64 passed on the kernel command line, in which case the xhci interrupt is routed to GIC interrupt #324
Even if this is not proven to be fully resolved, it certainly seems like an improvement - so: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Ard Biesheuvel (2): Platforms/AMD: correct legacy PCI interrupt routing in DSDT Platforms/AMD: correct legacy PCI interrupt routing in DTS
Platforms/AMD/Styx/AcpiTables/Dsdt.asl | 63 +++++++++++--------- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 7973 -> 8123 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 20 +++++-- 3 files changed, 49 insertions(+), 34 deletions(-)
-- 2.9.3