Re: [Linaro-uefi] [Patch v4 24/56] Platforms/Hisilicon: add D05 platform modules and files

On Tue, Dec 06, 2016 at 07:10:41PM +0800, Heyi Guo wrote:

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diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved.

Umm, I can read this file in the diff. Are you sure it's UCS-2 (or UTF-8)?

I agree this is superior for review, but I don't think it's correct.

Nothing below this line needs addressing for next version.

I check the file using the command ":set fileencoding", it shows fileencoding=utf-8, does that shows the format is utf-8?

Hah, you are correct. I had not seen git format-patch correctly generate utf-8 before. Apologies for the noise.

Regards,

Leif

Thanks and Regards, Heyi

...

Regards,

Leif

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+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/

+/=#

+#langdef en-US "English"

+// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"

+// +// DIMM Device Locator strings

+#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28"

+// +// End English Language Strings +//

diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..149bb7d --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#include <PlatformArch.h> +#include <Uefi.h>

+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h>

+#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2

+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {

•  {67,0,0,0},
  

•  {225,0,0,3},
  

•  {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
  

•  {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
  

+};

+BOOLEAN OemIsSocketPresent (UINTN Socket) +{

• if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
• return TRUE;
• } else {
• return FALSE;
• }

+}

+UINTN OemGetSocketNumber (VOID) +{

• if(!OemIsMpBoot()) {
• return OEM_SINGLE_SOCKET;
• }
• return OEM_DUAL_SOCKET;

+}

+UINTN OemGetDdrChannel (VOID) +{

• return 4;

+}

+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{

• return 2;

+}

+VOID CoreSelectBoot(VOID) +{

• if (!PcdGet64 (PcdTrustedFirmwareEnable)) {

•  StartupAp ();
  

• }
• return;

+}

+BOOLEAN OemIsMpBoot() +{

• return PcdGet32(PcdIsMPBoot);

+}

+VOID OemLpcInit(VOID) +{

• LpcInit();
• return;

+}

+UINT32 OemIsWarmBoot(VOID) +{

• return 0;

+}

+VOID OemBiosSwitch(UINT32 Master) +{

• (VOID)Master;
• return;

+}

+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{

• return TRUE;

+} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/

+[Defines]

• INF_VERSION = 0x00010019
• BASE_NAME = OemMiscLibHi1616Evb
• FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
• MODULE_TYPE = BASE
• VERSION_STRING = 1.0
• LIBRARY_CLASS = OemMiscLib

+[Sources.common]

• BoardFeatureD05.c
• BoardFeatureD05Strings.uni
• OemMiscLibD05.c

+[Packages]

• ArmPkg/ArmPkg.dec
• MdeModulePkg/MdeModulePkg.dec
• MdePkg/MdePkg.dec
• OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec

+[LibraryClasses]

• PcdLib
• TimerLib

+[BuildOptions]

+[Ppis]

• gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES

+[Pcd]

• gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
• gHisiTokenSpaceGuid.PcdIsMPBoot
• gHisiTokenSpaceGuid.PcdSocketMask
• gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable

+[FixedPcd.common]

+[Guids]

+[Protocols]

diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file

• Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
• Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
• This program and the accompanying materials
• are licensed and made available under the terms and conditions of the BSD License
• which accompanies this distribution. The full text of the license may be found at
• http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
• WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+**/

+#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h>

+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},

•                                    {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};
  

+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},

•                                     {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};
  

+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},

•                             {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};
  

+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},

•                       {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};
  

+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {

• {// HostBridge 0
• /* Port 0 */
• {

•  PCI_HB0RB0_ECAM_BASE, //ecam
  

•  0x80,  //BusBase
  

•  0x87, //BusLimit
  

•  PCI_HB0RB0_PCIREGION_BASE, //Membase
  

•  PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
  

•  PCI_HB0RB0_IO_BASE,  //IoBase
  

•  (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB0RB0_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB0RB0_PCI_BASE),//RbPciBar
  

•  PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 1 */
• {

•  PCI_HB0RB1_ECAM_BASE,//ecam
  

•  0x90,  //BusBase
  

•  0x97, //BusLimit
  

•  PCI_HB0RB1_PCIREGION_BASE, //Membase
  

•  PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
  

•  (PCI_HB0RB1_IO_BASE),  //IoBase
  

•  (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
  

•  PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB0RB1_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB0RB1_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 2 */
• {

•  PCI_HB0RB2_ECAM_BASE,
  

•  0x80,  //BusBase
  

•  0x87, //BusLimit
  

•  PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase
  

•  PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
  

•  (PCI_HB0RB2_IO_BASE),  //IOBase
  

•  (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
  

•  PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB0RB2_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB0RB2_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 3 */
• {

•  PCI_HB0RB3_ECAM_BASE,
  

•  0xb0,  //BusBase
  

•  0xb7, //BusLimit
  

•  (PCI_HB0RB3_ECAM_BASE),  //MemBase
  

•  (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit
  

•  (PCI_HB0RB3_IO_BASE), //IoBase
  

•  (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1),  //IoLimit
  

•  PCI_HB0RB3_CPUMEMREGIONBASE,
  

•  PCI_HB0RB3_CPUIOREGIONBASE,
  

•  (PCI_HB0RB3_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 4 */
• {

•  PCI_HB0RB4_ECAM_BASE, //ecam
  

•  0x88,  //BusBase
  

•  0x8f, //BusLimit
  

•  PCI_HB0RB4_CPUMEMREGIONBASE, //Membase
  

•  PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit
  

•  PCI_HB0RB4_IO_BASE,  //IoBase
  

•  (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
  

•  PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB0RB4_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB0RB4_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 5 */
• {

•  PCI_HB0RB5_ECAM_BASE,//ecam
  

•  0x0,  //BusBase
  

•  0x7, //BusLimit
  

•  PCI_HB0RB5_CPUMEMREGIONBASE, //Membase
  

•  PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit
  

•  (PCI_HB0RB5_IO_BASE),  //IoBase
  

•  (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
  

•  PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB0RB5_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB0RB5_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 6 */
• {

•  PCI_HB0RB6_ECAM_BASE,
  

•  0xC0,  //BusBase
  

•  0xC7, //BusLimit
  

•  PCI_HB0RB6_PCIREGION_BASE ,//MemBase
  

•  PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit
  

•  (PCI_HB0RB6_IO_BASE),  //IOBase
  

•  (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
  

•  PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB0RB6_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB0RB6_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 7 */
• {

•  PCI_HB0RB7_ECAM_BASE,
  

•  0x90,  //BusBase
  

•  0x97, //BusLimit
  

•  PCI_HB0RB7_CPUMEMREGIONBASE,  //MemBase
  

•  PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit
  

•  (PCI_HB0RB7_IO_BASE), //IoBase
  

•  (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1),  //IoLimit
  

•  PCI_HB0RB7_CPUMEMREGIONBASE,
  

•  PCI_HB0RB7_CPUIOREGIONBASE,
  

•  (PCI_HB0RB7_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit
  

• }
• },

+{// HostBridge 1

• /* Port 0 */
• {

•  PCI_HB1RB0_ECAM_BASE,
  

•  0x80,  //BusBase
  

•  0x87, //BusLimit
  

•  (PCI_HB1RB0_ECAM_BASE),  //MemBase
  

•  (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit
  

•  PCI_HB1RB0_IO_BASE, //IoBase
  

•  (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB1RB0_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB1RB0_PCI_BASE),  //RbPciBar
  

•  PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 1 */
• {

•  PCI_HB1RB1_ECAM_BASE,
  

•  0x90,  //BusBase
  

•  0x97, //BusLimit
  

•  (PCI_HB1RB1_ECAM_BASE),  //MemBase
  

•  (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit
  

•  PCI_HB1RB1_IO_BASE, //IoBase
  

•  (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB1RB1_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB1RB1_PCI_BASE),  //RbPciBar
  

•  PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 2 */
• {

•  PCI_HB1RB2_ECAM_BASE,
  

•  0x10,  //BusBase
  

•  0x1f, //BusLimit
  

•  PCI_HB1RB2_CPUMEMREGIONBASE,  //MemBase
  

•  PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit
  

•  PCI_HB1RB2_IO_BASE, //IoBase
  

•  (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB1RB2_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB1RB2_PCI_BASE),  //RbPciBar
  

•  PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 3 */
• {

•  PCI_HB1RB3_ECAM_BASE,
  

•  0xb0,  //BusBase
  

•  0xb7, //BusLimit
  

•  (PCI_HB1RB3_ECAM_BASE),  //MemBase
  

•  (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit
  

•  PCI_HB1RB3_IO_BASE, //IoBase
  

•  (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB1RB3_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB1RB3_PCI_BASE),  //RbPciBar
  

•  PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 4 */
• {

•  PCI_HB1RB4_ECAM_BASE,
  

•  0x20,  //BusBase
  

•  0x2f, //BusLimit
  

•  PCI_HB1RB4_CPUMEMREGIONBASE,  //MemBase
  

•  PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit
  

•  PCI_HB1RB4_IO_BASE, //IoBase
  

•  (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB1RB4_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB1RB4_PCI_BASE),  //RbPciBar
  

•  PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 5 */
• {

•  PCI_HB1RB5_ECAM_BASE,
  

•  0x30,  //BusBase
  

•  0x3f, //BusLimit
  

•  PCI_HB1RB5_CPUMEMREGIONBASE,  //MemBase
  

•  PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit
  

•  PCI_HB1RB5_IO_BASE, //IoBase
  

•  (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB1RB5_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB1RB5_PCI_BASE),  //RbPciBar
  

•  PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 6 */
• {

•  PCI_HB1RB6_ECAM_BASE,
  

•  0xa8,  //BusBase
  

•  0xaf, //BusLimit
  

•  (PCI_HB1RB6_ECAM_BASE),  //MemBase
  

•  PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit
  

•  PCI_HB1RB6_IO_BASE, //IoBase
  

•  (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB1RB6_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB1RB6_PCI_BASE),  //RbPciBar
  

•  PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
  

• },
• /* Port 7 */
• {

•  PCI_HB1RB7_ECAM_BASE,
  

•  0xb8,  //BusBase
  

•  0xbf, //BusLimit
  

•  (PCI_HB1RB7_ECAM_BASE),  //MemBase
  

•  PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit
  

•  PCI_HB1RB7_IO_BASE, //IoBase
  

•  (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  

•  PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
  

•  PCI_HB1RB7_CPUIOREGIONBASE,  //CpuIoRegionBase
  

•  (PCI_HB1RB7_PCI_BASE),  //RbPciBar
  

•  PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase
  

•  PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit
  

• }
• }

+};

diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +##

+[Defines]

• INF_VERSION = 0x00010019
• BASE_NAME = PlatformPciLib
• FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
• MODULE_TYPE = BASE
• VERSION_STRING = 1.0

+[Sources]

• PlatformPciLib.c

+[Packages]

• MdePkg/MdePkg.dec
• OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec

+[LibraryClasses]

• PcdLib

+[FixedPcd]

• gHisiTokenSpaceGuid.PcdHb1BaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PciHb0Rb0Base
• gHisiTokenSpaceGuid.PciHb0Rb1Base
• gHisiTokenSpaceGuid.PciHb0Rb2Base
• gHisiTokenSpaceGuid.PciHb0Rb3Base
• gHisiTokenSpaceGuid.PciHb0Rb4Base
• gHisiTokenSpaceGuid.PciHb0Rb5Base
• gHisiTokenSpaceGuid.PciHb0Rb6Base
• gHisiTokenSpaceGuid.PciHb0Rb7Base
• gHisiTokenSpaceGuid.PciHb1Rb0Base
• gHisiTokenSpaceGuid.PciHb1Rb1Base
• gHisiTokenSpaceGuid.PciHb1Rb2Base
• gHisiTokenSpaceGuid.PciHb1Rb3Base
• gHisiTokenSpaceGuid.PciHb1Rb4Base
• gHisiTokenSpaceGuid.PciHb1Rb5Base
• gHisiTokenSpaceGuid.PciHb1Rb6Base
• gHisiTokenSpaceGuid.PciHb1Rb7Base
• gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb7IoSize

-- 1.9.1