Hi Leif and Ard,
There might be another issue in timer interrupt handler. Timer interrupt seems to be level triggered, so is it OK to write EOIR before clearing the interrupt source, i.e. updating compare value register?
Heyi
On 29 July 2016 at 15:11, Ard Biesheuvel ard.biesheuvel@linaro.org wrote:
On 29 July 2016 at 09:09, Ard Biesheuvel ard.biesheuvel@linaro.org wrote:
On 29 July 2016 at 03:23, Heyi Guo heyi.guo@linaro.org wrote:
In timer interrupt handler, we can see the comment that "Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers".
So, if we want to fix this, shall we remove EOIR writing in GIC IRQ
handler
(move it to unregistered interrupt branch only) and keep the one in
timer
interrupt handler, and declare that EOIR should be taken care by each interrupt handler itself, rather than by GIC driver?
Can we use priority drop instead?
Reply to self: probably not. I suppose the whole point is to allow nested timer interrupts.
In any case, we need to get rid of the double EOIR write. I would prefer not to change the contract with existing interrupt handlers, though.