On Mon, Apr 10, 2017 at 05:53:19PM +0200, Marcin Wojtas wrote:
2017-04-10 17:24 GMT+02:00 Leif Lindholm leif.lindholm@linaro.org:
On Fri, Apr 07, 2017 at 05:58:39PM +0200, Marcin Wojtas wrote:
This patch introduces following fixes to the lanes options:
- Remove XAUI, because it's not supported;
- Correct opiton for Lane1 is SATA0;
- Rename KR to SFI;
Why?
According to my information, the kind of SerDes we have now is SFI, KR mode is its subset and will be added later.
Makes sense. Can you add that to commit message?
- Remove SFI from Lane3;
Why?
HW does not support SFI on Lane3, initial assignment was inappropriate. Same as other setting that reside in the initial code.
Makes sense. Can you add that to commit message? :)
- SFI on Lane4 mux selector should be 0x2;
- Align SGMII numbering according to the specification.
The latter change required also an update of ComPhy description in Armda70x0.dsc file.
Because this is such an opaque piece of code, I would normally prefer changing only one thing per patch.
Ok. How about:
- Fix lane assignment.
- Rename to SFI.
- Update .dsc to the newest changes.
?
That would be optimal, thanks.
Regards,
Leif
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Platforms/Marvell/Armada/Armada70x0.dsc | 2 +- Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 30 +++++++++-------------- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 2 +- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 2 +- 4 files changed, 15 insertions(+), 21 deletions(-)
diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 9b7bbb8..5512d61 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -112,7 +112,7 @@ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1"
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2" gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000"
#MDIO
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c index c71ddb6..cee7519 100755 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -49,32 +49,26 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
- and " PIPE Selectors".
- PIPE selector include USB and PCIe options.
- PHY selector include the Ethernet and SATA options, every Ethernet option
- has different options, for example: serdes Lane2 had option Eth_port_0
- that include (SGMII0, XAUI0, RXAUI0, KR)
- has different options, for example: serdes Lane2 have option Eth_port_0
*/
- that include (SGMII0, RXAUI0, SFI)
COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { /* Lane 0 */
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1},
- {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, {PHY_TYPE_SATA1, 0x4}}}, /* Lane 1 */
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1},
- {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, /* Lane 2 */
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1},
- {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1},
- {PHY_TYPE_SATA0, 0x4} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
- {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, /* Lane 3 */
- {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1},
- {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1},
- {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
- {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII1, 0x2},
- {PHY_TYPE_SATA1, 0x4}}}, /* Lane 4 */
- {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2},
- {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1},
- {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } },
- {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAUI0, 0x2},
- {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1},
- {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, {PHY_TYPE_XAUI3, 0x1},
- {PHY_TYPE_SATA1, 0x4} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAUI1, 0x2},
- {PHY_TYPE_SATA1, 0x4}}},
};
COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = { diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c index 9efefb2..88680fc 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -39,7 +39,7 @@ CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"SGMII0", L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2",
L"XAUI3", L"RXAUI0", L"RXAUI1", L"KR"};
L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"};CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps", L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h index 945f266..24839b2 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -109,7 +109,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PHY_TYPE_XAUI3 20 #define PHY_TYPE_RXAUI0 21 #define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_KR 23 +#define PHY_TYPE_SFI 23 #define PHY_TYPE_MAX 24 #define PHY_TYPE_INVALID 0xff
-- 1.8.3.1