Re: [Linaro-uefi] [PATCH v2 8/8] Platforms/Marvell: ComPhyLib: Move devices description to MvHwDescLib

On 14 April 2017 at 22:16, Marcin Wojtas mw@semihalf.com wrote:

This patch introduces ComPhy description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple ComPhy chips and also significantly reduces amount of used PCD's for that purpose. Update PortingGuide documentation accordingly.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com

Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org

---

Documentation/Marvell/PortingGuide/ComPhy.txt | 64 +++------------- Platforms/Marvell/Armada/Armada70x0.dsc | 13 +--- Platforms/Marvell/Include/Library/MvComPhyLib.h | 5 ++ Platforms/Marvell/Include/Library/MvHwDescLib.h | 38 ++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 89 +++++++++++++++-------- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 14 +--- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 26 +------ Platforms/Marvell/Marvell.dec | 28 +------ 8 files changed, 122 insertions(+), 155 deletions(-)

diff --git a/Documentation/Marvell/PortingGuide/ComPhy.txt b/Documentation/Marvell/PortingGuide/ComPhy.txt index b5c4727..a96015e 100644 --- a/Documentation/Marvell/PortingGuide/ComPhy.txt +++ b/Documentation/Marvell/PortingGuide/ComPhy.txt @@ -2,44 +2,18 @@ COMPHY configuration

---

In order to configure ComPhy library, following PCDs are available:

• gMarvellTokenSpaceGuid.PcdComPhyChipCount

• gMarvellTokenSpaceGuid.PcdComPhyDevices

-Indicates how many different chips are placed on board. So far, up to 4 chips -are supported. +This array indicates, which ones of the ComPhy chips defined in +MVHW_COMPHY_DESC template will be configured.

Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not important, but configuration will be set for first PcdComPhyChipCount chips).

-Every chip has 8 ComPhy PCDs and three of them concern lanes settings for this -chip. Below is example for the first chip (Chip0).

-General PCDs:

• gMarvellTokenSpaceGuid.PcdChip0Compatible

-Unicode string indicating type of chip - currently supported is -{ L"Cp110" }

• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress

-Indicates COMPHY unit base address.

• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress

-Indicates Hpipe3 unit base address.

• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount

-Indicates number of bits that are allocated for every MUX in the -COMPHY-selector register.

• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes

-Indicates maximum ComPhy lanes number.

-Next three PCDs are in unicode string format containing settings for up to 10 -lanes. Setting for each one is separated with semicolon. These PCDs form -structure describing outputs of PHY integrated in simple cihp. +Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes +settings for this chip. Their format is unicode string, containing settings +for up to 10 lanes. Setting for each one is separated with semicolon. +These PCDs together describe outputs of PHY integrated in simple cihp. Below is example for the first chip (Chip0).

gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes @@ -48,16 +22,9 @@ Unicode string indicating PHY types. Currently supported are:

{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", -L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", +L"SGMII1", L"SGMII2", L"SGMII3", L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", -L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", -L"RXAUI1", L"KR" }

-Below documents describes some of above interfaces' types:

-SGMII, QSGMII, XAUI - IEEE 802.3 -KR - IEEE 802.3a -RXAUI - RXAUI Interface and RXAUI Adapter Specification, Marvell +L"RXAUI0", L"RXAUI1", L"SFI" }

gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds

@@ -72,14 +39,7 @@ Indicates lane polarity invert. Example

---

#ComPhy

• gMarvellTokenSpaceGuid.PcdComPhyChipCount|1
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6
• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000
• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4
• gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110"
• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
• gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;1250;5000;5000;5000"

• gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1;USB3_HOST1;PCIE2"
• gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;5000"

diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 5512d61..6ea46d7 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -97,13 +97,9 @@ gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18

#ComPhy

• gMarvellTokenSpaceGuid.PcdComPhyChipCount|1
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6
• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000
• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4
• gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110m"

• gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }

• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"

• gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000"

  #UtmiPhy gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2

@@ -112,9 +108,6 @@ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1"

• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
• gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000"
• #MDIO gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200

diff --git a/Platforms/Marvell/Include/Library/MvComPhyLib.h b/Platforms/Marvell/Include/Library/MvComPhyLib.h index 6bd6243..6076ede 100644 --- a/Platforms/Marvell/Include/Library/MvComPhyLib.h +++ b/Platforms/Marvell/Include/Library/MvComPhyLib.h @@ -35,6 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef __MVCOMPHYLIB_H__ #define __MVCOMPHYLIB_H__

+typedef enum {

• MvComPhyTypeCp110,
• MvComPhyTypeMax,

+} MV_COMPHY_CHIP_TYPE;

EFI_STATUS MvComPhyInit ( VOID diff --git a/Platforms/Marvell/Include/Library/MvHwDescLib.h b/Platforms/Marvell/Include/Library/MvHwDescLib.h index 32284a0..ac8dc37 100644 --- a/Platforms/Marvell/Include/Library/MvHwDescLib.h +++ b/Platforms/Marvell/Include/Library/MvHwDescLib.h @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef __MVHWDESCLIB_H__ #define __MVHWDESCLIB_H__

+#include <Library/MvComPhyLib.h> #include <Library/NonDiscoverableDeviceRegistrationLib.h>

// @@ -45,6 +46,20 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index])

// +// CommonPhy devices description template definition +// +#define MVHW_MAX_COMPHY_DEVS 4

+typedef struct {

• UINT8 ComPhyDevCount;
• UINTN ComPhyBaseAddresses[MVHW_MAX_COMPHY_DEVS];
• UINTN ComPhyHpipe3BaseAddresses[MVHW_MAX_COMPHY_DEVS];
• UINTN ComPhyLaneCount[MVHW_MAX_COMPHY_DEVS];
• UINTN ComPhyMuxBitCount[MVHW_MAX_COMPHY_DEVS];
• MV_COMPHY_CHIP_TYPE ComPhyChipType[MVHW_MAX_COMPHY_DEVS];

+} MVHW_COMPHY_DESC;

+// // NonDiscoverable devices description template definition // #define MVHW_MAX_XHCI_DEVS 4 @@ -81,6 +96,29 @@ typedef struct { } MVHW_RTC_DESC;

// +// Platform description of CommonPhy devices +// +#define MVHW_CP0_COMPHY_BASE 0xF2441000 +#define MVHW_CP0_HPIPE3_BASE 0xF2120000 +#define MVHW_CP0_COMPHY_LANES 6 +#define MVHW_CP0_COMPHY_MUX_BITS 4 +#define MVHW_CP1_COMPHY_BASE 0xF4441000 +#define MVHW_CP1_HPIPE3_BASE 0xF4120000 +#define MVHW_CP1_COMPHY_LANES 6 +#define MVHW_CP1_COMPHY_MUX_BITS 4

+#define DECLARE_A7K8K_COMPHY_TEMPLATE \ +STATIC \ +MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate = {\

• 2,\
• { MVHW_CP0_COMPHY_BASE, MVHW_CP1_COMPHY_BASE },\
• { MVHW_CP0_HPIPE3_BASE, MVHW_CP1_HPIPE3_BASE },\
• { MVHW_CP0_COMPHY_LANES, MVHW_CP1_COMPHY_LANES },\
• { MVHW_CP0_COMPHY_MUX_BITS, MVHW_CP1_COMPHY_MUX_BITS },\
• { MvComPhyTypeCp110, MvComPhyTypeCp110 }\

+}

+// // Platform description of NonDiscoverable devices // #define MVHW_CP0_XHCI0_BASE 0xF2500000 diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c index 174f10d..b61ccb6 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -33,6 +33,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/

#include "ComPhyLib.h" +#include <Library/MvComPhyLib.h> +#include <Library/MvHwDescLib.h>

+DECLARE_A7K8K_COMPHY_TEMPLATE;

CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3", @@ -46,14 +50,10 @@ CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps", L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"};

CHIP_COMPHY_CONFIG ChipCfgTbl[] = {

• { /* CP master */
• .ChipType = L"Cp110m",

• {
• .ChipType = MvComPhyTypeCp110, .Init = ComPhyCp110Init },

• { /* CP slave */
• .ChipType = L"Cp110s",
• .Init = ComPhyCp110Init
• }

};

VOID @@ -208,13 +208,12 @@ GetChipComPhyInit ( TblSize = sizeof(ChipCfgTbl) / sizeof(ChipCfgTbl[0]);

for (i = 0; i < TblSize ; i++) {

• if (StrCmp (PtrChipCfg->ChipType, ChipCfgTbl[i].ChipType) == 0) {

• if (PtrChipCfg->ChipType == ChipCfgTbl[i].ChipType) { PtrChipCfg->Init = ChipCfgTbl[i].Init; return EFI_SUCCESS; } }

• DEBUG((DEBUG_ERROR, "ComPhy: Empty ChipType string\n")); return EFI_D_ERROR;

}

@@ -222,18 +221,35 @@ STATIC VOID InitComPhyConfig ( IN OUT CHIP_COMPHY_CONFIG *ChipConfig,

• IN OUT PCD_LANE_MAP *LaneData

• IN OUT PCD_LANE_MAP *LaneData,
• IN UINT8 Id )

{

• MVHW_COMPHY_DESC *Desc = &mA7k8kComPhyDescTemplate;
• ChipConfig->ChipType = Desc->ComPhyChipType[Id];
• ChipConfig->ComPhyBaseAddr = Desc->ComPhyBaseAddresses[Id];
• ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id];
• ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id];
• ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id];
• /*

• • Below macro contains variable name concatenation (used to form PCD's name)
• • and that's why invoking it cannot be automated, e.g. using for loop.
• • Currently up to 4 ComPhys might be configured.

• • Below macro contains variable name concatenation (used to form PCD's name).
  */

• GetComPhyPcd(ChipConfig, LaneData, 0);
• GetComPhyPcd(ChipConfig, LaneData, 1);
• GetComPhyPcd(ChipConfig, LaneData, 2);
• GetComPhyPcd(ChipConfig, LaneData, 3);

• switch (Id) {
• case 0:
• GetComPhyPcd (ChipConfig, LaneData, 0);
• break;
• case 1:
• GetComPhyPcd (ChipConfig, LaneData, 1);
• break;
• case 2:
• GetComPhyPcd (ChipConfig, LaneData, 2);
• break;
• case 3:
• GetComPhyPcd (ChipConfig, LaneData, 3);
• break;
• }

}

EFI_STATUS @@ -242,29 +258,42 @@ MvComPhyInit ( ) { EFI_STATUS Status;

• CHIP_COMPHY_CONFIG ChipConfig[MAX_CHIPS], *PtrChipCfg;
• PCD_LANE_MAP LaneData[MAX_CHIPS];
• UINT32 Lane, ChipCount, i, MaxComphyCount;
• ChipCount = PcdGet32 (PcdComPhyChipCount);
• InitComPhyConfig(ChipConfig, LaneData);

• CHIP_COMPHY_CONFIG ChipConfig[MVHW_MAX_COMPHY_DEVS], *PtrChipCfg;
• PCD_LANE_MAP LaneData[MVHW_MAX_COMPHY_DEVS];
• UINT32 Lane, MaxComphyCount;
• UINT8 *ComPhyDeviceTable, Index;
• /* Obtain table with enabled ComPhy devices */
• ComPhyDeviceTable = (UINT8 *)PcdGetPtr (PcdComPhyDevices);
• if (ComPhyDeviceTable == NULL) {
• DEBUG ((DEBUG_ERROR, "Missing PcdComPhyDevices\n"));
• return EFI_INVALID_PARAMETER;
• }

• if (ChipCount <= 0 || ChipCount > MAX_CHIPS)

• if (PcdGetSize (PcdComPhyDevices) > MVHW_MAX_COMPHY_DEVS) {
• DEBUG ((DEBUG_ERROR, "Wrong PcdComPhyDevices format\n")); return EFI_INVALID_PARAMETER;
• }
• /* Initialize enabled chips */
• for (Index = 0; Index < PcdGetSize (PcdComPhyDevices); Index++) {
• if (!MVHW_DEV_ENABLED (ComPhy, Index)) {

•  DEBUG ((DEBUG_ERROR, "Skip ComPhy chip %d\n", Index));
  

•  continue;
  

• }

• for (i = 0; i < ChipCount ; i++) {
• PtrChipCfg = &ChipConfig[i];

• PtrChipCfg = &ChipConfig[Index];

• InitComPhyConfig(PtrChipCfg, LaneData, Index);

  /* Get the count of the SerDes of the specific chip */ MaxComphyCount = PtrChipCfg->LanesCount; for (Lane = 0; Lane < MaxComphyCount; Lane++) { /* Parse PCD with string indicating SerDes Type */ PtrChipCfg->MapData[Lane].Type =

•    ParseSerdesTypeString (LaneData[i].TypeStr[Lane]);
  

•    ParseSerdesTypeString (LaneData[Index].TypeStr[Lane]);
   PtrChipCfg->MapData[Lane].Speed =
  

•    ParseSerdesSpeed (LaneData[i].SpeedValue[Lane]);
  

•  PtrChipCfg->MapData[Lane].Invert = (UINT32) LaneData[i].InvFlag[Lane];
  

•    ParseSerdesSpeed (LaneData[Index].SpeedValue[Lane]);
  

•  PtrChipCfg->MapData[Lane].Invert = (UINT32)LaneData[Index].InvFlag[Lane];
  
   if ((PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_INVALID) ||
       (PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_ERROR) ||
  

@@ -278,7 +307,7 @@ MvComPhyInit (

 Status = GetChipComPhyInit (PtrChipCfg);
 if (EFI_ERROR(Status)) {

• DEBUG((DEBUG_ERROR, "ComPhy: Invalid Chip%dType name\n", i));
  

• DEBUG ((DEBUG_ERROR, "ComPhy: Invalid Chip%d type\n", Index));
  return Status;
  

  }

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h index 56bb991..3c589f2 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -40,22 +40,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include <Library/DebugLib.h> #include <Library/PcdLib.h> #include <Library/MemoryAllocationLib.h> +#include <Library/MvComPhyLib.h> #include <Library/IoLib.h> #include <Library/TimerLib.h> #include <Library/ParsePcdLib.h>

#define MAX_LANE_OPTIONS 10 -#define MAX_CHIPS 4

/***** Parsing PCD *****/ -#define GET_TYPE_STRING(id) PcdGetPtr(PcdChip##id##Compatible) #define GET_LANE_TYPE(id) PcdGetPtr(PcdChip##id##ComPhyTypes) #define GET_LANE_SPEED(id) PcdGetPtr(PcdChip##id##ComPhySpeeds) #define GET_LANE_INV(id) PcdGetPtr(PcdChip##id##ComPhyInvFlags) -#define GET_COMPHY_BASE_ADDR(id) PcdGet64(PcdChip##id##ComPhyBaseAddress) -#define GET_HPIPE3_BASE_ADDR(id) PcdGet64(PcdChip##id##Hpipe3BaseAddress) -#define GET_MUX_BIT_COUNT(id) PcdGet32(PcdChip##id##ComPhyMuxBitCount) -#define GET_MAX_LANES(id) PcdGet32(PcdChip##id##ComPhyMaxLanes)

#define FillLaneMap(chip_struct, lane_struct, id) { \ ParsePcdString((CHAR16 *) GET_LANE_TYPE(id), chip_struct[id].LanesCount, NULL, lane_struct[id].TypeStr); \ @@ -64,11 +59,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. }

#define GetComPhyPcd(chip_struct, lane_struct, id) { \

• chip_struct[id].ChipType = (CHAR16 *) GET_TYPE_STRING(id); \
• chip_struct[id].ComPhyBaseAddr = GET_COMPHY_BASE_ADDR(id); \
• chip_struct[id].Hpipe3BaseAddr = GET_HPIPE3_BASE_ADDR(id); \
• chip_struct[id].MuxBitCount = GET_MUX_BIT_COUNT(id); \
• chip_struct[id].LanesCount = GET_MAX_LANES(id); \ FillLaneMap(chip_struct, lane_struct, id); \

}

@@ -601,7 +591,7 @@ VOID );

struct _CHIP_COMPHY_CONFIG {

• CHAR16* ChipType;

• MV_COMPHY_CHIP_TYPE ChipType; COMPHY_MAP MapData[MAX_LANE_OPTIONS]; COMPHY_MUX_DATA *MuxData; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr;

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf index 02905a5..ea0b83f 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -59,48 +59,24 @@ ComPhyMux.c

[FixedPcd]

• gMarvellTokenSpaceGuid.PcdComPhyChipCount

• gMarvellTokenSpaceGuid.PcdComPhyDevices

  #Chip0

• gMarvellTokenSpaceGuid.PcdChip0Compatible

• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress

• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress

• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount

• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes

• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags

  #Chip1

• gMarvellTokenSpaceGuid.PcdChip1Compatible

• gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress

• gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress

• gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount

• gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes

• gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags

  #Chip2

• gMarvellTokenSpaceGuid.PcdChip2Compatible

• gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress

• gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress

• gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount

• gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes

• gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags

  #Chip3

• gMarvellTokenSpaceGuid.PcdChip3Compatible

• gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress

• gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress

• gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount

• gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes

• gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags

diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 735a71f..5cbf0c3 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -130,48 +130,24 @@ gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056

#ComPhy

• #Chip0
• gMarvellTokenSpaceGuid.PcdComPhyChipCount|0|UINT32|0x30000098
• gMarvellTokenSpaceGuid.PcdChip0Compatible|{ 0x0 }|VOID*|0x30000064
• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0|UINT64|0x30000065
• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0|UINT64|0x30000066
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|0|UINT32|0x30000067
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|0|UINT32|0x30001267

• gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098

• #Chip0 gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0x0 }|VOID*|0x30000068 gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x0 }|VOID*|0x30000069 gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0x0 }|VOID*|0x30000070

  #Chip1

• gMarvellTokenSpaceGuid.PcdChip1Compatible|{ 0x0 }|VOID*|0x30000100

• gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress|0|UINT64|0x30000101

• gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress|0|UINT64|0x30000102

• gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount|0|UINT32|0x30000103

• gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes|0|UINT32|0x30001304

• gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0x0 }|VOID*|0x30000105 gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0x0 }|VOID*|0x30000106 gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0x0 }|VOID*|0x30000107

  #Chip2

• gMarvellTokenSpaceGuid.PcdChip2Compatible|{ 0x0 }|VOID*|0x30000135

• gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress|0|UINT64|0x30000136

• gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress|0|UINT64|0x30000137

• gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount|0|UINT32|0x30000138

• gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes|0|UINT32|0x30000139

• gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0x0 }|VOID*|0x30000140 gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0x0 }|VOID*|0x30000141 gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0x0 }|VOID*|0x30000142

  #Chip3

• gMarvellTokenSpaceGuid.PcdChip3Compatible|{ 0x0 }|VOID*|0x30000170

• gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress|0|UINT64|0x30000171

• gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress|0|UINT64|0x30000172

• gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount|0|UINT32|0x30000173

• gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes|0|UINT32|0x30000174

• gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0x0 }|VOID*|0x30000175 gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000176 gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177

-- 1.8.3.1