Re: [Linaro-uefi] [PATCH 04/11] Hisilicon/PCIe: Add support for Hi1616

On Thu, Oct 13, 2016 at 10:00:13AM +0800, Heyi Guo wrote:

Hi1616 has 8 root ports for each SOC.

A bit more descriptive commit message please.

Also there appears to be two distinct things happening here: - Increasing support to 8 root ports. - Adding support for Hi1616.

I think these should be two separate patches.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org

---

.../Drivers/PciHostBridgeDxe/PciHostBridge.c | 214 ++++++++++++- .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 2 + .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 9 +- .../Hi1610/Drivers/PcieInit1610/PcieInit.c | 61 +++- .../Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 5 +- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 346 ++++++++++++++++++--- .../Hi1610/Drivers/PcieInit1610/PcieKernelApi.h | 4 +- Chips/Hisilicon/HisiPkg.dec | 114 ++++++- Chips/Hisilicon/Include/Library/PlatformPciLib.h | 136 +++++++- .../D02/Library/PlatformPciLib/PlatformPciLib.c | 32 +- .../D02/Library/PlatformPciLib/PlatformPciLib.inf | 118 ++++++- Platforms/Hisilicon/D03/D03.dsc | 2 +- .../D03/Library/PlatformPciLib/PlatformPciLib.c | 33 +- .../D03/Library/PlatformPciLib/PlatformPciLib.inf | 118 ++++++- 14 files changed, 1093 insertions(+), 101 deletions(-) mode change 100755 => 100644 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c

diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index ccc263e..bf2b928 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -30,12 +30,20 @@ UINT64 RootBridgeAttribute[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE,

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

  }, { //Host Bridge1 EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE,

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

•        EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  

  } };

@@ -136,10 +144,8 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] 0 } }

• }

-}, -{ // Host Bridge1

• /* Port 0 */

• },
• /* Port 4 */ { { {

@@ -235,6 +241,200 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] } } } +}, +{ // Host Bridge1

• /* Port 0 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A0B),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 1 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A0C),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 2 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A0D),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 3 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A0E),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 4 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A0F),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 5 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A10),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 6 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A11),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• },
• /* Port 7 */
• {

•  {
  

•    {
  

•      ACPI_DEVICE_PATH,
  

•      ACPI_DP,
  

•      {
  

•        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  

•        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  

•      }
  

•    },
  

•    EISA_PNP_ID(0x0A12),
  

•    0
  

•  },
  

•  {
  

•    END_DEVICE_PATH_TYPE,
  

•    END_ENTIRE_DEVICE_PATH_SUBTYPE,
  

•    {
  

•      END_DEVICE_PATH_LENGTH,
  

•      0
  

•    }
  

•  }
  

• } }

}; @@ -286,7 +486,7 @@ InitializePciHostBridge ( if (!OemIsMpBoot()) { PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);

• PcieRootBridgeMask &= 0xf;

• PcieRootBridgeMask &= 0xff; } else {

@@ -299,7 +499,7 @@ InitializePciHostBridge ( // for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) {

• if (((PcieRootBridgeMask >> (4 * Loop1)) & 0xF ) == 0) {

• if (((PcieRootBridgeMask >> (8 * Loop1)) & 0xFF ) == 0) {

Since we've had to change this once already, would it be worth setting up some defines rather than hardcoding this number in place?

   continue;
 }

@@ -326,7 +526,7 @@ InitializePciHostBridge ( // Create Root Bridge Device Handle in this Host Bridge // for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {

•  if (!(((PcieRootBridgeMask >> (4 * Loop1)) >> Loop2 ) & 0x01)) {
  

•  if (!(((PcieRootBridgeMask >> (8 * Loop1)) >> Loop2 ) & 0x01)) {
     continue;
   }
  

diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index 99c97cf..cddda6b 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -478,6 +478,8 @@ typedef struct { UINT32 SocType; UINT64 CpuMemRegionBase; UINT64 CpuIoRegionBase;

• UINT64 PciRegionBase;
• UINT64 PciRegionLimit;

EFI_DEVICE_PATH_PROTOCOL *DevicePath; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 01aa1e0..0031f22 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -730,7 +730,8 @@ void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT6 VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private) {

• SetAtuMemRW (Private->RbPciBar, Private->MemBase, Private->MemLimit, Private->CpuMemRegionBase, 0);

• SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0);
• //SetAtuMemRW (Private->RbPciBar, 0xa9000000, 0xafffffff, Private->CpuMemRegionBase, 0);

Drop the commented-out line.

SetAtuConfig0RW (Private, 1); SetAtuConfig1RW (Private, 2); SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3); @@ -741,7 +742,7 @@ BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port) { UINT32 Value = 0;

• if (0x1610 == SocType)

• if ((0x1610 == SocType) || (0x1616 == SocType)) { Value = MmioRead32(RbPciBar + 0x131C); if ((Value & 0x3F) == 0x11)

@@ -800,6 +801,8 @@ RootBridgeConstructor ( PrivateData->Ecam = ResAppeture->Ecam; PrivateData->CpuMemRegionBase = ResAppeture->CpuMemRegionBase; PrivateData->CpuIoRegionBase = ResAppeture->CpuIoRegionBase;

• PrivateData->PciRegionBase = ResAppeture->PciRegionBase;
• PrivateData->PciRegionLimit = ResAppeture->PciRegionLimit;

// // Bus Appeture for this Root Bridge (Possible Range) @@ -1058,7 +1061,7 @@ RootBridgeIoMemRW ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); /* Address is bus resource */

• Address -= PrivateData->MemBase;

• Address -= PrivateData->PciRegionBase; Address += PrivateData->CpuMemRegionBase;

PCIE_DEBUG("RootBridgeIoMemRW Address:0x%llx\n", Address); diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c index 284fa3f..f9674e1 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c @@ -69,6 +69,46 @@ PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] = }, },

• //Port 4
• {

•    0x4,                        //Portindex
  

•    {
  

•        PCIE_ROOT_COMPLEX,      //PortType
  

•        PCIE_WITDH_X8,          //PortWidth
  

•        PCIE_GEN3_0,            //PortGen
  

•    },
  

• },
• //Port 5
• {

•    0x5,                        //Portindex
  

•    {
  

•        PCIE_ROOT_COMPLEX,      //PortType
  

•        PCIE_WITDH_X8,          //PortWidth
  

•        PCIE_GEN3_0,            //PortGen
  

•    },
  

• },
• //Port 6
• {

•    0x6,                        //Portindex
  

•    {
  

•        PCIE_ROOT_COMPLEX,      //PortType
  

•        PCIE_WITDH_X8,          //PortWidth
  

•        PCIE_GEN3_0,            //PortGen
  

•    },
  

• },
• //Port 7
• {

•    0x7,                        //Portindex
  

•    {
  

•        PCIE_ROOT_COMPLEX,      //PortType
  

•        PCIE_WITDH_X8,          //PortWidth
  

•        PCIE_GEN3_0,            //PortGen
  

•    },
  

• },

}; EFI_STATUS @@ -84,25 +124,36 @@ PcieInitEntry ( UINT32 soctype = 0; UINT32 PcieRootBridgeMask;

• soctype = PcdGet32(Pcdsoctype); if (!OemIsMpBoot()) { PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);

OK, so here is something I should have spotted when this code went in, but: Why are we reading a mask from a Pcd only to then trim it down by a hard-coded constant?

•    PcieRootBridgeMask &= 0xf;
  

•    if (0x1610 == soctype)
  

•        PcieRootBridgeMask &= 0xf;
  

•    else PcieRootBridgeMask &= 0xff;
  

That 'else' should be on a line of its own.

 }
 else
 {
     PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
 }

• soctype = PcdGet32(Pcdsoctype); for (HostBridgeNum = 0; HostBridgeNum < PCIE_HOST_BRIDGE_NUM; HostBridgeNum++) { for (Port = 0; Port < PCIE_MAX_PORT_NUM; Port++) {

•        if (!(((( PcieRootBridgeMask >> (4 * HostBridgeNum))) >> Port) & 0x1))
  

•        if (0x1610 == soctype)
  

Revers the comparison, please.

•        {
  

•            if (!(((( PcieRootBridgeMask >> (4 * HostBridgeNum))) >> Port) & 0x1))
  

And as we're modifying this code to begin with, can we turn this a little bit more readable with a few macros?

•            {
  

•                continue;
  

•            }
  

•        }
  

•        else
         {
  

•            continue;
  

•            if (!(((( PcieRootBridgeMask >> (8 * HostBridgeNum))) >> Port) & 0x1))
  

Same here.

•            {
  

•                continue;
  

•            }
         }
  

Status = PciePortInit(soctype, HostBridgeNum, &gastr_pcie_driver_cfg[Port]); diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 63d8bb1..61a5049 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -51,7 +51,10 @@ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P gHisiTokenSpaceGuid.Pcdsoctype

• gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress

• gArmTokenSpaceGuid.PcdGicDistributorBase

This change appears functionally unrelated to the stated purpose of the patch. Even if it is a prerequisite, it should be broken out as a separate commit.

+[FeaturePcd]

• gHisiTokenSpaceGuid.PcdIsItsSupported

And the same goes for this one.

[depex] TRUE diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c old mode 100755 new mode 100644 index a8dd9df..0257109 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -23,14 +23,24 @@ static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; -UINT64 pcie_subctrl_base_1610[2] = {0xa0000000, 0xb0000000}; +UINT64 pcie_subctrl_base_1610[2][8] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000},

Again, can we have a #define each for that 2 and that 8?

•                                    {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000,}};
  

+UINT64 pcie_subctrl_base_1616[2][8] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},

•                                    {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000,}};
  

UINT64 io_sub0_base = 0xa0000000; UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000}; #define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000)) UINT64 PCIE_APB_SLVAE_BASE_1610[2][4] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000}, {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}}; +UINT64 PCIE_APB_SLVAE_BASE_1616[2][8] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},

•                                     {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000},};
  

UINT64 PCIE_PHY_BASE_1610[2][4] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000}, {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}}; +UINT64 PCIE_PHY_BASE_1616[2][8] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},

•                                {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};
  

+UINT64 PCIE_ITS_1610 = 0xc6010040; +UINT64 PCIE_ITS_1616[2][8] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},

•                          {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};
  

UINT32 loop_test_flag[4] = {0,0,0,0}; UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR; #define PcieMaxLanNum 8 @@ -149,6 +159,45 @@ VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN } } }

• else if (0x1616 == soctype)

Flip comparison.

• {

•    if (On) {
  

•        /*
  

•        * to valid the RX, firstly, we should check and make
  

•        * sure the RX lanes have been steadily locked.
  

•        */
  

•        for (Loopcnt = 500 * Lanenum; Loopcnt > 0; Loopcnt--) {
  

Can we have a #define for that 500?

•            Laneid = Loopcnt % Lanenum;
  

•            RegRead(PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0xf4 + Laneid * 0x4, Value);
  

•            if (((Value >> 21) & 0x7) >= 4)
  

And that 0xf4, 0x4, 21, 0x7 and 4?

•                Lockedcnt[Laneid]++;
  

•            else
  

•                Lockedcnt[Laneid] = 0;
  

•            /*
  

•            * If we get a locked status above 8 times incessantly
  

•            * on anyone of the lanes, we get a stable lock.
  

If I'm reading this correctly, I think 'consistently' would be a more correct word that 'incessantly'.

•            */
  

•            if (Lockedcnt[Laneid] >= 8)
  

•                break;
  

•            if (Laneid == (Lanenum - 1))
  

This bit deserves its own comment. (Why are we stopping here?)

•                MicroSecondDelay(500);
  

•            }
  

•        if (Loopcnt == 0)
  

•            DEBUG((EFI_D_ERROR, "pcs locked timeout!\n"));
  

•        for (i = 0; i < Lanenum; i++) {
  

•            RegRead(PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
  

•            Value &= (~BIT14);
  

#defines for 0x204 and 0x4 please. What effect are we hoping to achieve by clearing BIT14?

•            RegWrite(PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
  

Also, spaces between 'i', '*' and '0x4'.

•            }
  

•        } else {
  

OK, I was not going to complain about this, but the placement of '}', 'else' and '{' needs to be consistent at least within the same patch. And the correct format is '} else {'. Please address throughout.

•        for (i = 0; i < Lanenum; i++) {
  

•            RegRead(PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
  

•            Value |= BIT14;
  

•            Value &= (~BIT15);
  

And here by setting BIT14 and clearung BIT15?

•            RegWrite(PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
  

•       }
  

•    }
  

• }

} EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) @@ -169,6 +218,14 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);

The return value of this function is VOID - why is it being cast to VOID? I noticed this in other locations too - please address throughout.

     return EFI_SUCCESS;
 }

• else if (0x1616 == soctype)

Please flip comparison.

• {

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1114, Value);
  

#define for 0x1114, please.

•    Value |= BIT11|BIT30|BIT31;
  

What are we doing by setting these bits?

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1114, Value);
  

•    (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
  

What does the 1 mean?

•    return EFI_SUCCESS;
  

• } else { PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);

@@ -219,6 +276,31 @@ EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) Value |= (BIT28 | BIT30); RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL19_REG, Value); }

• else if (0x1616 == soctype)

Please flip this comparison.

• {

•    //PCIe_SYS_CTRL13
  

Pointless comment, as above.

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL13_REG, Value);
  

#define for that 0x1000.

•    Value |= (BIT13 | BIT12);
  

•    Value |= BIT10;
  

What do these bitops do?

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL13_REG, Value);
  

•    //PCIe_SYS_CTRL6
  

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + PCIE_CTRL_6_REG, Value);
  

•    Value |= (BIT13 | BIT12);
  

•    Value |= (BIT17 | BIT19 | BIT21 | BIT23 | BIT25 | BIT27 | BIT29);
  

What do these bitops do? (Same applies below.)

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + PCIE_CTRL_6_REG, Value);
  

•    //PCIe_SYS_CTRL54
  

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL54_REG, Value);
  

•    Value &= ~(BIT30);
  

•    Value &= ~(0xff<<16);
  

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL54_REG, Value);
  

•    //PCIe_SYS_CTRL19
  

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL19_REG, Value);
  

•    Value |= (BIT28 | BIT30);
  

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL19_REG, Value);
  

• } else { PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);

@@ -267,6 +349,14 @@ EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1); return EFI_SUCCESS; }

• else if (0x1616 == soctype)

Flip comparison.

• {

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1114, Value);
  

•    Value &= ~(BIT11);
  

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1114, Value);
  

•    PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
  

•    return EFI_SUCCESS;
  

• } else { PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);

@@ -467,6 +557,10 @@ EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_P { RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28); }

• else if (0x1616 == soctype)

Flip comparison.

• {

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28);
  

• } else { PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);

@@ -493,12 +587,26 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) UINT32 Value = 0; if (0x1610 == soctype) {

•    RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
  

•    Value |= (1 << 20);
  

•    RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
  

•    for (i = 0; i < 8; i++)
  

•    {
  

•        RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
  

#define for that 0x204 Spaces around '*'.

•        Value |= (1 << 20);
  

•        RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
  

•    }
     PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
     RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
  

  }
• else if (0x1616 == soctype)
• {

•    for (i = 0; i < 8; i++)
  

•    {
  

•        RegRead(PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
  

•        Value |= (1 << 20);
  

•        RegWrite(PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
  

Spaces around '*'.

•    }
  

•    PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
  

What is 0?

•    RegWrite(PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0x264, 0x3D090);
  

#define for 0x264, 0x3d090.

• } else { if(Port<=2)

@@ -586,6 +694,18 @@ VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value); }

• else if (0x1616 == soctype)

Flip comparison. Move else to line above, and the { onto the same line.

• {

•    PcieRegWrite(Port, 0x164, 0x44444444);
  

•    PcieRegWrite(Port, 0x168, 0x44444444);
  

•    PcieRegWrite(Port, 0x16c, 0x44444444);
  

•    PcieRegWrite(Port, 0x170, 0x44444444);
  

#define for all values in block above, please.

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
  

•    Value &= (~0x3f);
  

•    Value |= 0x5;
  

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
  

And for 0x2d0. What do these bitops do?

• } else { Value = PcieRegRead(Port, 0x80);

@@ -618,21 +738,20 @@ EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0; mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0; ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));

• if(Port <= 2)

• if (Port == 3 || Port == 7)

A comment on why 3 and 7 are special?

 {

•    RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
  

•    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
  

Missing space before 0x1. What effect does this operation have?

     MicroSecondDelay(0x1000);

Why is the delay specified in hexadecimal? What is the delay for?

Above comments repeated 3x below.

•    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
  

•    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
     MicroSecondDelay(0x1000);
  

  } else {

•    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
  

•    RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * (Port % 4)), 0x1);
     MicroSecondDelay(0x1000);
  

•    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
  

•    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * (Port % 4)), 0x1);
     MicroSecondDelay(0x1000);
  

  } return EFI_SUCCESS;

@@ -654,12 +773,25 @@ EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port { if(Port <= 2) {

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x3);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x3);
  

•        MicroSecondDelay(0x1000);
  

•    }
  

•    else
  

•    {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
  

•        MicroSecondDelay(0x1000);
  

•    }
  

• }
• else if (0x1616 == soctype)

Flip comparison.

• {

•    if (Port == 3 || Port == 7)
  

•    {
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
         MicroSecondDelay(0x1000);
     }
     else
     {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * (Port%4)), 0x3);
  

Spaces around that '%'.

         MicroSecondDelay(0x1000);
     }
 }

@@ -694,14 +826,28 @@ EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Po if (0x1610 == soctype) {

•    if(Port <= 2)
     {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x3);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x3);
  

What does 0x3 mean? #define?

•        MicroSecondDelay(0x1000);
  

•    }
  

•    else
  

•    {
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x3);
  

Space after ','.

•        MicroSecondDelay(0x1000);
  

•    }
  

• }
• else if (0x1616 == soctype)

Flip comparison. "else if" on same line as } {

• {

•    if (Port == 3 || Port == 7)
  

What's special about ports 3 and 7? Add comment, please.

•    {
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x3);
  

Space after ','.

         MicroSecondDelay(0x1000);
     }
     else
     {

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x3);
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * (Port%4)), 0x3);
  

Spaces around '%'.

         MicroSecondDelay(0x1000);
     }
 }

@@ -727,16 +873,31 @@ EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) u_sc_pcie_hilink_pcs_reset_req reset_req; if (0x1610 == soctype) {

•    if(Port <= 3)
  

•    if(Port <= 7)
  

Comment, please.

     {
         reset_req.UInt32 = 0;

•        reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
  

•        reset_req.UInt32 = reset_req.UInt32 | (0x1 << (Port%4));
  

Spaces around '%'.

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
  

reset_req.UInt32 = 0;

•        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
  

•        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * (Port%4)));
  

Spaces around '%'.

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
  

•        MicroSecondDelay(0x1000);
  

•    }
  

• }
• else if (0x1616 == soctype)

Flip comparison.

• {

•    if(Port <= 7)
  

Comment, please. I will stop pointing it out, but please address throughout.

•    {
  

•        reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0x1 << (Port%4));
  

Spaces around '%'. I won't keep pointing it out, but please address throughout. (And a descriptive #define for that 4 would be nice.)

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
  

•        reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * (Port%4)));
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
         MicroSecondDelay(0x1000);
     }
  

  }

@@ -762,16 +923,31 @@ EFI_STATUS DeassertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Por u_sc_pcie_hilink_pcs_reset_req reset_req; if (0x1610 == soctype) {

•    if(Port <= 3)
  

•    if(Port <= 7)
     {
         reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + 0xacc, reset_req.UInt32);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
  

•        reset_req.UInt32 = reset_req.UInt32 | (0x1 << (Port%4));
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
  

reset_req.UInt32 = 0;

•        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
  

•        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * (Port%4)));
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
  

•        MicroSecondDelay(0x1000);
  

•    }
  

• }
• else if (0x1616 == soctype)
• {

•    if(Port <= 7)
  

•    {
  

•        reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0x1 << (Port%4));
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + 0xacc, reset_req.UInt32);
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
  

•        reset_req.UInt32 = 0;
  

•        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * (Port%4)));
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
         MicroSecondDelay(0x1000);
     }
  

  }

@@ -798,20 +974,27 @@ EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT32 reg_clock_disable; UINT32 reg_clock_enable;

• if (Port == 3) {

• if (Port == 3 || Port == 7) { reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG; reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG; } else {

•    reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port);
  

•    reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port);
  

•    reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port%4);
  

•    reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port%4);
  

  }

if (0x1610 == soctype) { if (Clock)

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + reg_clock_enable, 0x7);
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_enable, 0x7);
  

•    else
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_disable, 0x7);
  

#define for 0x7.

• }
• else if (0x1616 == soctype)

Flip comparison. "else if" with } { (I'll stop addressing these too explicitly, but please address throughout.)

• {

•    if (Clock)
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + reg_clock_enable, 0x7);
     else
  

•        RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + reg_clock_disable, 0x7);
  

•        RegWrite(pcie_subctrl_base_1616[HostBridgeNum][Port] + reg_clock_disable, 0x7);
  

  } else {

@@ -833,6 +1016,14 @@ VOID PciePortNumSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Num Value |= Num; RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value); }

• else if (0x1616 == soctype)
• {

•    UINT32 Value = 0;
  

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
  

•    Value &= ~(0xff);
  

•    Value |= Num;
  

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
  

And I'll stop pointing out that I would like #defines for all magic values too...

• } return;

} @@ -845,6 +1036,12 @@ VOID PcieLaneReversalSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) Value |= BIT16; RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value); }

• else if (0x1616 == soctype)
• {

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
  

•    Value |= BIT16;
  

And all bitops. (Or at leats descriptive comments.)

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
  

• } return;

} EFI_STATUS PcieMaskLinkUpInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) @@ -856,6 +1053,12 @@ EFI_STATUS PcieMaskLinkUpInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) Value |= 1 << 25; PcieRegWrite(Port,0x120, Value); }

• else if (0x1616 == soctype)
• {

•    Value = PcieRegRead(Port, 0x120);
  

•    Value |= 1 << 25;
  

•    PcieRegWrite(Port,0x120, Value);
  

• } else { PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);

@@ -879,6 +1082,14 @@ BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) return TRUE; return FALSE; }

• else if (0x1616 == soctype)
• {

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32);
  

•    Value = PcieStat.UInt32;
  

•    if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
  

•        return TRUE;
  

•    return FALSE;
  

• } else { RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);

@@ -897,6 +1108,11 @@ BOOLEAN PcieClockIsLock(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead( PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x504, Value); return ((Value & 0x3) == 0x3); }

• else if (0x1616 == soctype)
• {

•    RegRead( PCIE_PHY_BASE_1616[HostBridgeNum][Port] + 0x504, Value);
  

•    return ((Value & 0x3) == 0x3);
  

• } else return TRUE;

} @@ -912,12 +1128,21 @@ VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd) RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value); return; }

• else if (0x1616 == soctype)
• {

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0xa0, Value);
  

•    Value &= ~(0xf);
  

•    Value |= Spd;
  

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0xa0, Value);
  

•    return;
  

• } return;

} -VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 Data) +VOID PcieWriteOwnConfig(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 Data) { UINT32 Value = 0;

• if (0x1610 == soctype)
  {
      RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
      Value &= 0x0000ffff;
  

@@ -925,18 +1150,51 @@ VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value); return; }

• else if (0x1616 == soctype)
  

• {
  

•     RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
  

•     Value &= 0x0000ffff;
  

•     Value |= 0x06040000;
  

•     RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
  

•     return;
  

• }
  

} void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 Value = 0;

• RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdPcieMsiTargetAddress));
• RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c4, 0);
• RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
• Value |= (1 << 12);
• RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);

• if (0x1610 == soctype)
• {

•    if (FeaturePcdGet (PcdIsItsSupported))
  

•    {
  

•        RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PCIE_ITS_1610);
  

•        RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c4, PCIE_ITS_1610 >> 32);
  

•    }
  

•    else
  

•    {
  

•        RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdGicDistributorBase) + 0x40);
  

•        RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c4, (PcdGet64 (PcdGicDistributorBase) + 0x40) >> 32);
  

•    }
  

•    RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
  

•    Value |= (1 << 12);
  

•    RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
  

• }
• else if (0x1616 == soctype)
• {

•    if (FeaturePcdGet (PcdIsItsSupported))
  

•    {
  

•        RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x11b4, PCIE_ITS_1616[HostBridgeNum][Port]);
  

•        RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x11c4, (PCIE_ITS_1616[HostBridgeNum][Port] >> 32));
  

•    }
  

•    else
  

•    {
  

•        RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdGicDistributorBase) + 0x40);
  

•        RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x11c4, (PcdGet64 (PcdGicDistributorBase) + 0x40) >> 32);
  

•    }
  

•    RegRead(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x11c8, Value);
  

•    Value |= (1 << 12);
  

•    RegWrite(PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][Port] + 0x11c8, Value);
  

• } return;

} @@ -961,6 +1219,11 @@ PciePortInit ( mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][PortIndex]; DEBUG((EFI_D_INFO, "Soc type is 1610\n")); }

• else if (0x1616 == soctype)
  

• {
  

•     mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLVAE_BASE_1616[HostBridgeNum][PortIndex];
  

•     DEBUG((EFI_D_INFO, "Soc type is 1616\n"));
  

• }
  else
  {
      mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
  

@@ -1003,7 +1266,8 @@ PciePortInit ( /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex);

• (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex);
  

• if (0x1610 == soctype)
  

•     (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex);
  

PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); /* @@ -1013,7 +1277,7 @@ PciePortInit ( * in RC mode. Here we just disable it */ PcieRegWrite(PortIndex, 0x10, 0);

• (VOID)PcieWriteOwnConfig(HostBridgeNum, PortIndex, 0xa, 0x0604);
  

• (VOID)PcieWriteOwnConfig(soctype, HostBridgeNum, PortIndex, 0xa, 0x0604);
  

I don't think 'soctype' benefits from being added to the API. It can be easily extracted in the callee, with reduced stack overhead.

  /* check if the link is up or not */
  while (!PcieIsLinkUp(soctype, HostBridgeNum, PortIndex)) {
      MicroSecondDelay(1000);

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h index d1ba1c8..0e63521 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h @@ -16,8 +16,8 @@ #ifndef __PCIE_KERNEL_API_H__ #define __PCIE_KERNEL_API_H__ -#define PCIE_HOST_BRIDGE_NUM (1) -#define PCIE_MAX_PORT_NUM (4) +#define PCIE_HOST_BRIDGE_NUM (2) +#define PCIE_MAX_PORT_NUM (8)

Oh, so we already have these defines, they are just not being used? Please address.

#define PCIE_MAX_OUTBOUND (6) #define PCIE_MAX_INBOUND (4) #define PCIE3_MAX_OUTBOUND (16) diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 8e46e0d..b76cd72 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -121,46 +121,156 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0|UINT64|0x00000057 gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000058 gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0|UINT64|0x00000059

• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000152
• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0|UINT64|0x00000153
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000154
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0|UINT64|0x00000155
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000156
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0|UINT64|0x00000157
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000158
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0|UINT64|0x00000159
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0|UINT64|0x00000252
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0|UINT64|0x00000253
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0|UINT64|0x00000254
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0|UINT64|0x00000255
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0|UINT64|0x00000256
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0|UINT64|0x00000257
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000258
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0|UINT64|0x00000259
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000352
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0|UINT64|0x00000353
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000354
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0|UINT64|0x00000355
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000356
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0|UINT64|0x00000357
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000358
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0|UINT64|0x00000359

gHisiTokenSpaceGuid.PciHb0Rb0Base|0|UINT64|0x0000005a gHisiTokenSpaceGuid.PciHb0Rb1Base|0|UINT64|0x0000005b gHisiTokenSpaceGuid.PciHb0Rb2Base|0|UINT64|0x0000005c gHisiTokenSpaceGuid.PciHb0Rb3Base|0|UINT64|0x0000005d

• gHisiTokenSpaceGuid.PciHb0Rb4Base|0|UINT64|0x0100005a
• gHisiTokenSpaceGuid.PciHb0Rb5Base|0|UINT64|0x0100005b
• gHisiTokenSpaceGuid.PciHb0Rb6Base|0|UINT64|0x0100005c
• gHisiTokenSpaceGuid.PciHb0Rb7Base|0|UINT64|0x0100005d
• gHisiTokenSpaceGuid.PciHb1Rb0Base|0|UINT64|0x0200005a
• gHisiTokenSpaceGuid.PciHb1Rb1Base|0|UINT64|0x0200005b
• gHisiTokenSpaceGuid.PciHb1Rb2Base|0|UINT64|0x0200005c
• gHisiTokenSpaceGuid.PciHb1Rb3Base|0|UINT64|0x0200005d
• gHisiTokenSpaceGuid.PciHb1Rb4Base|0|UINT64|0x0300005a
• gHisiTokenSpaceGuid.PciHb1Rb5Base|0|UINT64|0x0300005b
• gHisiTokenSpaceGuid.PciHb1Rb6Base|0|UINT64|0x0300005c
• gHisiTokenSpaceGuid.PciHb1Rb7Base|0|UINT64|0x0300005d
• gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0|UINT64|0x8000005a gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0|UINT64|0x8000005b gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0|UINT64|0x8000005c gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0|UINT64|0x8000005d
• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0|UINT64|0x8000005e
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0|UINT64|0x8000005f
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0|UINT64|0x80000060
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0|UINT64|0x80000061
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0|UINT64|0x80000062
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0|UINT64|0x80000063
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0|UINT64|0x80000064
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0|UINT64|0x80000065
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0|UINT64|0x80000066
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0|UINT64|0x80000067
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0|UINT64|0x80000068
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0|UINT64|0x80000069

gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0|UINT64|0x6000005a gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0|UINT64|0x6000005b gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0|UINT64|0x6000005c gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0|UINT64|0x6000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0|UINT64|0x6000005e
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0|UINT64|0x6000005f
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0|UINT64|0x60000060
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0|UINT64|0x60000061
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0|UINT64|0x60000062
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0|UINT64|0x60000063
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0|UINT64|0x60000064
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0|UINT64|0x60000065
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0|UINT64|0x60000066
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0|UINT64|0x60000067
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0|UINT64|0x60000068
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0|UINT64|0x60000069

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0|UINT64|0x7000005a gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0|UINT64|0x7000005b gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0|UINT64|0x7000005c gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0|UINT64|0x7000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0|UINT64|0x7000005e
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0|UINT64|0x7000005f
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0|UINT64|0x70000060
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0|UINT64|0x70000061
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0|UINT64|0x70000062
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0|UINT64|0x70000063
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0|UINT64|0x70000064
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0|UINT64|0x70000065
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0|UINT64|0x70000066
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0|UINT64|0x70000067
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0|UINT64|0x70000068
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0|UINT64|0x70000069

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0|UINT64|0x3000005a gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0|UINT64|0x3000005b gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0|UINT64|0x3000005c

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0|UINT64|0x3000005d

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0|UINT64|0x3000005e

Why this change? Duff merge fixup?

• gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0|UINT64|0x3000005f
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0|UINT64|0x30000070
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0|UINT64|0x30000061
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0|UINT64|0x30000062
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0|UINT64|0x30000063
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0|UINT64|0x30000064
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0|UINT64|0x30000065
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0|UINT64|0x30000066
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0|UINT64|0x30000067
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0|UINT64|0x30000068
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0|UINT64|0x30000069
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0|UINT64|0x3000006a

gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0|UINT64|0x9000005a gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0|UINT64|0x9000005b gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0|UINT64|0x9000005c gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0|UINT64|0x9000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0|UINT64|0x9100005a
• gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0|UINT64|0x9100005b
• gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0|UINT64|0x9100005c
• gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0|UINT64|0x9100005d
• gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0|UINT64|0x9010005a
• gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0|UINT64|0x9010005b
• gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0|UINT64|0x9010005c
• gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0|UINT64|0x9010005d
• gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0|UINT64|0x9110005a
• gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0|UINT64|0x9110005b
• gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0|UINT64|0x9110005c
• gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0|UINT64|0x9110005d

gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0|UINT64|0x2000005a gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0|UINT64|0x2000005b gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0|UINT64|0x2000005c gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0|UINT64|0x2000005d

• gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0|UINT64|0x2100005a
• gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0|UINT64|0x2100005b
• gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0|UINT64|0x2100005c
• gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0|UINT64|0x2100005d
• gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0|UINT64|0x2010005a
• gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0|UINT64|0x2010005b
• gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0|UINT64|0x2010005c
• gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0|UINT64|0x2010005d
• gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0|UINT64|0x2110005a
• gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0|UINT64|0x2110005b
• gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0|UINT64|0x2110005c
• gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d

gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061

• gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064 gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056

[PcdsFeatureFlag]

• gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065

diff --git a/Chips/Hisilicon/Include/Library/PlatformPciLib.h b/Chips/Hisilicon/Include/Library/PlatformPciLib.h index 72d2d21..f478ef8 100644 --- a/Chips/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformPciLib.h @@ -17,17 +17,25 @@ #define _PLATFORM_PCI_LIB_H_ #define PCIE_MAX_HOSTBRIDGE 2 -#define PCIE_MAX_ROOTBRIDGE 4 +#define PCIE_MAX_ROOTBRIDGE 8

Are these not redefinitions of

+#define PCIE_HOST_BRIDGE_NUM (2) +#define PCIE_MAX_PORT_NUM (8)

?

If so, please try to avoid and use only one set of definitions.

#define PCI_HB0RB0_PCI_BASE FixedPcdGet64(PciHb0Rb0Base) #define PCI_HB0RB1_PCI_BASE FixedPcdGet64(PciHb0Rb1Base) #define PCI_HB0RB2_PCI_BASE FixedPcdGet64(PciHb0Rb2Base) #define PCI_HB0RB3_PCI_BASE FixedPcdGet64(PciHb0Rb3Base) +#define PCI_HB0RB4_PCI_BASE FixedPcdGet64(PciHb0Rb4Base) +#define PCI_HB0RB5_PCI_BASE FixedPcdGet64(PciHb0Rb5Base) +#define PCI_HB0RB6_PCI_BASE FixedPcdGet64(PciHb0Rb6Base) +#define PCI_HB0RB7_PCI_BASE FixedPcdGet64(PciHb0Rb7Base) -#define PCI_HB1RB0_PCI_BASE 0xb0090000 -#define PCI_HB1RB1_PCI_BASE 0xb0200000 -#define PCI_HB1RB2_PCI_BASE 0xb00a0000 -#define PCI_HB1RB3_PCI_BASE 0xb00b0000 +#define PCI_HB1RB0_PCI_BASE FixedPcdGet64(PciHb1Rb0Base) +#define PCI_HB1RB1_PCI_BASE FixedPcdGet64(PciHb1Rb1Base) +#define PCI_HB1RB2_PCI_BASE FixedPcdGet64(PciHb1Rb2Base) +#define PCI_HB1RB3_PCI_BASE FixedPcdGet64(PciHb1Rb3Base) +#define PCI_HB1RB4_PCI_BASE FixedPcdGet64(PciHb1Rb4Base) +#define PCI_HB1RB5_PCI_BASE FixedPcdGet64(PciHb1Rb5Base) +#define PCI_HB1RB6_PCI_BASE FixedPcdGet64(PciHb1Rb6Base) +#define PCI_HB1RB7_PCI_BASE FixedPcdGet64(PciHb1Rb7Base) #define PCI_HB0RB0_ECAM_BASE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceBaseAddress) #define PCI_HB0RB0_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceSize) @@ -37,15 +45,32 @@ #define PCI_HB0RB2_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceSize) #define PCI_HB0RB3_ECAM_BASE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceBaseAddress) #define PCI_HB0RB3_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceSize) +#define PCI_HB0RB4_ECAM_BASE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB4_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceSize) +#define PCI_HB0RB5_ECAM_BASE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB5_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceSize) +#define PCI_HB0RB6_ECAM_BASE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB6_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceSize) +#define PCI_HB0RB7_ECAM_BASE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB7_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceSize)

+#define PCI_HB1RB0_ECAM_BASE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB0_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceSize) +#define PCI_HB1RB1_ECAM_BASE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB1_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceSize) +#define PCI_HB1RB2_ECAM_BASE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB2_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceSize) +#define PCI_HB1RB3_ECAM_BASE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB3_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceSize) +#define PCI_HB1RB4_ECAM_BASE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB4_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceSize) +#define PCI_HB1RB5_ECAM_BASE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB5_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceSize) +#define PCI_HB1RB6_ECAM_BASE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB6_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceSize) +#define PCI_HB1RB7_ECAM_BASE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB7_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceSize) -#define PCI_HB1RB0_ECAM_BASE (FixedPcdGet64 (PcdHb1BaseAddress) + PCI_HB0RB0_ECAM_BASE) -#define PCI_HB1RB0_ECAM_SIZE PCI_HB0RB0_ECAM_SIZE -#define PCI_HB1RB1_ECAM_BASE (FixedPcdGet64 (PcdHb1BaseAddress) + PCI_HB0RB1_ECAM_BASE) -#define PCI_HB1RB1_ECAM_SIZE PCI_HB0RB1_ECAM_SIZE -#define PCI_HB1RB2_ECAM_BASE 0xb8000000 -#define PCI_HB1RB2_ECAM_SIZE 0x4000000 -#define PCI_HB1RB3_ECAM_BASE 0xbc000000 -#define PCI_HB1RB3_ECAM_SIZE 0x4000000 #define PCI_HB0RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb0PciRegionBaseAddress)) #define PCI_HB0RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb0PciRegionSize)) #define PCI_HB0RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb1PciRegionBaseAddress)) @@ -54,26 +79,109 @@ #define PCI_HB0RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb2PciRegionSize)) #define PCI_HB0RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb3PciRegionBaseAddress)) #define PCI_HB0RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb3PciRegionSize)) +#define PCI_HB0RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb4PciRegionBaseAddress)) +#define PCI_HB0RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb4PciRegionSize)) +#define PCI_HB0RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb5PciRegionBaseAddress)) +#define PCI_HB0RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb5PciRegionSize)) +#define PCI_HB0RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb6PciRegionBaseAddress)) +#define PCI_HB0RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb6PciRegionSize)) +#define PCI_HB0RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb7PciRegionBaseAddress)) +#define PCI_HB0RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb7PciRegionSize))

+#define PCI_HB1RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb0PciRegionBaseAddress)) +#define PCI_HB1RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb0PciRegionSize)) +#define PCI_HB1RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb1PciRegionBaseAddress)) +#define PCI_HB1RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb1PciRegionSize)) +#define PCI_HB1RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb2PciRegionBaseAddress)) +#define PCI_HB1RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb2PciRegionSize)) +#define PCI_HB1RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb3PciRegionBaseAddress)) +#define PCI_HB1RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb3PciRegionSize)) +#define PCI_HB1RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb4PciRegionBaseAddress)) +#define PCI_HB1RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb4PciRegionSize)) +#define PCI_HB1RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb5PciRegionBaseAddress)) +#define PCI_HB1RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb5PciRegionSize)) +#define PCI_HB1RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb6PciRegionBaseAddress)) +#define PCI_HB1RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb6PciRegionSize)) +#define PCI_HB1RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb7PciRegionBaseAddress)) +#define PCI_HB1RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb7PciRegionSize))

#define PCI_HB0RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuMemRegionBase)) #define PCI_HB0RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuMemRegionBase)) #define PCI_HB0RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuMemRegionBase)) #define PCI_HB0RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuMemRegionBase)) +#define PCI_HB0RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuMemRegionBase)) +#define PCI_HB0RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuMemRegionBase)) +#define PCI_HB0RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuMemRegionBase)) +#define PCI_HB0RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuMemRegionBase))

+#define PCI_HB1RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuMemRegionBase)) +#define PCI_HB1RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuMemRegionBase)) +#define PCI_HB1RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuMemRegionBase)) +#define PCI_HB1RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuMemRegionBase)) +#define PCI_HB1RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuMemRegionBase)) +#define PCI_HB1RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuMemRegionBase)) +#define PCI_HB1RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuMemRegionBase)) +#define PCI_HB1RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuMemRegionBase))

#define PCI_HB0RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuIoRegionBase)) #define PCI_HB0RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuIoRegionBase)) #define PCI_HB0RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuIoRegionBase)) #define PCI_HB0RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuIoRegionBase)) +#define PCI_HB0RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuIoRegionBase)) +#define PCI_HB0RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuIoRegionBase)) +#define PCI_HB0RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuIoRegionBase)) +#define PCI_HB0RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuIoRegionBase))

+#define PCI_HB1RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuIoRegionBase)) +#define PCI_HB1RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuIoRegionBase)) +#define PCI_HB1RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuIoRegionBase)) +#define PCI_HB1RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuIoRegionBase)) +#define PCI_HB1RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuIoRegionBase)) +#define PCI_HB1RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuIoRegionBase)) +#define PCI_HB1RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuIoRegionBase)) +#define PCI_HB1RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuIoRegionBase))

#define PCI_HB0RB0_IO_BASE (FixedPcdGet64 (PcdHb0Rb0IoBase)) #define PCI_HB0RB1_IO_BASE (FixedPcdGet64 (PcdHb0Rb1IoBase)) #define PCI_HB0RB2_IO_BASE (FixedPcdGet64 (PcdHb0Rb2IoBase)) #define PCI_HB0RB3_IO_BASE (FixedPcdGet64 (PcdHb0Rb3IoBase)) +#define PCI_HB0RB4_IO_BASE (FixedPcdGet64 (PcdHb0Rb4IoBase)) +#define PCI_HB0RB5_IO_BASE (FixedPcdGet64 (PcdHb0Rb5IoBase)) +#define PCI_HB0RB6_IO_BASE (FixedPcdGet64 (PcdHb0Rb6IoBase)) +#define PCI_HB0RB7_IO_BASE (FixedPcdGet64 (PcdHb0Rb7IoBase))

+#define PCI_HB1RB0_IO_BASE (FixedPcdGet64 (PcdHb1Rb0IoBase)) +#define PCI_HB1RB1_IO_BASE (FixedPcdGet64 (PcdHb1Rb1IoBase)) +#define PCI_HB1RB2_IO_BASE (FixedPcdGet64 (PcdHb1Rb2IoBase)) +#define PCI_HB1RB3_IO_BASE (FixedPcdGet64 (PcdHb1Rb3IoBase)) +#define PCI_HB1RB4_IO_BASE (FixedPcdGet64 (PcdHb1Rb4IoBase)) +#define PCI_HB1RB5_IO_BASE (FixedPcdGet64 (PcdHb1Rb5IoBase)) +#define PCI_HB1RB6_IO_BASE (FixedPcdGet64 (PcdHb1Rb6IoBase)) +#define PCI_HB1RB7_IO_BASE (FixedPcdGet64 (PcdHb1Rb7IoBase)) #define PCI_HB0RB0_IO_SIZE (FixedPcdGet64 (PcdHb0Rb0IoSize)) #define PCI_HB0RB1_IO_SIZE (FixedPcdGet64 (PcdHb0Rb1IoSize)) #define PCI_HB0RB2_IO_SIZE (FixedPcdGet64 (PcdHb0Rb2IoSize)) #define PCI_HB0RB3_IO_SIZE (FixedPcdGet64 (PcdHb0Rb3IoSize)) +#define PCI_HB0RB4_IO_SIZE (FixedPcdGet64 (PcdHb0Rb4IoSize)) +#define PCI_HB0RB5_IO_SIZE (FixedPcdGet64 (PcdHb0Rb5IoSize)) +#define PCI_HB0RB6_IO_SIZE (FixedPcdGet64 (PcdHb0Rb6IoSize)) +#define PCI_HB0RB7_IO_SIZE (FixedPcdGet64 (PcdHb0Rb7IoSize))

+#define PCI_HB1RB0_IO_SIZE (FixedPcdGet64 (PcdHb1Rb0IoSize)) +#define PCI_HB1RB1_IO_SIZE (FixedPcdGet64 (PcdHb1Rb1IoSize)) +#define PCI_HB1RB2_IO_SIZE (FixedPcdGet64 (PcdHb1Rb2IoSize)) +#define PCI_HB1RB3_IO_SIZE (FixedPcdGet64 (PcdHb1Rb3IoSize)) +#define PCI_HB1RB4_IO_SIZE (FixedPcdGet64 (PcdHb1Rb4IoSize)) +#define PCI_HB1RB5_IO_SIZE (FixedPcdGet64 (PcdHb1Rb5IoSize)) +#define PCI_HB1RB6_IO_SIZE (FixedPcdGet64 (PcdHb1Rb6IoSize)) +#define PCI_HB1RB7_IO_SIZE (FixedPcdGet64 (PcdHb1Rb7IoSize))

typedef struct { UINT64 Ecam; @@ -86,6 +194,8 @@ typedef struct { UINT64 CpuMemRegionBase; UINT64 CpuIoRegionBase; UINT64 RbPciBar;

• UINT64 PciRegionBase;
• UINT64 PciRegionLimit;

} PCI_ROOT_BRIDGE_RESOURCE_APPETURE; extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c index b487b5f..797163a 100644 --- a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c @@ -29,7 +29,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB0RB0_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB0_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 1 */ {

@@ -42,7 +44,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1, //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, PCI_HB0RB2_CPUIOREGIONBASE,

•  (PCI_HB0RB1_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB1_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB1_PCIREGION_BASE,
  

•  PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1
  

  }, /* Port 2 */ {

@@ -55,7 +59,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1, //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, PCI_HB0RB2_CPUIOREGIONBASE,

•  (PCI_HB0RB2_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB2_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB2_PCIREGION_BASE ,
  

•  PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1
  

  },

/* Port 3 */ @@ -69,7 +75,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB0RB3_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB3_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  } },

{// HostBridge 1 @@ -84,7 +92,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB0_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB0_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 1 */ {

@@ -97,7 +107,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB1_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB1_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 2 */ {

@@ -110,7 +122,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB2_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB2_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  },

/* Port 3 */ @@ -124,7 +138,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB3_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB3_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  } }

}; diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf index 5040a04..fc7df53 100644 --- a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf @@ -40,37 +40,145 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize

• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize gHisiTokenSpaceGuid.PciHb0Rb0Base gHisiTokenSpaceGuid.PciHb0Rb1Base gHisiTokenSpaceGuid.PciHb0Rb2Base gHisiTokenSpaceGuid.PciHb0Rb3Base
• gHisiTokenSpaceGuid.PciHb0Rb4Base
• gHisiTokenSpaceGuid.PciHb0Rb5Base
• gHisiTokenSpaceGuid.PciHb0Rb6Base
• gHisiTokenSpaceGuid.PciHb0Rb7Base
• gHisiTokenSpaceGuid.PciHb1Rb0Base
• gHisiTokenSpaceGuid.PciHb1Rb1Base
• gHisiTokenSpaceGuid.PciHb1Rb2Base
• gHisiTokenSpaceGuid.PciHb1Rb3Base
• gHisiTokenSpaceGuid.PciHb1Rb4Base
• gHisiTokenSpaceGuid.PciHb1Rb5Base
• gHisiTokenSpaceGuid.PciHb1Rb6Base
• gHisiTokenSpaceGuid.PciHb1Rb7Base gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress

gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize

• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb2IoSize gHisiTokenSpaceGuid.PcdHb0Rb0IoBase gHisiTokenSpaceGuid.PcdHb0Rb0IoSize gHisiTokenSpaceGuid.PcdHb0Rb1IoBase gHisiTokenSpaceGuid.PcdHb0Rb1IoSize gHisiTokenSpaceGuid.PcdHb0Rb2IoBase gHisiTokenSpaceGuid.PcdHb0Rb2IoSize

• gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb7IoSize

diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index ccf16a2..6ff92a5 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -111,6 +111,7 @@ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE

• gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE

[PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" @@ -308,7 +309,6 @@ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000

• gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0xc6010040

################################################################################ # diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index 5ce7731..2f7d158 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -29,7 +29,10 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase

•  (PCI_HB0RB0_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB0_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase
  

•  PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit
  

• }, /* Port 1 */ {

@@ -42,7 +45,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase

•  (PCI_HB0RB1_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB1_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase
  

•  PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit
  

  }, /* Port 2 */ {

@@ -55,7 +60,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase

•  (PCI_HB0RB2_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB2_PCI_BASE),  //RbPciBar
  

•  PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase
  

•  PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit
  

  },

/* Port 3 */ @@ -69,7 +76,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB0RB3_PCI_BASE)  //RbPciBar
  

•  (PCI_HB0RB3_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  } },

{// HostBridge 1 @@ -84,7 +93,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB0_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB0_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 1 */ {

@@ -97,7 +108,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB1_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB1_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  }, /* Port 2 */ {

@@ -110,7 +123,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB2_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB2_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  },

/* Port 3 */ @@ -124,7 +139,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0,

•  (PCI_HB1RB3_PCI_BASE)  //RbPciBar
  

•  (PCI_HB1RB3_PCI_BASE),  //RbPciBar
  

•  0,
  

•  0
  

  } }

}; diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf index 5040a04..fc7df53 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf @@ -40,37 +40,145 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize

• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize gHisiTokenSpaceGuid.PciHb0Rb0Base gHisiTokenSpaceGuid.PciHb0Rb1Base gHisiTokenSpaceGuid.PciHb0Rb2Base gHisiTokenSpaceGuid.PciHb0Rb3Base
• gHisiTokenSpaceGuid.PciHb0Rb4Base
• gHisiTokenSpaceGuid.PciHb0Rb5Base
• gHisiTokenSpaceGuid.PciHb0Rb6Base
• gHisiTokenSpaceGuid.PciHb0Rb7Base
• gHisiTokenSpaceGuid.PciHb1Rb0Base
• gHisiTokenSpaceGuid.PciHb1Rb1Base
• gHisiTokenSpaceGuid.PciHb1Rb2Base
• gHisiTokenSpaceGuid.PciHb1Rb3Base
• gHisiTokenSpaceGuid.PciHb1Rb4Base
• gHisiTokenSpaceGuid.PciHb1Rb5Base
• gHisiTokenSpaceGuid.PciHb1Rb6Base
• gHisiTokenSpaceGuid.PciHb1Rb7Base gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress

gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize

• gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
• gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
• gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase

• gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb2IoSize gHisiTokenSpaceGuid.PcdHb0Rb0IoBase gHisiTokenSpaceGuid.PcdHb0Rb0IoSize gHisiTokenSpaceGuid.PcdHb0Rb1IoBase gHisiTokenSpaceGuid.PcdHb0Rb1IoSize gHisiTokenSpaceGuid.PcdHb0Rb2IoBase gHisiTokenSpaceGuid.PcdHb0Rb2IoSize

• gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
• gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
• gHisiTokenSpaceGuid.PcdHb1Rb7IoSize

1.9.1