Re: [Linaro-uefi] [PATCH edk2-platforms v3 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase

On Thu, Sep 21, 2017 at 06:59:49PM +0800, Heyi Guo wrote:

Io BAR should be based IoBase and Mem BAR should be based PciRegionBase.

Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang huangming23@huawei.com

Reviewed-by: Leif Lindholm leif.lindholm@linaro.org

---

Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++++++-------- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 ++++++-- 2 files changed, 35 insertions(+), 17 deletions(-)

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index a970da6..e3d3988 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -1410,9 +1410,8 @@ SetResource( Ptr->ResType = 1; Ptr->GenFlag = 0; Ptr->SpecificFlag = 0;

•    /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  

•    Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  

•                        (RootBridgeInstance->MemBase & 0xFFFFFFFF);
  

•    /* PCIE Device Iobar address should be based on IoBase */
  

•    Ptr->AddrRangeMin = RootBridgeInstance->IoBase;
     Ptr->AddrRangeMax = 0;
     Ptr->AddrTranslationOffset = \
          (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  

@@ -1429,9 +1428,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 32;

•    /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  

•    Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  

•                         (RootBridgeInstance->MemBase & 0xFFFFFFFF);
  

•    /* PCIE device Bar should be based on PciRegionBase */
  

•    if (RootBridgeInstance->PciRegionBase > MAX_UINT32) {
  

•      DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n"));
  

•      return EFI_UNSUPPORTED;
  

•    }
  

•    Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
  

•                        RootBridgeInstance->PciRegionBase;
     Ptr->AddrRangeMax = 0;
     Ptr->AddrTranslationOffset = \
          (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  

@@ -1448,9 +1451,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 32;

•    /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  

•    Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  

•                         (RootBridgeInstance->MemBase & 0xFFFFFFFF);
  

•    /* PCIE device Bar should be based on PciRegionBase */
  

•    if (RootBridgeInstance->PciRegionBase > MAX_UINT32) {
  

•      DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n"));
  

•      return EFI_UNSUPPORTED;
  

•    }
  

•    Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
  

•                        RootBridgeInstance->PciRegionBase;
     Ptr->AddrRangeMax = 0;
     Ptr->AddrTranslationOffset = \
          (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  

@@ -1467,9 +1474,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 64;

•    /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  

•    Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  

•                         (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
  

•    /* PCIE device Bar should be based on PciRegionBase */
  

•    Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
  

•                        RootBridgeInstance->PciRegionBase;
     Ptr->AddrRangeMax = 0;
     Ptr->AddrTranslationOffset = \
          (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  

@@ -1486,9 +1493,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 64;

•    /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  

•    Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  

•                         (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
  

•    /* PCIE device Bar should be based on PciRegionBase */
  

•    Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
  

•                        RootBridgeInstance->PciRegionBase;
     Ptr->AddrRangeMax = 0;
     Ptr->AddrTranslationOffset = \
          (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..10d766a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); for (Index = 0; Index < TypeMax; Index++) { if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {

•  Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
  

•  Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
  

•  switch (Index) {
  

•  case TypeIo:
  

•    Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase;
  

•    break;
  

•  case TypeBus:
  

•    Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
  

•    break;
  

•  default:
  

•  /* PCIE Device bar address should be base on PciRegionBase */
  

•  Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase +
  

•                                                PrivateData->PciRegionBase;
  

•  }
  

•  Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1;
   Configuration.SpaceDesp[Index].AddrLen      = PrivateData->ResAllocNode[Index].Length;
  

  } }

-- 1.9.1