Shaveta,
Have you tried some optimizations to get better performance in UEFI code
I think the question you should be asking is how do you measure how the current code is performing, this is a tools and methodology thing. With ARM there are all sorts of options from JTAG debuggers that can sample things to full up ETM/PTM that can show the flow. So first figure out where time is being spent during your network transfers using your favorite debug tools and with that data you will then know where to focus.
Eugene
-----Original Message----- From: Shaveta Leekha [mailto:shaveta.leekha@nxp.com] Sent: Thursday, July 14, 2016 10:03 PM To: Cohen, Eugene eugene@hp.com; Ard Biesheuvel ard.biesheuvel@linaro.org Cc: edk2-devel@lists.01.org; Linaro UEFI Mailman List <linaro- uefi@lists.linaro.org> Subject: RE: PCI performance issue
You are right Eugene!
Performance is getting impacted by all these factors, but that's true that I shall get better performance figure than this. That's why I am trying to figure out the possible optimizations in code that may help in improving it.
Have you tried some optimizations to get better performance in UEFI code?
Thanks and Regards, Shaveta
-----Original Message----- From: Cohen, Eugene [mailto:eugene@hp.com] Sent: Thursday, July 14, 2016 7:29 PM To: Shaveta Leekha shaveta.leekha@nxp.com; Ard Biesheuvel ard.biesheuvel@linaro.org Cc: edk2-devel@lists.01.org; Linaro UEFI Mailman List <linaro- uefi@lists.linaro.org> Subject: RE: PCI performance issue
I've been down this road before...
Network performance (on non-coherent DMA architectures) can be affected by:
- Excessive double buffering caused by unaligned buffers (PCI
BusMasterRead / BusMasterWrite cases) 2. Excessive accesses to uncached buffers (like PCI common buffer cases) 3. Packet loss due to the lack of interrupts in UEFI, I mean, due to a network polling rate that is too slow (look at the MNP poll and UEFI tick periods)
You should be able to get far better performance than 3MB/min!
Eugene
-----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Shaveta Leekha Sent: Thursday, July 14, 2016 7:45 AM To: Ard Biesheuvel ard.biesheuvel@linaro.org Cc: edk2-devel@lists.01.org; Linaro UEFI Mailman List <linaro- uefi@lists.linaro.org> Subject: Re: [edk2] PCI performance issue
Ok, I can try that !!
Thanks and Regards, Shaveta
-----Original Message----- From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] Sent: Thursday, July 14, 2016 7:11 PM To: Shaveta Leekha shaveta.leekha@nxp.com Cc: edk2-devel@lists.01.org; Linaro UEFI Mailman List <linaro- uefi@lists.linaro.org> Subject: Re: PCI performance issue
On 14 July 2016 at 15:29, Shaveta Leekha shaveta.leekha@nxp.com
wrote:
But I have not tested the code (software) on any other hardware/board. As I have not yet ported PCI code on any other board yet.
I would recommend to base your expectations not on U-Boot but on UEFI running on a different architecture using similar network hardware. _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel