On Tue, Oct 18, 2016 at 09:09:51PM +0800, Heyi Guo wrote:
There might be multiple PCIe associated ITS in the system, so we change PCD of MSI target address to a feature PCD and specify the addresses in the code. If ITS is not supported by OS, MSI target address will be set to GIC distributor.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 ++- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 10 +++++++--- Chips/Hisilicon/HisiPkg.dec | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 8659e29..8b10dbc 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -51,9 +51,10 @@ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P gHisiTokenSpaceGuid.Pcdsoctype
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress
- gArmTokenSpaceGuid.PcdGicDistributorBase
[FeaturePcd]
- gHisiTokenSpaceGuid.PcdIsItsSupported gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable
[depex] diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index dd851bc..fa48a6e 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -917,9 +917,13 @@ VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 Value = 0;
- RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdPcieMsiTargetAddress));
- RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c4, 0);
- if (FeaturePcdGet (PcdIsItsSupported)) {
RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PCIE_ITS_1610[HostBridgeNum][Port]);RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c4, PCIE_ITS_1610[HostBridgeNum][Port] >> 32);
Can we have some kind of #define for those 0x11b4/0x11c4?
- } else {
RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdGicDistributorBase) + 0x40);RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c4, (PcdGet64 (PcdGicDistributorBase) + 0x40) >> 32);- } RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); Value |= (1 << 12); RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 6054118..53ec269 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -267,11 +267,11 @@ gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064 gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056
[PcdsFeatureFlag] gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066
- gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 942b2b8..7c72c84 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -112,6 +112,7 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE
- gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
[PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" @@ -309,7 +310,6 @@ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0xc6010040
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1.9.1