On Sat, Nov 19, 2016 at 04:38:08PM +0800, Heyi Guo wrote:
Check the value of register(0xD000E014) to decide whether this is 50MHZ or 66MHZ board attached. Configure register PHY_CTRL to support 50MHZ or 66MHZ. Default Configure of PHY_CTRL is the configure of 50MHZ, if 66MHZ board attached, change the value of PHY_CTRL.
D03 have 66M and 50M two types boards, they refer the different reference clock, set the PCD to 0 so that the code will read frequency from register and be adapted to 66M and 50M boards, so also update FVMAIN_SEC binary to adapt different configuration about 50MHZ and 66MHZ boards.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiang Chen chenxiang66@Hisilicon.com Review-by: Graeme Gregory graeme.gregory@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 122 ++++++++++++++++++++- Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/D03/D03.dsc | 4 +- 3 files changed, 124 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index e19ea18..9944a50 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -80,6 +80,32 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -88,6 +114,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)}@@ -157,6 +196,32 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -165,6 +230,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)}@@ -216,7 +294,7 @@ Scope(_SB) Package () {"interrupt-parent",Package() {_SB.MBI2}}, Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, Package () {"queue-count", 16},
Package () {"phy-count", 8},
Package () {"phy-count", 9}, }@@ -233,6 +311,34 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,offset (0x2014),PHY8, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -241,6 +347,20 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)Store(Local1, PHY8)}diff --git a/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv index 1050b92..1830a6a 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv and b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv differ diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index aa085da..850b16b 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -218,7 +218,9 @@ # # ARM Architectual Timer Frequency #
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|66000000
- # Set it to 0 so that the code will read frequence from register and be
- # adapted to 66M and 50M boards
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE -- 1.9.1