From: Jan Dąbroś jsd@semihalf.com
Because Xenon SD/MMC controller isn't fully compatible with SDHC, it demands some quirks on generic driver during initialization, i.e. limit bus width to 4, no voltage switch and hence disable highest speed modes, etc. Moreover, Xenon-specific init sequence is required, because it configures custom set of registers of Sd/Mmc PHY.
Two files containing Xenon-specific functions and defines were added.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 121 +++--- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 40 +- Drivers/SdMmc/XenonDxe/XenonSdhci.c | 665 +++++++++++++++++++++++++++++++ Drivers/SdMmc/XenonDxe/XenonSdhci.h | 346 ++++++++++++++++ 4 files changed, 1087 insertions(+), 85 deletions(-) create mode 100755 Drivers/SdMmc/XenonDxe/XenonSdhci.c create mode 100644 Drivers/SdMmc/XenonDxe/XenonSdhci.h
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 4c1b5c8..981eab5 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -5,6 +5,8 @@ It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> + Copyright (C) 2016 Marvell International Ltd. All rigths reserved.<BR> + This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -16,6 +18,7 @@ **/
#include "SdMmcPciHcDxe.h" +#include "XenonSdhci.h"
// // Driver Global Variables @@ -520,13 +523,10 @@ SdMmcPciHcDriverBindingStart ( EFI_PCI_IO_PROTOCOL *PciIo; UINT64 Supports; UINT64 PciAttributes; - UINT8 SlotNum; - UINT8 FirstBar; UINT8 Slot; UINT8 Index; CARD_TYPE_DETECT_ROUTINE *Routine; UINT32 RoutineNum; - BOOLEAN MediaPresent; BOOLEAN Support64BitDma;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); @@ -593,78 +593,77 @@ SdMmcPciHcDriverBindingStart ( Private->PciAttributes = PciAttributes; InitializeListHead (&Private->Queue);
+ Support64BitDma = TRUE; + // - // Get SD/MMC Pci Host Controller Slot info + // There is only one slot 0 on Xenon // - Status = SdMmcHcGetSlotInfo (PciIo, &FirstBar, &SlotNum); + Slot = 0; + Private->Slot[Slot].Enable = TRUE; + + Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]); if (EFI_ERROR (Status)) { - goto Done; + return Status; }
- Support64BitDma = TRUE; - for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) { - Private->Slot[Slot].Enable = TRUE; + Support64BitDma &= Private->Capability[Slot].SysBus64;
- Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]); - if (EFI_ERROR (Status)) { - continue; - } - DumpCapabilityReg (Slot, &Private->Capability[Slot]); + // + // Override capabilities structure - only 4 Bit width bus is supported + // by HW and also force using SDR25 mode + // + Private->Capability[Slot].Sdr104 = 0; + Private->Capability[Slot].Ddr50 = 0; + Private->Capability[Slot].Sdr50 = 0; + Private->Capability[Slot].BusWidth8 = 0;
- Support64BitDma &= Private->Capability[Slot].SysBus64; + if (Private->Capability[Slot].BaseClkFreq == 0) { + Private->Capability[Slot].BaseClkFreq = 0xff; + }
- Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); - if (EFI_ERROR (Status)) { - continue; - } + DumpCapabilityReg (Slot, &Private->Capability[Slot]);
- Private->Slot[Slot].SlotType = Private->Capability[Slot].SlotType; - if ((Private->Slot[Slot].SlotType != RemovableSlot) && (Private->Slot[Slot].SlotType != EmbeddedSlot)) { - DEBUG ((DEBUG_INFO, "SdMmcPciHcDxe doesn't support the slot type [%d]!!!\n", Private->Slot[Slot].SlotType)); - continue; - } + Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); + if (EFI_ERROR (Status)) { + return Status; + }
- // - // Reset the specified slot of the SD/MMC Pci Host Controller - // - Status = SdMmcHcReset (PciIo, Slot); - if (EFI_ERROR (Status)) { - continue; - } - // - // Check whether there is a SD/MMC card attached - // - Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent); - if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) { - continue; - } else if (!MediaPresent) { - DEBUG ((EFI_ERROR, "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n", Slot)); - continue; - } + Private->Slot[Slot].SlotType = Private->Capability[Slot].SlotType; + if ((Private->Slot[Slot].SlotType != RemovableSlot) && (Private->Slot[Slot].SlotType != EmbeddedSlot)) { + DEBUG ((DEBUG_INFO, "SdMmcPciHcDxe doesn't support the slot type [%d]!!!\n", Private->Slot[Slot].SlotType)); + return EFI_D_ERROR; + }
- Status = SdMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]); - if (EFI_ERROR (Status)) { - continue; - } + // + // Perform Xenon-specific init sequence + // + XenonInit (Private);
- Private->Slot[Slot].MediaPresent = TRUE; - Private->Slot[Slot].Initialized = TRUE; - RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE); - for (Index = 0; Index < RoutineNum; Index++) { - Routine = &mCardTypeDetectRoutineTable[Index]; - if (*Routine != NULL) { - Status = (*Routine) (Private, Slot); - if (!EFI_ERROR (Status)) { - break; - } + // + // Initialize HC timeout control + // + Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot); + if (EFI_ERROR (Status)) { + return Status; + } + + Private->Slot[Slot].MediaPresent = TRUE; + Private->Slot[Slot].Initialized = TRUE; + RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE); + for (Index = 0; Index < RoutineNum; Index++) { + Routine = &mCardTypeDetectRoutineTable[Index]; + if (*Routine != NULL) { + Status = (*Routine) (Private, Slot); + if (!EFI_ERROR (Status)) { + break; } } - // - // This card doesn't get initialized correctly. - // - if (Index == RoutineNum) { - Private->Slot[Slot].Initialized = FALSE; - } + } + // + // This card doesn't get initialized correctly. + // + if (Index == RoutineNum) { + Private->Slot[Slot].Initialized = FALSE; }
// diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index e26e6a0..fad9fc6 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -6,6 +6,7 @@ # to specified devices from upper layer. # # Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> +# Copyright (C) 2016 Marvell International Ltd. All rights reserved.<BR> # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -18,47 +19,38 @@ ##
[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = SdMmcPciHcDxe + INF_VERSION = 0x00010019 + BASE_NAME = XenonDxe MODULE_UNI_FILE = SdMmcPciHcDxe.uni - FILE_GUID = 8E325979-3FE1-4927-AAE2-8F5C4BD2AF0D + FILE_GUID = 17f56b40-f7c1-435c-ab8d-404872da951e MODULE_TYPE = UEFI_DRIVER VERSION_STRING = 1.0 ENTRY_POINT = InitializeSdMmcPciHcDxe
-# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = IA32 X64 IPF EBC -# -# DRIVER_BINDING = gSdMmcPciHcDxeDriverBinding -# COMPONENT_NAME = gSdMmcPciHcDxeComponentName -# COMPONENT_NAME2 = gSdMmcPciHcDxeComponentName2 -# -# - [Sources] - SdMmcPciHcDxe.h - SdMmcPciHcDxe.c + ComponentName.c EmmcDevice.c SdDevice.c - SdMmcPciHci.h + SdMmcPciHcDxe.c + SdMmcPciHcDxe.h SdMmcPciHci.c - ComponentName.c + SdMmcPciHci.h + XenonSdhci.c + XenonSdhci.h
[Packages] MdePkg/MdePkg.dec
[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib DevicePathLib - UefiBootServicesTableLib - UefiRuntimeServicesTableLib MemoryAllocationLib - BaseMemoryLib - UefiLib - BaseLib + UefiBootServicesTableLib UefiDriverEntryPoint - DebugLib + UefiLib + UefiRuntimeServicesTableLib
[Protocols] gEfiDevicePathProtocolGuid ## TO_START diff --git a/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Drivers/SdMmc/XenonDxe/XenonSdhci.c new file mode 100755 index 0000000..31f207e --- /dev/null +++ b/Drivers/SdMmc/XenonDxe/XenonSdhci.c @@ -0,0 +1,665 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "XenonSdhci.h" + +STATIC +VOID +XenonReadVersion ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + OUT UINT32 *ControllerVersion + ) +{ + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CTRL_VER, TRUE, SDHC_REG_SIZE_2B, ControllerVersion); +} + +STATIC +VOID +XenonSetFifo ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINTN Data; + + // Set FIFO_RTC, FIFO_WTC, FIFO_CS and FIFO_PDLVMC + Data = SDHC_SLOT_FIFO_DEFAULT_CONFIG; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, SDHC_REG_SIZE_4B, &Data); +} + +// Auto Clock Gating +STATIC +VOID +XenonSetAcg ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN BOOLEAN Enable + ) +{ + UINT32 Var; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, SDHC_REG_SIZE_4B, &Var); + + if (Enable) { + Var &= ~AUTO_CLKGATE_DISABLE_MASK; + } else { + Var |= AUTO_CLKGATE_DISABLE_MASK; + } + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, SDHC_REG_SIZE_4B, &Var); +} + +STATIC +VOID +XenonSetSlot ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN BOOLEAN Enable + ) +{ + UINT32 Var; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, SDHC_REG_SIZE_4B, &Var); + if (Enable) { + Var |= ((0x1 << Slot) << SLOT_ENABLE_SHIFT); + } else { + Var &= ~((0x1 << Slot) << SLOT_ENABLE_SHIFT); + } + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, SDHC_REG_SIZE_4B, &Var); +} + +// +// Stub function, which will in future be responsible for +// setting SDIO controller in either HIGH (if Voltage parameter +// is equal 1) or LOW (if Voltage is equal 0) +// +STATIC +VOID +XenonSetSdio ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINTN Voltage + ) +{ + // Currently SDIO isn't supported + return; +} + +STATIC +VOID +XenonSetPower ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT32 Vcc, + IN UINT32 Vccq, + IN UINT8 Mode + ) +{ + UINT8 Pwr = 0; + UINT32 Ctrl = 0; + + // Below statement calls routine to set voltage for SDIO devices in either HIGH (1) or LOW (0) mode + switch (Vcc) { + case MMC_VDD_165_195: + Pwr = SDHCI_POWER_180; + if (Mode == XENON_MMC_MODE_SD_SDIO) { + XenonSetSdio (PciIo, 0); + } + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + Pwr = SDHCI_POWER_300; + if (Mode == XENON_MMC_MODE_SD_SDIO) { + XenonSetSdio (PciIo, 1); + } + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + Pwr = SDHCI_POWER_330; + if (Mode == XENON_MMC_MODE_SD_SDIO) { + XenonSetSdio (PciIo, 1); + } + break; + default: + DEBUG((DEBUG_ERROR, "SD/MMC: Does not support power mode(0x%X)\n", Vcc)); + break; + } + + if (Pwr == 0) { + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_POWER_CTRL, FALSE, SDHC_REG_SIZE_1B, &Pwr); + return; + } + + Pwr |= SDHCI_POWER_ON; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_POWER_CTRL, FALSE, SDHC_REG_SIZE_1B, &Pwr); + + // Set VCCQ + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, TRUE, SDHC_REG_SIZE_4B, &Ctrl); + Ctrl |= Vccq; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, FALSE, SDHC_REG_SIZE_4B, &Ctrl); +} + +UINTN +XenonSetClk ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT32 Clock + ) +{ + UINT32 Div; + UINT32 Clk; + UINT32 Retry; + UINT16 Value = 0; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &Value); + + if (Clock == 0) { + return 0; + } + + if (Private->ControllerVersion >= SDHCI_SPEC_300) { + // Version 3.00 Divisors must be a multiple of 2 + if (XENON_MMC_MAX_CLK <= Clock) { + Div = 1; + } else { + for (Div = 2; Div < SDHCI_MAX_DIV_SPEC_300; Div += 2) { + if ((XENON_MMC_MAX_CLK / Div) <= Clock) + break; + } + } + } else { + // Version 2.00 Divisors must be a power of 2 + for (Div = 1; Div < SDHCI_MAX_DIV_SPEC_200; Div *= 2) { + if ((XENON_MMC_MAX_CLK / Div) <= Clock) + break; + } + } + Div >>= 1; + + Clk = (Div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; + Clk |= ((Div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; + Clk |= SDHCI_CLOCK_INT_EN; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &Clk); + + // + // Poll for internal controller clock to be stabilised + // Wait up to 200us for this to occur + // + Retry = 200; + + do { + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &Clk); + if (Retry == 0) { + DEBUG((DEBUG_ERROR, "SD/MMC: Internal Clock never stabilised\n")); + return -1; + } + + Retry--; + + // Wait for internal clock to be stabilised + gBS->Stall (1); + + } while (!(Clk & SDHCI_CLOCK_INT_STABLE)); + + Clk |= SDHCI_CLOCK_CARD_EN; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &Clk); + + return 0; +} + +VOID +XenonPhyInit ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINT32 Var, Wait, Time; + UINT32 Clock = XENON_MMC_MAX_CLK; + UINT16 ClkCtrl; + + // Need to disable the clock to set EMMC_PHY_TIMING_ADJUST register + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &ClkCtrl); + ClkCtrl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &ClkCtrl); + + // Enable QSP PHASE SELECT + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var); + Var |= SAMPL_INV_QSP_PHASE_SELECT; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var); + + // Enable internal clock + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &ClkCtrl); + ClkCtrl |= SDHCI_CLOCK_INT_EN; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &ClkCtrl); + + // + // Poll for host MMC PHY clock init to be stable + // Wait up to 100us + // + Time = 100; + while (Time--) { + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var); + if (Var & SDHCI_CLOCK_INT_STABLE) { + break; + } + + // Poll interval for MMC PHY clock to be stable is 1us + gBS->Stall (1); + } + if (Time <= 0) { + DEBUG((DEBUG_ERROR, "SD/MMC: Failed to enable MMC internal clock in Time\n")); + return; + } + + // Enable bus clock + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &ClkCtrl); + ClkCtrl |= SDHCI_CLOCK_CARD_EN; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &ClkCtrl); + + // Delay 200us to wait for the completion of bus clock + gBS->Stall (200); + + // Init PHY + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var); + Var |= PHY_INITIALIZAION; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var); + + // Add duration of FC_SYNC_RST + Wait = ((Var >> FC_SYNC_RST_DURATION_SHIFT) & FC_SYNC_RST_DURATION_MASK); + + // Add interval between FC_SYNC_EN and FC_SYNC_RST + Wait += ((Var >> FC_SYNC_RST_EN_DURATION_SHIFT) & FC_SYNC_RST_EN_DURATION_MASK); + + // Add duration of asserting FC_SYNC_EN + Wait += ((Var >> FC_SYNC_EN_DURATION_SHIFT) & FC_SYNC_EN_DURATION_MASK); + + // Add duration of Waiting for PHY + Wait += ((Var >> WAIT_CYCLE_BEFORE_USING_SHIFT) & WAIT_CYCLE_BEFORE_USING_MASK); + + // 4 addtional bus clock and 4 AXI bus clock are required left shift 20 bits + Wait += 8; + Wait <<= 20; + + // Use the possibly slowest bus frequency value + if (Clock == 0) { + Clock = XENON_MMC_MIN_CLK; + } + + // Get the Wait Time in unit of ms + Wait = Wait / Clock; + Wait++; + + // Poll for host eMMC PHY init to complete, wait up to 100us + Time = 100; + while (Time--) { + Var = SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var); + Var &= PHY_INITIALIZAION; + if (!Var) { + break; + } + + // Wait for host eMMC PHY init to complete + gBS->Stall (1); + } + + if (Time <= 0) { + DEBUG((DEBUG_ERROR, "SD/MMC: Failed to init MMC PHY in Time\n")); + return; + } + + return; +} + +STATIC +VOID +XenonSetPhy ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + UINT8 Timing + ) +{ + UINT32 Var = 0; + + // Setup pad, set bit[30], bit[28] and bits[26:24] + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, TRUE, SDHC_REG_SIZE_4B, &Var); + Var |= (AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | FC_CMD_RECEN | FC_DQ_RECEN); + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, FALSE, SDHC_REG_SIZE_4B, &Var); + + // + // If Timing belongs to high speed, set bit[17] of + // EMMC_PHY_TIMING_ADJUST register + // + if ((Timing == MMC_TIMING_MMC_HS400) || + (Timing == MMC_TIMING_MMC_HS200) || + (Timing == MMC_TIMING_UHS_SDR50) || + (Timing == MMC_TIMING_UHS_SDR104) || + (Timing == MMC_TIMING_UHS_DDR50) || + (Timing == MMC_TIMING_UHS_SDR25)) { + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var); + + // Set SLOW_MODE for PHY + Var |= OUTPUT_QSN_PHASE_SELECT | QSN_PHASE_SLOW_MODE_BIT; + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var); + } + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, SDHC_REG_SIZE_4B, &Var); + Var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE; + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, SDHC_REG_SIZE_4B, &Var); + + if (Timing == MMC_TIMING_MMC_HS400) { + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, SDHC_REG_SIZE_4B, &Var); + Var &= ~DQ_ASYNC_MODE; + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, SDHC_REG_SIZE_4B, &Var); + + Var = LOGIC_TIMING_VALUE; + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_LOGIC_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var); + } + + XenonPhyInit (PciIo); +} + +STATIC +VOID +XenonConfigureInterrupts ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINT32 Var; + + // Clear interrupt status + Var = SDHC_CLR_ALL_IRQ_MASK; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, SDHC_REG_SIZE_4B, &Var); + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, SDHC_REG_SIZE_4B, &Var); + + // Enable only interrupts served by the SD controller + Var = SDHC_CLR_ALL_IRQ_MASK & ~(NOR_INT_STS_CARD_INS | NOR_INT_STS_CARD_INT); + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS_EN, FALSE, SDHC_REG_SIZE_4B, &Var); + + // Mask all sdhci interrupt sources + Var = SDHC_CLR_ALL_IRQ_MASK & ~NOR_INT_SIG_EN_CARD_INT; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_SIG_EN, FALSE, SDHC_REG_SIZE_4B, &Var); +} + +// Enable Parallel Transfer Mode +STATIC +VOID +XenonSetParallelTransfer ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN BOOLEAN Enable + ) +{ + UINT32 Var; + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, TRUE, SDHC_REG_SIZE_4B, &Var); + + if (Enable) { + Var |= (0x1 << Slot); + } else { + Var &= ~(0x1 << Slot); + } + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, FALSE, SDHC_REG_SIZE_4B, &Var); +} + +STATIC +VOID +XenonSetTuning ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN BOOLEAN Enable + ) +{ + UINT32 Var; + + // Set the Re-Tuning Request functionality + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, TRUE, SDHC_REG_SIZE_4B, &Var); + + if (Enable) { + Var |= RETUNING_COMPATIBLE; + } else { + Var &= ~RETUNING_COMPATIBLE; + } + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, FALSE, SDHC_REG_SIZE_4B, &Var); + + // Set the Re-tuning Event Signal Enable + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, TRUE, SDHC_REG_SIZE_4B, &Var); + + if (Enable) { + Var |= SDHCI_RETUNE_EVT_INTSIG; + } else { + Var &= ~SDHCI_RETUNE_EVT_INTSIG; + } + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, FALSE, SDHC_REG_SIZE_4B, &Var); +} + +VOID +XenonReset ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN UINT8 Mask + ) +{ + UINT32 Retry = 1000; + UINT8 SwReset; + + SwReset = Mask; + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_SW_RST, + FALSE, + sizeof (SwReset), + &SwReset + ); + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_SW_RST, + TRUE, + sizeof (SwReset), + &SwReset + ); + + while (SwReset & Mask) { + if (Retry == 0) { + DEBUG((DEBUG_ERROR, "SD/MMC: Reset never completed\n")); + return; + } + + Retry--; + + // Poll interval for SwReset is 100us according to SDHCI spec + gBS-> Stall (100); + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_SW_RST, + TRUE, + sizeof (SwReset), + &SwReset + ); + } +} + +STATIC +VOID +XenonTransferPio ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN OUT VOID *Buffer, + IN UINT16 BlockSize, + IN BOOLEAN Read + ) +{ + UINTN Index; + UINT8 *Offs; + + // + // SD stack's intrinsic functions cannot perform properly reading/writing from + // buffer register, that is why MmioRead/MmioWrite are used. It is temporary + // solution. + // + for (Index = 0; Index < BlockSize; Index += 4) { + Offs = Buffer + Index; + if (Read) { + *(UINT32 *)Offs = MmioRead32 (SDHC_DAT_BUF_PORT_ADDR); + } else { + MmioWrite32 (SDHC_DAT_BUF_PORT_ADDR, *(UINT32 *)Offs); + } + } +} + +EFI_STATUS +XenonTransferData ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN OUT VOID *Buffer, + IN UINT32 DataLen, + IN UINT16 BlockSize, + IN UINT16 Blocks, + IN BOOLEAN Read + ) +{ + UINT32 IntStatus, PresentState, Rdy, Mask, Retry, Block = 0; + + if (Buffer == NULL) { + return EFI_DEVICE_ERROR; + } + + Retry = SDHC_INT_STATUS_POLL_RETRY_DATA_TRAN; + Rdy = NOR_INT_STS_TX_RDY | NOR_INT_STS_RX_RDY; + Mask = PRESENT_STATE_BUFFER_RD_EN | PRESENT_STATE_BUFFER_WR_EN; + + do { + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + TRUE, + sizeof (IntStatus), + &IntStatus + ); + + if (IntStatus & NOR_INT_STS_ERR_INT) { + DEBUG((DEBUG_INFO, "SD/MMC: Error detected in status %0x\n", IntStatus)); + return EFI_DEVICE_ERROR; + } + + if (IntStatus & Rdy) { + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_PRESENT_STATE, + TRUE, + sizeof (PresentState), + &PresentState + ); + + if (!(PresentState & Mask)) { + continue; + } + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + FALSE, + sizeof (Rdy), + &Rdy + ); + + XenonTransferPio (Private, Slot, Buffer, BlockSize, Read); + + Buffer += BlockSize; + if (++Block >= Blocks) { + break; + } + } + + if (Retry-- > 0) { + + // Poll interval for data transfer complete bit in NOR_INT_STS register is 10us + gBS->Stall (10); + } else { + DEBUG((DEBUG_INFO, "SD/MMC: Transfer data timeout\n")); + return EFI_TIMEOUT; + } + } while (!(IntStatus & NOR_INT_STS_XFER_COMPLETE)); + + return EFI_SUCCESS; +} + +EFI_STATUS +XenonInit ( + IN SD_MMC_HC_PRIVATE_DATA *Private + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo = Private->PciIo; + + // Read XENON version + XenonReadVersion (PciIo, &Private->ControllerVersion); + + XenonSetFifo (PciIo); + + // Disable auto clock generator + XenonSetAcg (PciIo, FALSE); + + // XENON has only one port + XenonSetSlot (PciIo, XENON_MMC_SLOT_ID, TRUE); + + XenonSetPower (PciIo, MMC_VDD_165_195, eMMC_VCCQ_1_8V, XENON_MMC_MODE_SD_SDIO); + + // Set MAX_CLOCK for configuring PHY + XenonSetClk (PciIo, Private, XENON_MMC_MAX_CLK); + XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50); + + XenonConfigureInterrupts (PciIo); + + // Enable parallel transfer + XenonSetParallelTransfer (PciIo, XENON_MMC_SLOT_ID, TRUE); + XenonSetTuning (PciIo, XENON_MMC_SLOT_ID, FALSE); + + // Enable auto clock generator + XenonSetAcg (PciIo, TRUE); + + // Set proper clock for PHY configuration + XenonSetClk (PciIo, Private, XENON_MMC_BASE_CLK); + XenonPhyInit (PciIo); + + return EFI_SUCCESS; +} diff --git a/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Drivers/SdMmc/XenonDxe/XenonSdhci.h new file mode 100644 index 0000000..2be0ee6 --- /dev/null +++ b/Drivers/SdMmc/XenonDxe/XenonSdhci.h @@ -0,0 +1,346 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "SdMmcPciHcDxe.h" + +#include <Library/IoLib.h> + +#define SD_BAR_INDEX 0 + +#define SIZE_512B 0x200 + +/* Register Offset of SD Host Controller SOCP self-defined register */ + +#define SDHC_IPID 0x0100 +#define SDHC_SYS_CFG_INFO 0x0104 +#define SLOT_TYPE_SDIO_SHIFT 24 +#define SLOT_TYPE_EMMC_MASK 0xff +#define SLOT_TYPE_EMMC_SHIFT 16 +#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xff +#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8 + +#define SDHC_SYS_OP_CTRL 0x0108 +#define AUTO_CLKGATE_DISABLE_MASK (0x1<<20) +#define SDCLK_IDLEOFF_ENABLE_SHIFT 8 +#define SLOT_ENABLE_SHIFT 0 + +#define SDHC_SYS_EXT_OP_CTRL 0x010c +#define SDHC_TEST_OUT 0x0110 +#define SDHC_TESTOUT_MUXSEL 0x0114 + +#define SDHC_SLOT_EXT_INT_STATUS 0x0120 +#define SDHC_SLOT_EXT_ERR_STATUS 0x0122 +#define SDHC_SLOT_EXT_INT_STATUS_EN 0x0124 +#define SDHC_SLOT_EXT_ERR_STATUS_EN 0x0126 + +#define SDHC_SLOT_OP_STATUS_CTRL 0x0128 +#define TUNING_PROG_FIXED_DELAY_MASK 0x7ff +#define FORCE_SEL_INVERSE_CLK_SHIFT 11 + +#define SDHC_SLOT_FIFO_CTRL 0x012c +#define SDHC_SLOT_FIFO_DEFAULT_CONFIG 0x315 + +#define SDHC_SLOT_eMMC_CTRL 0x0130 +#define ENABLE_DATA_STROBE_SHIFT 24 +#define SET_EMMC_RSTN_SHIFT 16 +#define eMMC_VCCQ_MASK 0x3 +#define eMMC_VCCQ_1_8V 0x1 +#define eMMC_VCCQ_1_2V 0x2 +#define eMMC_VCCQ_3_3V 0x3 + +#define SDHC_SLOT_OUTPUT_DLY_CTRL 0x0134 +#define SDHC_SLOT_DCM_CTRL 0x0137 + +#define SDHC_SLOT_DLL_CTRL 0x0138 +#define SELECT_DEF_DLL 0x1 + +#define SDHC_SLOT_DLL_PHASE_SEL 0x013c +#define DLL_UPDATE_STROBE 7 + +#define SDHC_SLOT_STROBE_DLY_CTRL 0x0140 +#define STROBE_DELAY_FIXED_MASK 0xffff + +#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144 +#define RETUNING_COMPATIBLE 0x1 + +#define SDHC_SLOT_AUTO_RETUNING_CTRL 0x0148 +#define ENABLE_AUTO_RETUNING 0x1 + +#define SDHC_SLOT_EXT_PRESENT_STATE 0x014c +#define SDHC_SLOT_DLL_CUR_DLY_VAL 0x0150 +#define SDHC_SLOT_TUNING_CUR_DLY_VAL 0x0154 +#define SDHC_SLOT_STROBE_CUR_DLY_VAL 0x0158 +#define SDHC_SLOT_SUB_CMD_STRL 0x015c + +#define SDHC_SLOT_CQ_TASK_INFO 0x0160 + +#define SDHC_SLOT_TUNING_DEBUG_INFO 0x01f0 +#define SDHC_SLOT_DATAIN_DEBUG_INFO 0x01f4 + +#define SDHC_CMD_RESET_BIT (1 << 1) +#define SDHC_DATA_RESET_BIT (1 << 2) + +#define SDHC_CMD_INHIBIT (1 << 0) +#define SDHC_DATA_INHIBIT (1 << 1) + +#define SDHC_REG_SIZE_1B 1 +#define SDHC_REG_SIZE_2B 2 +#define SDHC_REG_SIZE_4B 4 + +#define SDHC_DAT_BUF_PORT_ADDR 0xF06E0020 + +/* Command register bits description */ +#define RESP_TYPE_136_BITS (1 << 0) +#define RESP_TYPE_48_BITS (1 << 1) +#define RESP_TYPE_48_BITS_NO_CRC ((1 << 0) | (1 << 1)) +#define CMD_CRC_CHK_EN (1 << 3) +#define CMD_INDEX_CHK_EN (1 << 4) +#define DATA_PRESENT (1 << 5) + +/* Transfer mode register bits description */ +#define SDHC_TRNS_BLK_CNT_EN (1 << 1) +#define SDHC_TRNS_MULTI_BLK_SEL (1 << 5) +#define SDHC_TRNS_TO_HOST_DIR (1 << 4) + +/* Block size register bits description */ +#define BLK_SIZE_HOST_DMA_BDRY_OFFSET 12 +#define BLK_SIZE_512KB 0x7 + +/* Int status register bits description */ +#define NOR_INT_STS_CMD_COMPLETE (1 << 0) +#define NOR_INT_STS_XFER_COMPLETE (1 << 1) +#define NOR_INT_STS_TX_RDY (1 << 4) +#define NOR_INT_STS_RX_RDY (1 << 5) +#define NOR_INT_STS_CARD_INS (1 << 6) +#define NOR_INT_STS_CARD_INT (1 << 8) +#define NOR_INT_STS_ERR_INT (1 << 15) +#define ERR_INT_STS_CMD_TIMEOUT_ERR (1 << 16) +#define ERR_INT_STS_DATA_TIMEOUT_ERR (1 << 20) + +#define NOR_INT_SIG_EN_CARD_INT (1 << 8) + +#define PRESENT_STATE_BUFFER_RD_EN (1 << 11) +#define PRESENT_STATE_BUFFER_WR_EN (1 << 10) + +#define SDHC_CLR_IRQ_STS_MASK 0xFFFF +#define SDHC_CLR_ALL_IRQ_MASK 0xFFFFFFFFUL + +/* Max clock in Hz */ +#define XENON_MMC_MAX_CLK 400000000 +#define XENON_MMC_CLK_RATIO 2046 +#define XENON_MMC_BASE_CLK XENON_MMC_MAX_CLK / XENON_MMC_CLK_RATIO +#define XENON_MMC_MIN_CLK 100000 + +#define XENON_MMC_CMD_MAX_TIMEOUT 3200 +#define XENON_MMC_CMD_DEFAULT_TIMEOUT 100 + +/* Tuning Parameter */ +#define TMR_RETUN_NO_PRESENT 0xf +#define XENON_MAX_TUN_COUNT 0xb + +#define EMMC_PHY_REG_BASE 0x170 +#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE +#define OUTPUT_QSN_PHASE_SELECT (1 << 17) +#define SAMPL_INV_QSP_PHASE_SELECT (1 << 18) +#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 +#define PHY_INITIALIZAION (1 << 31) +#define WAIT_CYCLE_BEFORE_USING_MASK 0xf +#define WAIT_CYCLE_BEFORE_USING_SHIFT 12 +#define FC_SYNC_EN_DURATION_MASK 0xf +#define FC_SYNC_EN_DURATION_SHIFT 8 +#define FC_SYNC_RST_EN_DURATION_MASK 0xf +#define FC_SYNC_RST_EN_DURATION_SHIFT 4 +#define FC_SYNC_RST_DURATION_MASK 0xf +#define FC_SYNC_RST_DURATION_SHIFT 0 + +#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4) +#define DQ_ASYNC_MODE (1 << 4) +#define DQ_DDR_MODE_SHIFT 8 +#define DQ_DDR_MODE_MASK 0xff +#define CMD_DDR_MODE (1 << 16) + +#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8) +#define REC_EN_SHIFT 24 +#define REC_EN_MASK 0xf +#define FC_DQ_RECEN (1 << 24) +#define FC_CMD_RECEN (1 << 25) +#define FC_QSP_RECEN (1 << 26) +#define FC_QSN_RECEN (1 << 27) +#define OEN_QSN (1 << 28) +#define AUTO_RECEN_CTRL (1 << 30) + +#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc) +#define EMMC_PHY_PAD_CONTROL2 (EMMC_PHY_REG_BASE + 0x10) +#define EMMC_PHY_DLL_CONTROL (EMMC_PHY_REG_BASE + 0x14) +#define DLL_DELAY_TEST_LOWER_SHIFT 8 +#define DLL_DELAY_TEST_LOWER_MASK 0xff +#define DLL_BYPASS_EN 0x1 + +#define EMMC_LOGIC_TIMING_ADJUST (EMMC_PHY_REG_BASE + 0x18) +#define EMMC_LOGIC_TIMING_ADJUST_LOW (EMMC_PHY_REG_BASE + 0x1c) + +#define LOGIC_TIMING_VALUE 0x5a54 /* Recommend by HW team */ + +#define QSN_PHASE_SLOW_MODE_BIT (1 << 29) + +/* XENON only have one slot 0 */ +#define XENON_MMC_SLOT_ID (0) + +#define MMC_TIMING_LEGACY 0 +#define MMC_TIMING_MMC_HS 1 +#define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 3 +#define MMC_TIMING_UHS_SDR25 4 +#define MMC_TIMING_UHS_SDR50 5 +#define MMC_TIMING_UHS_SDR104 6 +#define MMC_TIMING_UHS_DDR50 7 +#define MMC_TIMING_MMC_HS200 8 +#define MMC_TIMING_MMC_HS400 10 + +/* Data time out default value 0xE: TMCLK x 227 */ +#define DATA_TIMEOUT_DEF_VAL 0xE + +/* Max retry count for INT status ready */ +#define SDHC_INT_STATUS_POLL_RETRY 1000 +#define SDHC_INT_STATUS_POLL_RETRY_DATA_TRAN 100000 + +/* Take 2.5 seconds as generic time out value, 1 microsecond as unit */ +#define SD_GENERIC_TIMEOUT 2500 * 1000 + +/* SDMA start address should allign with 0x8, align mask 0x7 */ +#define DMA_START_ADDR_ALIGN_MASK 0x7 + +#define SDHCI_RETUNE_EVT_INTSIG 0x00001000 + +/* MMC modes */ +#define XENON_MMC_MODE_EMMC 0 +#define XENON_MMC_MODE_SD_SDIO 1 + +/* MMC Voltage */ +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +/* SDHCI FLAGS */ +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_SHIFT 6 +#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK_LEN 8 +#define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_INT_STABLE 0x0002 +#define SDHCI_CLOCK_INT_EN 0x0001 + +#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2 + +#define SDHCI_SIGNAL_ENABLE 0x38 + +#define SDHCI_MAX_DIV_SPEC_200 256 +#define SDHCI_MAX_DIV_SPEC_300 2046 + +/* SD DEVICE STATUS FLAGS */ +#define CURRENT_STATE_MASK (0xF << 9) +#define CURRENT_STATE_N_READY_MASK (7 << 9) +#define READY_FOR_DATA (1 << 8) +#define CARD_STATUS_ERROR_MASK (~0x0206BF7F) + +#define RCA_BITS_OFFSET 16 + +UINTN +XenonSetClk ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT32 Clock + ); + +VOID +XenonPhyInit ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ); + +VOID +XenonReset ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN UINT8 Mask + ); + +EFI_STATUS +XenonTransferData ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN OUT VOID *Buffer, + IN UINT32 DataLen, + IN UINT16 BlockSize, + IN UINT16 Blocks, + IN BOOLEAN Read + ); + +EFI_STATUS +XenonInit ( + IN SD_MMC_HC_PRIVATE_DATA *Private + ); + +EFI_STATUS +SdCardSendStatus ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 Slot, + IN UINT16 Rca, + OUT UINT32 *DevStatus + );