On 14 September 2016 at 13:52, Ard Biesheuvel ard.biesheuvel@linaro.org wrote:
Change the PCIe bus range in the DSDT from [0x0 .. 0xf] to [0x00 .. 0x7f], which aligns it with the DT descripton. Also fix the I/O window: its range should be listed without taking the translation into account.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Platforms/AMD/Styx/AcpiTables/Dsdt.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl b/Platforms/AMD/Styx/ AcpiTables/Dsdt.asl index 1f0a96fb83ee..7190decbec6d 100644 --- a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl +++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl @@ -554,9 +554,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x0000, // Range Minimum
0x000F, // Range Maximum
0x007F, // Range Maximum 0x0000, // Translation Offset
0x0010, // Length
0x0080, // Length ) DWordMemory (ResourceProducer, PosDecode, MinFixed,
MaxFixed, NonCacheable, ReadWrite, 0x00000000, // Granularity @@ -637,8 +637,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) ) DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00000000, // Granularity
0xEFFF0000, // Range Minimum
0xEFFFFFFF, // Range Maximum
0x00000000, // Range Minimum
0x0000FFFF, // Range Maximum 0xEFFF0000, // Translation Address 0x00010000 // Length )
This looks correct to me, I have a feeling we did similar to Juno as well in the past.
Acked-by: Graeme Gregory graeme.gregory@linaro.org
Thanks