On 7 April 2015 at 15:22, fu.wei@linaro.org wrote:

From: Fu Wei fu.wei@linaro.org

Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei fu.wei@linaro.org

---

.../AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 54 +++++++++++++++++----- 1 file changed, 42 insertions(+), 12 deletions(-)

diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..8adf7b6 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -36,16 +36,16 @@ */

[0004] Signature : "GTDT" -[0004] Table Length : 00000050 +[0004] Table Length : 000000D8 [0001] Revision : 02 [0001] Checksum : F1 [0006] Oem ID : "LINARO" [0008] Oem Table ID : "RTSMVEV8" -[0004] Oem Revision : 00000001 +[0004] Oem Revision : 00000002 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20110623

-[0008] Counter Block Address : 0000000000000000 +[0008] Counter Block Address : 000000002a430000 [0004] Reserved : 00000000

/* In RTSM model's dts file, the last cell of interrupts @@ -83,34 +83,64 @@ Always-on : 0

/* The 64-bit physical address at which the Counter Read block is located */ -[0008] CntReadBase Physical address : 0000000000000000 +[0008] CntReadBase Physical address : 000000002a800000

-[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Count : 00000002 +[0004] Platform Timer Offset : 00000060

/* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00 [0002] Length : 0064 [0001] Reserved : 000000 [0008] Block Address : 000000002a810000 -[0004] Timer Count : 00000001 -[0004] Timer Offset : 00000010 +[0004] Timer Count : 00000002 +[0004] Timer Offset : 00000014

-/* One frame is available */ +/* two frames is available */

/* Two frames are available */

[0001] Frame Number : 00 [0003] Reserved : 000000 [0008] Base Address : 000000002a820000 -[0008] EL0 Base Address : FFFFFFFFFFFFFFFF -[0004] Timer Interrupt : 00000029 /* 25+16 */ +[0008] EL0 Base Address : 000000002a820000 +[0004] Timer Interrupt : 00000039 /* 25+32 */ [0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */

•                         Trigger Mode : 1
  

•                             Polarity : 0
  

+/* No virtual timer */ +[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0

+[0004] Common Flags (decoded below) : 00000000

•                               Secure : 1
  

•                            Always On : 0
  

+[0001] Frame Number : 01 +[0003] Reserved : 000000 +[0008] Base Address : 000000002a830000 +[0008] EL0 Base Address : 000000002a830000 +[0004] Timer Interrupt : 0000003A /* 26+32 */ +[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */

•                         Trigger Mode : 1
  

•                             Polarity : 0
  

/* No virtual timer */ [0004] Virtual Timer Interrupt : 00000000 [0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0

[0004] Common Flags (decoded below) : 00000000

•                               Secure : 0
  

•                               Secure : 1
                             Always On : 0
  
  

+/* one EL2 SBSA Generic Watchdog timer is available */

/* One ....

+[0001] Subtable Type : 01 [SBSA Generic Watchdog] +[0001] Length : 1C +[0002] Reserved : 0000 +[0008] Refresh Frame Address : 000000002a450000 +[0008] Control Frame Address : 000000002a440000 +[0004] Timer Interrupt : 0000003B /* 27+32 */ +[0004] Timer Flags (decoded below) : 00000001

•                         Trigger Mode : 1
  

•                             Polarity : 0
  

•                               Secure : 0
  

Minor nits otherwise looks good to me!

Graeme