From: huangming huangming23@huawei.com

Io BAR should be based IoBase and Mem BAR should be based PciRegionBase.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com Change-Id: I23f987b24e284fc2e2c3c3270b32acd80052b284 --- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 29 ++++++++++++++-------- .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 +++++++++-- 2 files changed, 31 insertions(+), 13 deletions(-)

diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index a970da6..6ecc1e5 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -1410,9 +1410,8 @@ SetResource( Ptr->ResType = 1; Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE Device Iobar address should be based on IoBase */ + Ptr->AddrRangeMin = RootBridgeInstance->IoBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1429,9 +1428,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > 0xFFFFFFFF) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1448,9 +1451,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > 0xFFFFFFFF) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1467,9 +1474,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFFFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1486,9 +1493,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFFFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..8dfb4b9 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); for (Index = 0; Index < TypeMax; Index++) { if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { - Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; + switch (Index) { + case TypeIo: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase; + break; + case TypeBus: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; + break; + default: + /* PCIE Device bar address should be base on PciRegionBase */ + Configuration.SpaceDesp[Index].AddrRangeMin = (PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase) + + (PrivateData->PciRegionBase & 0xFFFFFFFFFFFFFFFF); + } + Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; } }

From: Chenhui Sun sunchenhui@huawei.com

The Hisilicon SoC uncore PMU devices like L3 cache, MN etc are probed by djtag. The djtag will have _HID and L3 cache and MN will use _ADR and _CID to identity the hardware version.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Anurup M anurup.m@huawei.com --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl | 204 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 2 + 2 files changed, 206 insertions(+) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl

diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl new file mode 100644 index 0000000..6d07475 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl @@ -0,0 +1,204 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2017, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2017, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2017, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) { + // Djtag for CPU die #1 (scl #1) + Device (DJT0) { + Name (_HID, "HISI0201") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40010000, // Min Base Address + 0x4001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01} + } + }) + + // L3C Bank 0 for SCL #1 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x02}}, + } + }) + } + + // L3C Bank 1 for SCL #1 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x04}}, + } + }) + } + + // L3C Bank 2 for SCL #1 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #1 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x08}}, + } + }) + } + + // MN1 for SCL #1 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0221") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0xb}, + } + }) + } + } + + // Djtag for CPU die #2 (scl #2) + Device (DJT1) { + Name (_HID, "HISI0201") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x60010000, // Min Base Address + 0x6001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + } + }) + + // L3C Bank 0 for SCL #2 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x02}}, + } + }) + } + + // L3C Bank 1 for SCL #2 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x04}}, + } + }) + } + + // L3C Bank 2 for SCL #2 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #2 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x08}}, + } + }) + } + + // MN1 for SCL #2 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0221") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0xb}, + } + }) + } + } +} + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl index 4185f80..af80eb6 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -26,4 +26,6 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP06 ", EFI_ACPI_ARM_O include ("D03Hns.asl") include ("D03Sas.asl") include ("D03Pci.asl") + include ("Apei.asl") + include ("D03UncorePmu.asl") }

From: Chenhui Sun sunchenhui@huawei.com

Use _HID of HISI0231 for DDRC uncore PMU in hi1612. Every CPU die support 2 DDRC channels and each DDRC channel will be represented as a device with _HID and _UID. The device will also support _STA method.

Signed-off-by: Anurup M anurup.m@huawei.com --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl | 137 ++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-)

diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl index 6d07475..96aaaa5 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl @@ -200,5 +200,140 @@ Scope(_SB) { }) } } -}

+ // DDRC Channel 0 for CPU die #1 (scl #1) + Device (DDR0) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 0) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40348000, // Min Base Address + 0x40348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #1 (scl #1) + Device (DDR1) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40358000, // Min Base Address + 0x40358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 0 for CPU die #2 (scl #2) + Device (DDR2) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 2) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x60348000, // Min Base Address + 0x60348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #2 (scl #2) + Device (DDR3) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 3) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x60358000, // Min Base Address + 0x60358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } +}

From: huangming huangming23@huawei.com

On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are 0x20000000 and 0x30000000 based. These addresses overlap with the DDR memory range 0-1G. In this situation, on the inbound direction, our pcie will drop the DDR address access that are located in the pci range window and lead to a dataflow error.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 ++++---- Platforms/Hisilicon/D05/D05.dsc | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 79267e5..55c7f50 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -646,10 +646,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x20000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x65000000000, // Translate - 0xd0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, @@ -766,10 +766,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x30000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x75000000000, // Translate - 0xc0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 2fa0508..ffa1897 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -328,12 +328,12 @@ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 @@ -351,9 +351,9 @@ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000 gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000 gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000

From: Chenhui Sun sunchenhui@huawei.com

Change-Id: Icf98e5cbf43c837e634fb37407da179d060be692 Signed-off-by: Chenhui Sun sunchenhui@huawei.com --- .../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 2 + Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc | 86 ++++++++++++++++++++++ Platforms/Hisilicon/D05/D05.dsc | 2 + 3 files changed, 90 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf index 5e8f14d..9876a50 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf @@ -36,6 +36,7 @@ D05Slit.aslc D05Srat.aslc D05Spcr.aslc + Dbg2.aslc

[Packages] ArmPkg/ArmPkg.dec @@ -55,5 +56,6 @@ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc new file mode 100644 index 0000000..fb55a07 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2017 Hisilicon Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * +*/ + +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/DebugPort2Table.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include "Hi1616Platform.h" + +#define NUMBER_DEBUG_DEVICE_INFO 1 +#define NUMBER_OF_GENERIC_ADDRESS 1 +#define NAMESPACE_STRING_SIZE 8 +#define UART_LENGTH 0x1000 + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; + UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; + CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; +} EFI_ACPI_DBG2_DDI_STRUCT; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc; + EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO]; +} EFI_ACPI_DEBUG_PORT_2_TABLE; + +#pragma pack() + +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { + { + ARM_ACPI_HEADER( + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DEBUG_PORT_2_TABLE, + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION + ), + OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi), + NUMBER_DEBUG_DEVICE_INFO + }, + { + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof(EFI_ACPI_DBG2_DDI_STRUCT), + NUMBER_OF_GENERIC_ADDRESS, + NAMESPACE_STRING_SIZE, + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString), + 0, //OemDataLength + 0, //OemDataOffset + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address), + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize), + }, + { + { + EFI_ACPI_6_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_1_BYTE, + FixedPcdGet64 (PcdSerialDbgRegisterBase) + } + }, + { + UART_LENGTH + }, + "COM1" + } + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index ffa1897..8191459 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -179,6 +179,8 @@ # use the TTY terminal type (which has a working backspace) gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4

+ ## Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0xD00C0000

gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000

From: Chenhui Sun chenhui.sun@linaro.org

This is a temporary program, need continue to investigate the root cause.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 8dfb4b9..2effd7c 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -1770,6 +1770,13 @@ RootBridgeIoPciRead ( return EFI_INVALID_PARAMETER; }

+ if ((EfiPciAddress->Bus == 0x81) && (PrivateData->MemBase == 0xAA000000) && (EfiPciAddress->Device > 0)) { + return EFI_NOT_FOUND; + } + if ((EfiPciAddress->Bus == 0x91) && (EfiPciAddress->Device > 0)) { + return EFI_NOT_FOUND; + } + // The UEFI PCI enumerator scans for devices at all possible addresses, // and ignores some PCI rules - this results in some hardware being // detected multiple times. We work around this by faking absent

From: Ming Huang waip23@foxmail.com

Add APEI driver

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com --- Chips/Hisilicon/HisiPkg.dec | 16 +++++++++++++ .../Binary/D03/Drivers/Apei/AcpiApei.depex | Bin 0 -> 54 bytes .../Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.efi | Bin 0 -> 9408 bytes .../Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf | 26 +++++++++++++++++++++ Platforms/Hisilicon/D03/D03.fdf | 1 + 5 files changed, 43 insertions(+) create mode 100644 Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.depex create mode 100644 Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.efi create mode 100644 Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf

diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 2c02e14..023d784 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -21,6 +21,9 @@

[Includes] Include + Hi1610/Hi1610AcpiTables/ + Hi1616/D05AcpiTables/ + Pv660/Pv660AcpiTables/

[Ppis] gIpmiInterfacePpiGuid = {0x28ae4d88, 0xb658, 0x46b9, {0xa0, 0xe7, 0xd4, 0x95, 0xe2, 0xe8, 0x97, 0xf}} @@ -37,12 +40,25 @@ gBmcInfoProtocolGuid = {0x43fa6ffd, 0x35e4, 0x479e, {0xab, 0xec, 0x5, 0x3, 0xf6, 0x48, 0x0, 0xf5}} gSataEnableFlagProtocolGuid = {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf, 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}} gPlatformSasProtocolGuid = {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}} + gEfiApeiBertProtocolGuid = {0x40e98200, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}} + gEfiApeiHestProtocolGuid = { 0xb3fa54ee, 0x3729, 0x4942, { 0xb5, 0x36, 0x7e, 0xa3, 0xe0, 0x5e, 0xa, 0x8a }}

[Guids] gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}}

gHisiEfiMemoryMapGuid = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}} gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}} + # + # APEI Support + # + gEfiCperArmProcessorSectionTypeGuid = { 0xe19e3d16, 0xbc11, 0x11e4, { 0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0 }} + gEfiCperFirmwareErrorSectionTypeGuid = { 0x81212a96, 0x09ed, 0x4996, { 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed }} + gEfiCperPciBusSectionTypeGuid = { 0xc5753963, 0x3b84, 0x4095, { 0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd }} + gEfiCperPciDevSectionTypeGuid = { 0xeb5e4685, 0xca66, 0x4769, { 0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26 }} + gEfiCperPcieSectionTypeGuid = { 0xd995e954, 0xbbc1, 0x430f, { 0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35 }} + gEfiCperPlatformMemory2SectionTypeGuid = { 0x61EC04FC, 0x48E6, 0xD813, { 0x25, 0xC9, 0x8D, 0xAA, 0x44, 0x75, 0x0B, 0x12 }} + gEfiCperPlatformMemorySectionTypeGuid = { 0xa5bc1114, 0x6f64, 0x4ede, { 0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1 }} + gEfiCperProcessorGenericSectionTypeGuid = { 0x9876ccad, 0x47b4, 0x4bdb, { 0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb }}

[LibraryClasses] PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.depex b/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.depex new file mode 100644 index 0000000000000000000000000000000000000000..163dbbe18c94d23e0100234e66f0f561bc7c891e GIT binary patch literal 54 zcmV-60LlLX-D}|g2Vtg0d$L-be#IwT0*(lm>)+4DNxn<j2BoqNh648RqZ3Ld@ILb3 M-o+9$FEj%K2<b%`c>n+a

literal 0 HcmV?d00001

diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.efi new file mode 100644 index 0000000000000000000000000000000000000000..6358de232ab07f25291a23aab918e48a418e1fb8 GIT binary patch literal 9408 zcmcgy4^&jwng8B<0|F8q1k__lcpw@}I6{@EBq(nNQP~*d0@?P|L<Z5UG$#JV)%6b# zw9$yQjvA91n+zHg-)yv2F>$tb9Za*ERCjY6#iX028N_6hHE9HOWn9bb?|Xk>U`1QI zXWu#FefRtB{qFC6_xpDrKK28;>qouoncWj-77@+$O5Fs!U8d30UnG)K@QXHBD*6h3 z)+6JEf4v`nM)$b>y_tRV?S0U1MOIlp82;fzfcJm)j9xZx#WG0aJ@Y=THgW-($TfOy z#j*+>2feuN?`|W<DS$V6$-D&%D-Em`W^N-NjB`fz@8&(cj?P>uC9ShRg|15EeVk~= z6|_gF<DH5)!JbA+C@3X)r-B}o61|=MmC%(^MZ-L|Un)Nze%F}KbNuHCN1^zxtrE1W zlHgT|a?@fIUjflGg%XwV{1(W<ws$Da`q(^|K)Jzaf#-!PJ|Vj_T?t*-OKu+PqJs0m zAxfy_M%XT75pWpuM_~Rntapt%-nM9|puq~09+K2RGF@&DO37Zvd2N+L14aWY_R9O@ z{ayh+-tTD}?ciSvWb;1%GvYlys+*pPcjoiBNF7v0Q4;Hc*CtW}x=z*!x=zQEU}s%0 zR+p%R1n?z~5(?LdTDV5S&xT)=CZ8qy$(v;7{i@iLM^ppwqIQ^QQslfj|4nw~Lt|X9 zGyD$ocHDr@WXO(H0~de~7)n@<J`XghQ3<ISCz^DUA=`DRJ(x&3Jvan<#aRy1_m}J~ z(a$;AyG)`T1tRVEN}wIQuP$A#6Lej+Vox%#P?8c#&!<v>ww6=_FVkKB)|0-?q<j9g zC;hNV51#Hx|Inn%z35+C@=x^~A1fH^dVWLp5x~NjCZ`yfE=W<C85aM8p7W-HuG{}A z(wf>yxApDsqn)6HWazLWTJf=c9e^%eBPq}GE!kV4E4I~|&8Z!8z_;O@Z9>KPE310> z1>|0V?YXwx-$ArBPz~FveUI#N5{1w&ku%6g(P(Yt^Zx<ZAj@%r?6%jH&`FHrwI%4D zWw-7ncLV$Y=NKT^#}6S(Uk~#AQu+Bb>{}!yuLV9=Ck!1whhoM%DRoQ?bmpY{#vt4z zog_Qx1UijDhywk7Zu10ER;K4pKI^nmf+HhktU$D~%a%?5Zjr=H_Hnl7R@ltNaQLO_ z0gA6Cntat_a(!b7xohGG`bzRP{F3Y<Fg^{v(NML-Gn#y^L5fctss=nG$tNqImC(vo z__n7+aJNX3cNXgy^4MRAYzeLb(2Z$#UH;n(ODAmj+AQ`j$?FH6<tCox;^6vo5qQ#k z1|BEliBe1aCY~0=2)~KP4?KI~6rUe>CYV?n(C<uCa8?3Rk)UI`HjD8Y{?HdLOGmHV zMn}S71JiwsDK0`saeeD(P^69&@lVo`g=NKUurwSru-t&ZQ+x!L_`b1xi?LnjrT%$X zp12Jb$36qgM~r1y1eRfaV>um(MfuZg$I{D~+hD19-N4ewSYjivAg=ah$66#7xevWa zMt-n->iQ~CV>^BcF{?F|LiYeuU$)$|+rab_taI(Tlv2+gO0eu%j6(j2u;<oPCFGnr zzMgHGeXP#Jc72soBae`fOv(MLBm9hQJ1iOT-OB40MoV8`boTA{6)zju=Ci(R5&E+A zt*@sd^`#m<*4w{GK+F^Nw<Es!DpJ%E?mI}xWEx_XkC5~A_Z&nM^i^|w8gd@@IX;F9 zg)_Vd&ixhd8nONebjh*)s2?#IF_uOncOsq%qtyV%-fUoNEfm}?#QvJi_jhpI`xIy6 zLX75EZN-0%V^$7GL~OYFE3$i#b6cQGn+^5MS)-n59WJ;zmXp}=PH?yqY8drG3Gb<? zSX)v~!ZR&IWwn?m6NPGzlb!Q6*I$B-LQA6&UrVUX@yBpkS1txNeQ#!5Y&7R^jkEn9 zjk@3h_8}xeKW6@CncU~Pz=e0@6TM!j;P+@XAo~TkJQVArKl~8JzGl=LJhmlV8$g|< z&*OX~#84;|*iz&1vr{N-8_wTP?sU{@qKq~lt%7zsS{K^YXjQbE(FW1(M(ZIrYUPmp zB!$x7qL6_2Eaa09xB?aJVLRu#pW__5YA!S1S$SJHYMf>1E8TgUrkLkA#W=@bp@!iz z^!(z_$ls_HiPi_MAct?j`ezS84<hI7^?`NhH~pM#26{s5Ovf3q{uG%)4(ufzJO_B` z&}DiCh2~(M*uE~1J_`HH!8@raiPi_wp))xb<79FxFG6>$1BKk;YP2r2&{MjKb~joN zTIeU;kM=m)AllPtNpOq5Ln{kzAqD!&!Y?1c=~(A$&=tX*=E9hppv4QJ)=F}x{a1G# z@qO&2N8N&bTlaw$<a<RUdm{F?47HAWlH94X(l$+`GN!W+EEALJCD;ku4(EOs?AtXG zW20%M3v<X%3G7o$Bh(i-2R*NIy)3hzqRwS|=JV~kQ}n_hBPVoWINXha>5&-f5dUt8 z;m}`>ff^z(T<FHY^hgY1zdkSo?*aqzgcY-zerDMDIWuN8?=oW6cGz77^sLv4rk%UM zYeno~TpYJ*F~*8j9G^G_CH>ThFD>vVJw|OeV^k~YF-jE>qwZBgg0@kQQ5BoKdW@<- zjB0>98NP4Dq^8K2gmv|pWS$}8=X(~gtW3?I#Z5LU^XxQqSq<DCQP6GbecTV3&X~EL zWSio<BH!c07&Tzol>k5Sz_w(J^9+EE%kTsEnrDC#s+$D61C4n^Vm<q(Zi8IA-NFW= zOdI4{*kj(gx?<}(qpsHD401+~eT*{p;o2Ipk0ssvVEV20QP;nFA5B~CVjqkCl6?qg zf)D8TjzH(V#vPbzj>LMhU#}Fk!JEkb80^O{8u7jP1uK6fdj;Cql|NiKd+u}o@ZjCb zAB}jwP>KBJB)7+uQH%XbGM|N!V|cDk!`xtY_gr13iuG{jewGP8*3TR7j_;ZGp*6S< z4Hw+jeTe5At1;%VtQKjg*U~Tdzb7D%Y*g}gifT!kJ$1|w75AKtls7nod@ANPV?CVF zVHH?;Jlk}VV(ZAo-E19lyhRh^l~8&->G7TA57+H-sPSzA^LP!G&1<l1UZXZz&)bJ< zw@^oyT;$YeO}SiC2$1W+nw;nG^&`{}G;-Zl+`l{Fce)*-9=l%Y#J3j1r+92D?qR4E zF8Seyw)t}=IBn#vBwPPV)Q&g8;UPgu%GCX@5Z^i^oHMT}(W9Lb;%lK{(|kv-BWg^A z90hV_!~QYP%kyMXLmBX$DE!J5YKujzFIR=OY0*?xY@;(HQxvVrmNR~HZjGkVsBxn* z9NMO=wOUMupn0<<Y0)X9y_H*_v8+^CYA%<ltrcsGBqg*#E$_fRH1wvL+F|i=Cmjc# zZ-c-57<j%n{i(;8CkoV9eA96jyu1yU%O{MQUo`>zyqNjlnegW2)CtynUOzL-sb%FB zYFqNxYU|@`bPS9qE=$znb0zIy{v_@7cmq>xys}ODdiA!fTt!Qx*i%l5tsj}<z&O%I zWjG<L5VC%)ITf+3N}#f*Qv{9q^D{)9|HCXvAG08Ly)ll2wl6!wWn1!BYdrS(lr{R; zjTvh-9=j>4Mq7|;1BQI<jg*Pn{)|b`lYvDd;S}q3j_SPOyc#Zh*G7%3ch>)2;A9=I zCkYs(Q_rW==z3+jo3hqun{#h!`*fbz_5yISuHQ&0!1^`%8a&RMHBle?R_<|qywk)w zI=>KD3a~GyK9+UJV>7c9tdXw`$d{l)Q9skTEb2N-USl$UGcj%JA7HES?Lee$S@Dv; z6(|pp9p4swT#q7e9DNe;g=-4VRj*>MFl}Q=i{M$Z8}FPWo&Z0IlIl|_>Czn7%wMDb zN8P4-esk09V;<RIyCDUwfHo}${xsKkXG}bXv9J$Zs3f}+_E(5lgm<@#3eGF|&K4dB z-yf)ibo^Gl$KJT+<L`r);X5Aq3D@>|jRgN$0bjA+c@5qV$G3LiOv^&7tLTNn)YX@~ z?{XtA{D&kWrzyURSfeR?Vi4E<pTqxx{T+w-EM2pWaj#M8rRZb0!wF=sv)An+MJ;KO zV!W+VKkxbn$?nHKB6ZJry7rFRf#W*YavbM5=3fT}|17d6K^NDsHonV-xE>ga`%~>W z)C!_-Nrb=GKCFb6uO0eIP#WS*qrvqL^Eo5F1o3T21#d8D{y2_boKMsM=TWW&zJ(6_ z5j7p(Cpms`JhSeV!GWnA(J6(REy<~g@%WZvQ#90q=f3La=t#du(Bvr6f>Nv=i`dTi zEROsQ*WUP!2^;c{AUmJO`#2k>MV^IampF@;7+0ijWYZ=%*K_SjtA$sL^TRzdrfC<y z{|Iyk&O08hp-W_lcyUHrN6pzd(3E)FjI^t3&-T;bV`ijXUUSxlce+TAvs@)!m|-KK zUd)e~Q2@W@nx+6T^a9SbfrgI5m{46r?5joW1I<@w#=KgrjeeekV#d`4Q&*VhIkAOu z#;f#Neg)z!+0=<Dy_(NF_DAmH+tdM-3JzE_j&Ioi!~(LlDWjAd_{LsVi&#;qp!QdU zGcKxo%Z2f2hzI+_;WCvbb<O{r9%<g!`M~&n@igd!ofg-^9$Z+%g*7TK{{1!=i3eOH z9bkEBWIIzyBI-A(dHAya&6R|^hAGoUgmH|kTQ-k7kwl9f5i%`#mBE$UB4rx#M933O zjQNl?v4_0p;dlQczc=i2tXn`)ms&f*WnUmi&7*$xyw?VjF72a{n>>gmz4zQIMR{u} z3VY~xX)pN3dj0CTzXv)&TYn7pd_hX}N_ItKyTIQvv;xRfX!4EVkk^K>zB$IA4z;tN z@g1cCn3fHo1l&V1xn>*z-*LrJLJR2WcxQU;Ky?uRy}}hw_GHZA7MA8aitjneG0ns9 zT{06fGIKD-z^@V-*2a`_e~>w!*BGe3CuRzGhrQ}?xOeReTQY1t_((HjRm@h8i(P*Q zq0C(P_ISupQ3I!;ZgNSD?Gsog_aUGAxy;9R9Mt5Q+|OaY-cQu~S?GhVk1sv9H82YO zvE*qd!~-7Bdsl>*@z_sW1N1$V`)19Z0GuB9=VE+Yx(c219EZ6s>p%sMWndiMW5&gz zg?$Iuk5Los2o7`{{$F><LaF()0!iQZXA$qLXV!%PzY9u&UMmqlCqcne_Mq`s!44=d z@;UO8FIRu`=*lS@_V54r_n+VMVA)qM{<i6t0}Bth8y`EBzwn_SO__b^>EBdMeS6Qy z=z2;Vxid4Z_M6z9#XA=Nc**W9Ro_f+&-=TNwx3Jb^)PLHprGk7s{2aGdU)5=UE7P+ zB+lIV)E~-j9Qn?8XYtW-Yxf3c$8FjY^U|fyKK$q6e|q${(fbY$c)l{P`n~m!yr`U5 z@y)-V4Sn!wQo`|la~J-8#<9vt>%LjN?iUA6FMqjl>L-uBJ$rE5_FrH5<fiTGiZ7-m zemvrXAA2WP_aF4>Gr@4biZ`aLI{bs(Yu|g|$%gOVJ8RC1frKpu<oTd#$s>a&zS@#- z{9?jx@5!k9o|<yV+Pkx;qzq?G0!=F}EtchJ#WQop$+FD+;u&SrGZK>Zckc7E0s)bq zt!BI5Z2e~YvDscW+ZZGdeny#XQSpqwy3=~h=La#FNW!@(WJ)6nhndK&@ur_@1mECx z^F<Vzk@I`=VPm)D+j_0vdw!I`hnRi}^DMKn+GqwCfltQ^lGP&D^x$)s9~~Fkn7;Ar z<6`f?x9g*b44p$StVyLyyvgluib_iFXb;x;=&~8;E%wLf!;jF5Z|TM0hQnenzO`?Q zFZI&DWe67E#sVYOw{~LjqYU}@H&$VuwZ7Hf?fF>p@%Ojeu8;fGZTY&5-v&SbKMT4I zKmHE<d+va5z#aI=L$_UjrY?Z!oY{U~pFs4oX?QLKb$+H5m6joA+%e9uKH%8``-ko$ zEGKgRPom$~V~n*-h&pjdJk;{FzNY<u(fOzv@cZ3x<2S?k-JHm^v*#~-c3$@UoSd=a zAIi-clf86d^^(eY+0V^;c479S>ZS9uoz+zf=4MaM8Cz;_N{XfzIZBJlrxq6G=4Cq^ zC56+*<z_#=Xx?)(7gQ{Jdf}31XFl_{*@g3~7A?)5R<*QhK~?3#=dvd+saig7$<k~` z<)W%=$D(=WKa-1`PfXQ`OdCCS!2%r{bjlfX>%o@~dJgVCc<A7<gZ_i>AJlm=Q3hT- Td-m@+wCC6!{~n#%<DdTlii>!3

literal 0 HcmV?d00001

diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf new file mode 100644 index 0000000..6e51a1d --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2017, Hisilicon Limited. All rights reserved. +# Copyright (c) 2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[defines] + INF_VERSION = 0x00010019 + BASE_NAME = AcpiApei + FILE_GUID = E4630F5E-EBC2-FD3a-86BB-3CFDC4398C5F + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + +[Binaries] + PE32|AcpiApei.efi|* + diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index ff65af3..6d21ffe 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -238,6 +238,7 @@ READ_LOCK_STATUS = TRUE INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf

+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf # #Network #

From: Chenhui Sun chenhui.sun@linaro.org

The PerTuning function is not stable, it will cause the 3008/3108 crash, remove this function first.

Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- Platforms/Hisilicon/D03/D03.dsc | 1 - 1 file changed, 1 deletion(-)

diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index ff8d613..8f5df1c 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -112,7 +112,6 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE

[PcdsFixedAtBuild.common] gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03"

From: huangming huangming23@huawei.com

modify processorFamily of type 4 to ProcessorFamilyIndicatorFamily2, indicator to obtain the processor family from the Processor Family 2 field.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com --- .../Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 61473e8..c9903ba 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -125,7 +125,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] = { }, 1, //Socket CentralProcessor, //ProcessorType - ProcessorFamilyOther, //ProcessorFamily + ProcessorFamilyIndicatorFamily2, //ProcessorFamily 2, //ProcessorManufacture { //ProcessorId { //Signature @@ -172,7 +172,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] = { }, 1, //Socket CentralProcessor, //ProcessorType - ProcessorFamilyOther, //ProcessorFamily + ProcessorFamilyIndicatorFamily2, //ProcessorFamily 2, //ProcessorManufacture { //ProcessorId { //Signature

From: huangming huangming23@huawei.com

Optimize pcie space for promoting usage rate.Change regions order of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion can satisfy the requirement of larger address alignment.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 16 +++++------ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 8 +++--- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 +++++++++++----------- Platforms/Hisilicon/D05/D05.dsc | 12 ++++---- .../D05/Library/PlatformPciLib/PlatformPciLib.c | 8 +++--- 5 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 9ab164f..494f3f1 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -130,9 +130,9 @@ [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 /* this is the map for PCIe2 in 1P NA */ -[0004] Input base : 00028000 +[0004] Input base : 0002f800 [0004] ID Count : 00000800 -[0004] Output Base : 00008000 +[0004] Output Base : 0000f800 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -214,9 +214,9 @@ [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 /* this is the map for PCIe1 in 1P NB */ -[0004] Input base : 00010000 +[0004] Input base : 00017800 [0004] ID Count : 00000800 -[0004] Output Base : 00000000 +[0004] Output Base : 00007800 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -550,9 +550,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002

-[0004] Input base : 00008000 +[0004] Input base : 0000f800 [0004] ID Count : 00000800 -[0004] Output Base : 00028000 +[0004] Output Base : 0002f800 [0004] Output Reference : 000000f4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -607,9 +607,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005

-[0004] Input base : 00000000 +[0004] Input base : 00007800 [0004] ID Count : 00000800 -[0004] Output Base : 00010000 +[0004] Output Base : 00017800 [0004] Output Reference : 000001e4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc index b47cfec..64807b1 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -57,8 +57,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0xa0000000, //Base Address 0x2, //Segment Group Number - 0x80, //Start Bus Number - 0x87, //End Bus Number + 0xF8, //Start Bus Number + 0xFF, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe0 @@ -73,8 +73,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0x8b0000000, //Base Address 0x5, //Segment Group Number - 0x0, //Start Bus Number - 0x7, //End Bus Number + 0x78, //Start Bus Number + 0x7F, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe2 diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 55c7f50..71a8f2d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -89,15 +89,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number + Name(_BBN, 0xF8) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x87, // AddressMaximum - Maximum Bus Number + 0xF8, // AddressMinimum - Minimum Bus Number + 0xFF, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -109,8 +109,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xa8800000, // Min Base Address - 0xaffeffff, // Max Base Address + 0xa8000000, // Min Base Address + 0xaf7effff, // Max Base Address 0x0, // Translate 0x77f0000 // Length ) @@ -123,7 +123,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0xafff0000, // Translate + 0xaf7f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -162,7 +162,7 @@ Scope(_SB) { Name (_HID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] + Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [bus f8-ff] }) Method (_STA, 0x0, NotSerialized) { @@ -274,15 +274,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 5) // Segment of this Root complex - Name(_BBN, 0x0) // Base Bus Number + Name(_BBN, 0x78) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x7, // AddressMaximum - Maximum Bus Number + 0x78, // AddressMinimum - Minimum Bus Number + 0x7f, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -294,8 +294,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xb0800000, // Min Base Address - 0xb7feffff, // Max Base Address + 0xb0000000, // Min Base Address + 0xb77effff, // Max Base Address 0x800000000, // Translate 0x77f0000 // Length ) @@ -308,7 +308,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0x8b7ff0000, // Translate + 0x8b77f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -575,7 +575,7 @@ Scope(_SB) 0x0, // Translate 0x800000 // Length ) - QwordMemory ( //ECAM space for [bus 0-7] + QwordMemory ( //ECAM space for [bus 78-7f] ResourceConsumer, PosDecode, MinFixed, @@ -583,8 +583,8 @@ Scope(_SB) NonCacheable, ReadWrite, 0x0, // Granularity - 0x8b0000000, // Min Base Address - 0x8b07fffff, // Max Base Address + 0x8b7800000, // Min Base Address + 0x8b7ffffff, // Max Base Address 0x0, // Translate 0x800000 // Length ) diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 4e4baeb..cb12879 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -314,13 +314,13 @@ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 @@ -345,10 +345,10 @@

gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 @@ -362,10 +362,10 @@

gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index 57283a1..ed6c4ac 100644 --- a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 2 */ { PCI_HB0RB2_ECAM_BASE, - 0x80, //BusBase - 0x87, //BusLimit + 0xF8, //BusBase + 0xFF, //BusLimit PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB2_IO_BASE), //IOBase @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 5 */ { PCI_HB0RB5_ECAM_BASE,//ecam - 0x0, //BusBase - 0x7, //BusLimit + 0x78, //BusBase + 0x7F, //BusLimit PCI_HB0RB5_CPUMEMREGIONBASE, //Membase PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB5_IO_BASE), //IoBase

From: huangming huangming23@huawei.com

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wangzhou wangzhou1@hisilicon.com --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index be47671..f62b4fc 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -220,8 +220,15 @@ [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 +/* this is the map for PCIe0 in 1P NB */ +[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0

-//234 +//248 /* 2P NA PCIe SMMU */ [0001] Type : 04 [0002] Length : 0050 @@ -581,7 +588,7 @@ [0004] Input base : 00008800 [0004] ID Count : 00000800 [0004] Output Base : 00008800 -[0004] Output Reference : 0000007c +[0004] Output Reference : 000001e4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -695,7 +702,7 @@ [0004] Input base : 00001000 [0004] ID Count : 00001000 [0004] Output Base : 00021000 -[0004] Output Reference : 00000234 +[0004] Output Reference : 00000248 [0004] Flags (decoded below) : 00000000 Single Mapping : 0

From: Ming Huang waip23@foxmail.com

1. Disable I2C0 device avoiding access conflict in OS; 2. Modify name of _HID for matching the string in OS driver;

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl index eb906ef..3cc60d1 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl @@ -18,26 +18,8 @@

Scope(_SB) { - Device(I2C0) { - Name(_HID, "APMC0D0F") - Name(_CID, "APMC0D0F") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI6") { 705 } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"clock-frequency", 100000}, - Package () {"i2c-sda-falling-time-ns", 913}, - Package () {"i2c-scl-falling-time-ns", 303}, - Package () {"i2c-sda-hold-time-ns", 0x9c2}, - } - }) - } - Device(I2C2) { - Name(_HID, "APMC0D0F") + Name(_HID, "HISI02A1") Name(_CID, "APMC0D0F") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xd0100000, 0x10000)

From: Ming Huang waip23@foxmail.com

1. Because Hi161x chip doesn't support "ARI Forwarding Enable" function, BIOS will enumerate 32 same devices (Device Number 0~31) when attach a Non-ARI capable device in the RP. Hi161x chip will not fix it, need BIOS patch. 2. Just enlarge iatu for those root port with ARI capable device attached, Non-ARI capable device's RP, keep iatu limitation. 3. Remove previous temporary solution as below commit id: "7d157da88852cc91df2b11b10ade2edbbfbe77da"

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jason zhang zhangjinsong2@huawei.com

Conflicts: Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c --- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 + .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 4 ++ .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 83 ++++++++++++++++++++-- 3 files changed, 81 insertions(+), 7 deletions(-)

diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index 6ecc1e5..5bc04a2 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -839,6 +839,7 @@ NotifyPhase(

case EfiPciHostBridgeEndEnumeration: PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); + EnlargeAtuConfig0 (This); break;

case EfiPciHostBridgeBeginBusAllocation: diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index cddda6b..925ed40 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -518,4 +518,8 @@ RootBridgeConstructor ( IN UINT32 Seg );

+VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ); #endif diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 2effd7c..b41dbe2 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -14,6 +14,7 @@ **/

#include "PciHostBridge.h" +#include <IndustryStandard/PciExpress30.h> #include <Library/DevicePathLib.h> #include <Library/DmaLib.h> #include <Library/PciExpressLib.h> @@ -1770,13 +1771,6 @@ RootBridgeIoPciRead ( return EFI_INVALID_PARAMETER; }

- if ((EfiPciAddress->Bus == 0x81) && (PrivateData->MemBase == 0xAA000000) && (EfiPciAddress->Device > 0)) { - return EFI_NOT_FOUND; - } - if ((EfiPciAddress->Bus == 0x91) && (EfiPciAddress->Device > 0)) { - return EFI_NOT_FOUND; - } - // The UEFI PCI enumerator scans for devices at all possible addresses, // and ignores some PCI rules - this results in some hardware being // detected multiple times. We work around this by faking absent @@ -2329,3 +2323,78 @@ RootBridgeIoConfiguration ( return EFI_SUCCESS; }

+BOOLEAN +PcieCheckAriFwdEn ( + UINTN PciBaseAddr + ) +{ + UINT8 PciPrimaryStatus; + UINT8 CapabilityOffset; + UINT8 CapId; + UINT8 TempData; + + PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET); + + if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { + CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET); + CapabilityOffset &= ~(BIT0 | BIT1); + + while ((CapabilityOffset != 0) && (CapabilityOffset != 0xff)) { + CapId = MmioRead8 (PciBaseAddr + CapabilityOffset); + if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) { + break; + } + CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1); + CapabilityOffset &= ~(BIT0 | BIT1); + } + } else { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + if ((CapabilityOffset == 0xff) || (CapabilityOffset == 0x0)) { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + TempData = MmioRead16 (PciBaseAddr + CapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); + TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; + + if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) { + return TRUE; + } else { + return FALSE; + } +} + +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + UINTN RbPciBase; + UINT64 MemLimit; + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n"); + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + PCIE_DEBUG ("HostBridge has data.\n"); + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + + RbPciBase = RootBridgeInstance->RbPciBar; + + // Those ARI FWD Enable Root Bridge, need enlarge iatu window. + if (PcieCheckAriFwdEn (RbPciBase)) { + MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam, RootBridgeInstance->BusBase + 2, 0, 0, 0) - 1; + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); + } + List = List->ForwardLink; + } +}

From: Ming Huang waip23@foxmail.com

1. Fix 1P NB PCIe SMMU Length bug. 2. Update PXM information according to Iort spec.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 73 +++++++++++++++--------- 1 file changed, 46 insertions(+), 27 deletions(-)

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index f62b4fc..1f6f313 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -112,16 +112,17 @@ //f4 /* 1P NA PCIe SMMU */ [0001] Type : 04 -[0002] Length : 0050 +[0002] Length : 0054 //length added 4 [0001] Revision : 00 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 0000003C +[0004] Mapping Offset : 00000040 //new spec define the length

[0008] Base Address : a0040000 -[0004] Flags (decoded below) : 00000001 +[0004] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0004] Reserved : 00000000 [0008] VATOS Address : 0 [0004] Model : 00000001 @@ -129,6 +130,9 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 00 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 /* this is the map for PCIe2 in 1P NA */ [0004] Input base : 0002f800 [0004] ID Count : 00000800 @@ -137,19 +141,20 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 0

-//144 +//148 /* 2P NB PCIe SMMU */ [0001] Type : 04 -[0002] Length : 0064 +[0002] Length : 0068 //length added 4 [0001] Revision : 00 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 0000003C +[0004] Mapping Offset : 00000040 //new spec define the length

[0008] Base Address : 700a0040000 -[0004] Flags (decoded below) : 00000001 +[0004] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0004] Reserved : 00000000 [0008] VATOS Address : 0 [0004] Model : 00000001 @@ -157,6 +162,9 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 03 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 /* this is the map for pcie0 in 2p nb */ [0004] Input base : 00002000 [0004] Id count : 00001000 @@ -172,18 +180,19 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 0

-//1a8 +//1b0 [088h 0136 1] Type : 04 -[089h 0137 2] Length : 003C +[089h 0137 2] Length : 0040 //length added 4 [08Bh 0139 1] Revision : 00 [08Ch 0140 4] Reserved : 00000000 [090h 0144 4] Mapping Count : 00000000 -[094h 0148 4] Mapping Offset : 0000003C +[094h 0148 4] Mapping Offset : 00000040 //new spec define the length

[098h 0152 8] Base Address : 00000000C0040000 -[0A0h 0160 4] Flags (decoded below) : 00000001 +[0A0h 0160 4] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0A4h 0164 4] Reserved : 00000000 [0A8h 0168 8] VATOS Address : 0000000000000000 [0B0h 0176 4] Model : 00000001 @@ -191,21 +200,24 @@ [0B8h 0184 4] PRI GSIV : 00000000 [0BCh 0188 4] GERR GSIV : 00000000 [0C0h 0192 4] Sync GSIV : 00000000 +[0001] Proximity domain: 00 +[0001] Reserved1: 00 +[0002] Reserved2: 0000

- -//1e4 +//1F0 /* 1P NB PCIe SMMU */ [0001] Type : 04 -[0002] Length : 0050 +[0002] Length : 0068 //length added 4 [0001] Revision : 00 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 0000003C +[0004] Mapping Offset : 00000040 //new spec define the length

[0008] Base Address : 8a0040000 -[0004] Flags (decoded below) : 00000001 +[0004] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0004] Reserved : 00000000 [0008] VATOS Address : 0 [0004] Model : 00000001 @@ -213,6 +225,9 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 01 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 /* this is the map for PCIe1 in 1P NB */ [0004] Input base : 00017800 [0004] ID Count : 00000800 @@ -228,19 +243,20 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 0

-//248 +//258 /* 2P NA PCIe SMMU */ [0001] Type : 04 -[0002] Length : 0050 +[0002] Length : 0054 //length added 4 [0001] Revision : 00 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 0000003C +[0004] Mapping Offset : 00000040 //new spec define the length

[0008] Base Address : 600a0040000 -[0004] Flags (decoded below) : 00000001 +[0004] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0004] Reserved : 00000000 [0008] VATOS Address : 0 [0004] Model : 00000001 @@ -248,6 +264,9 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 02 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 /* this is the map for PCIe2 in 2P NA */ [0004] Input base : 00021000 [0004] ID Count : 00001000 @@ -588,7 +607,7 @@ [0004] Input base : 00008800 [0004] ID Count : 00000800 [0004] Output Base : 00008800 -[0004] Output Reference : 000001e4 +[0004] Output Reference : 000001F0 [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -617,7 +636,7 @@ [0004] Input base : 00007800 [0004] ID Count : 00000800 [0004] Output Base : 00017800 -[0004] Output Reference : 000001e4 +[0004] Output Reference : 000001F0 [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -702,7 +721,7 @@ [0004] Input base : 00001000 [0004] ID Count : 00001000 [0004] Output Base : 00021000 -[0004] Output Reference : 00000248 +[0004] Output Reference : 00000258 [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -731,7 +750,7 @@ [0004] Input base : 00002000 [0004] ID Count : 00001000 [0004] Output Base : 00002000 -[0004] Output Reference : 00000144 +[0004] Output Reference : 00000148 [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -760,7 +779,7 @@ [0004] Input base : 00003000 [0004] ID Count : 00001000 [0004] Output Base : 00013000 -[0004] Output Reference : 00000144 +[0004] Output Reference : 00000148 [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -855,7 +874,7 @@ [38Ch 0908 4] Input base : 00000000 [390h 0912 4] ID Count : 00000001 [394h 0916 4] Output Base : 00040900 -[398h 0920 4] Output Reference : 000001a8 +[398h 0920 4] Output Reference : 000001b0 [39Ch 0924 4] Flags (decoded below) : 00000001 Single Mapping : 1

@@ -952,6 +971,6 @@ [44Ch 1100 4] Input base : 00000000 [450h 1104 4] ID Count : 00000001 [454h 1108 4] Output Base : 00000000 -[458h 1112 4] Output Reference : 000001a8 +[458h 1112 4] Output Reference : 000001b0 [45Ch 1116 4] Flags (decoded below) : 00000001 Single Mapping : 1

Signed-off-by: Chenhui Sun sunchenhui@huawei.com --- Platforms/Hisilicon/D03/D03.dsc | 1 + Platforms/Hisilicon/D03/D03.fdf | 1 + 2 files changed, 2 insertions(+)

diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 128eab9..d856e2b 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -479,6 +479,7 @@ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf

diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 6d21ffe..599043d 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -271,6 +271,7 @@ READ_LOCK_STATUS = TRUE # VGA Driver # INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/SasPlatform/SasPlatform.inf INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf

Add file D05IortSmmu.asl and Add 'OemConfig->Support Smmu' setup menu to support Smu enable or disable. Remove Smmu node from D05Iort.asl.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com --- .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 74 ++ .../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 5 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 345 +------- .../Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl | 976 +++++++++++++++++++++ 4 files changed, 1063 insertions(+), 337 deletions(-) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl

diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c index 7d06fcc..9266c4b 100644 --- a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c @@ -24,6 +24,76 @@ #define NODE_IN_SOCKET 2 #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET)

+#define FIELD_IORT_NODE_OFFSET 40 + +typedef enum { + NodeTypeIts = 0, + NodeTypeNameComponent, + NodeTypePciRC, + NodeTypeSmmuV1, + NodeTypeSmmuV3, + NodeTypePMCG +} IORT_NODE_TYPE; + +#pragma pack(1) +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 IdMapNumber; + UINT32 IdArrayOffset; +} IORT_NODE_HEAD; +#pragma pack() + +BOOLEAN +IsIortWithSmmu ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + UINT32 *NodeOffset; + UINT32 NextOffset; + IORT_NODE_HEAD *Node; + + NodeOffset = (UINT32 *)((UINT8 *)TableHeader + FIELD_IORT_NODE_OFFSET); + NextOffset = *NodeOffset; + + while (NextOffset < TableHeader->Length) { + Node = (IORT_NODE_HEAD *)((UINT8 *)TableHeader + NextOffset); + NextOffset += Node->Length; + + if ((Node->Type == NodeTypeSmmuV1) || (Node->Type == NodeTypeSmmuV3)) { + return TRUE; + } + } + + return FALSE; +} + +EFI_STATUS +SelectIort ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + EFI_STATUS Status; + BOOLEAN EnableSmmu; + + EnableSmmu = 0; + Status = EFI_SUCCESS; + if (IsIortWithSmmu(TableHeader)) { + if (!EnableSmmu) { + Status = EFI_ABORTED; + } + } else { + if (EnableSmmu) { + Status = EFI_ABORTED; + } + } + DEBUG((DEBUG_INFO, "SmmuEnable=%x, return %r for Iort table.\n", EnableSmmu, Status)); + + return Status; +} + STATIC VOID RemoveUnusedMemoryNode ( @@ -132,6 +202,10 @@ UpdateAcpiTable ( case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE: Status = UpdateSlit (TableHeader); break; + + case EFI_ACPI_6_1_IO_REMAPPING_TABLE_SIGNATURE: + Status = SelectIort(TableHeader); + break; } return Status; } diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf index 9876a50..f3dad78 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf @@ -33,10 +33,11 @@ MadtHi1616.aslc D05Mcfg.aslc D05Iort.asl + D05IortSmmu.asl D05Slit.aslc D05Srat.aslc D05Spcr.aslc - Dbg2.aslc + Dbg2.aslc

[Packages] ArmPkg/ArmPkg.dec @@ -56,6 +57,6 @@ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum - gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 1f6f313..9955f6d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -109,171 +109,7 @@ [0004] ItsCount : 00000001 [0004] Identifiers : 00000007

-//f4 -/* 1P NA PCIe SMMU */ -[0001] Type : 04 -[0002] Length : 0054 //length added 4 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000040 //new spec define the length - -[0008] Base Address : a0040000 -[0004] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000001 -[0004] Event Interrupt : 00000000 -[0004] PRI Interrupt : 00000000 -[0004] GERR Interrupt : 00000000 -[0004] Sync Interrupt : 00000000 -[0001] Proximity domain: 00 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 -/* this is the map for PCIe2 in 1P NA */ -[0004] Input base : 0002f800 -[0004] ID Count : 00000800 -[0004] Output Base : 0000f800 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -//148 -/* 2P NB PCIe SMMU */ -[0001] Type : 04 -[0002] Length : 0068 //length added 4 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000040 //new spec define the length - -[0008] Base Address : 700a0040000 -[0004] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000001 -[0004] Event Interrupt : 00000000 -[0004] PRI Interrupt : 00000000 -[0004] GERR Interrupt : 00000000 -[0004] Sync Interrupt : 00000000 -[0001] Proximity domain: 03 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 -/* this is the map for pcie0 in 2p nb */ -[0004] Input base : 00002000 -[0004] Id count : 00001000 -[0004] Output base : 00002000 -[0004] Output reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single mapping : 0 -/* this is the map for PCIe1 in 2P NB */ -[0004] Input base : 00013000 -[0004] ID Count : 00001000 -[0004] Output Base : 00003000 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0

-//1b0 -[088h 0136 1] Type : 04 -[089h 0137 2] Length : 0040 //length added 4 -[08Bh 0139 1] Revision : 00 -[08Ch 0140 4] Reserved : 00000000 -[090h 0144 4] Mapping Count : 00000000 -[094h 0148 4] Mapping Offset : 00000040 //new spec define the length - -[098h 0152 8] Base Address : 00000000C0040000 -[0A0h 0160 4] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0A4h 0164 4] Reserved : 00000000 -[0A8h 0168 8] VATOS Address : 0000000000000000 -[0B0h 0176 4] Model : 00000001 -[0B4h 0180 4] Event GSIV : 00000000 -[0B8h 0184 4] PRI GSIV : 00000000 -[0BCh 0188 4] GERR GSIV : 00000000 -[0C0h 0192 4] Sync GSIV : 00000000 -[0001] Proximity domain: 00 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 - -//1F0 -/* 1P NB PCIe SMMU */ -[0001] Type : 04 -[0002] Length : 0068 //length added 4 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000040 //new spec define the length - -[0008] Base Address : 8a0040000 -[0004] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000001 -[0004] Event Interrupt : 00000000 -[0004] PRI Interrupt : 00000000 -[0004] GERR Interrupt : 00000000 -[0004] Sync Interrupt : 00000000 -[0001] Proximity domain: 01 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 -/* this is the map for PCIe1 in 1P NB */ -[0004] Input base : 00017800 -[0004] ID Count : 00000800 -[0004] Output Base : 00007800 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 -/* this is the map for PCIe0 in 1P NB */ -[0004] Input base : 00008800 -[0004] ID Count : 00000800 -[0004] Output Base : 00008800 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -//258 -/* 2P NA PCIe SMMU */ -[0001] Type : 04 -[0002] Length : 0054 //length added 4 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000040 //new spec define the length - -[0008] Base Address : 600a0040000 -[0004] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000001 -[0004] Event Interrupt : 00000000 -[0004] PRI Interrupt : 00000000 -[0004] GERR Interrupt : 00000000 -[0004] Sync Interrupt : 00000000 -[0001] Proximity domain: 02 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 -/* this is the map for PCIe2 in 2P NA */ -[0004] Input base : 00021000 -[0004] ID Count : 00001000 -[0004] Output Base : 00001000 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0

/* mbi-gen peri b, named component */ [0001] Type : 01 @@ -578,8 +414,8 @@

[0004] Input base : 0000f800 [0004] ID Count : 00000800 -[0004] Output Base : 0002f800 -[0004] Output Reference : 000000f4 +[0004] Output Base : 0000f800 +[0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 /* 1P NB PCIe0 */ @@ -607,7 +443,7 @@ [0004] Input base : 00008800 [0004] ID Count : 00000800 [0004] Output Base : 00008800 -[0004] Output Reference : 000001F0 +[0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -635,8 +471,8 @@

[0004] Input base : 00007800 [0004] ID Count : 00000800 -[0004] Output Base : 00017800 -[0004] Output Reference : 000001F0 +[0004] Output Base : 00007800 +[0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -720,8 +556,8 @@

[0004] Input base : 00001000 [0004] ID Count : 00001000 -[0004] Output Base : 00021000 -[0004] Output Reference : 00000258 +[0004] Output Base : 00001000 +[0004] Output Reference : 000000c4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -750,7 +586,7 @@ [0004] Input base : 00002000 [0004] ID Count : 00001000 [0004] Output Base : 00002000 -[0004] Output Reference : 00000148 +[0004] Output Reference : 000000dc [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -778,8 +614,8 @@

[0004] Input base : 00003000 [0004] ID Count : 00001000 -[0004] Output Base : 00013000 -[0004] Output Reference : 00000148 +[0004] Output Base : 00003000 +[0004] Output Reference : 000000dc [0004] Flags (decoded below) : 00000000 Single Mapping : 0

@@ -813,164 +649,3 @@ [0004] Output Reference : 000000c4 [0004] Flags (decoded below) : 00000001 Single Mapping : 1 - -[320h 0800 1] Type : 01 -[321h 0801 2] Length : 0040 -[323h 0803 1] Revision : 00 -[324h 0804 4] Reserved : 00000000 -[328h 0808 4] Mapping Count : 00000001 -[32Ch 0812 4] Mapping Offset : 0000002C - -[330h 0816 4] Node Flags : 00000000 -[334h 0820 8] Memory Properties : [IORT Memory Access Properties] -[334h 0820 4] Cache Coherency : 00000000 -[338h 0824 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[339h 0825 2] Reserved : 0000 -[33Bh 0827 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[33Ch 0828 1] Memory Size Limit : 00 -[33Dh 0829 11] Device Name : "_SB_.USB0" -[348h 0840 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[34Ch 0844 4] Input base : 00000000 -[350h 0848 4] ID Count : 00000001 -[354h 0852 4] Output Base : 00040080 -[358h 0856 4] Output Reference : 000000F4 -[35Ch 0860 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -[360h 0864 1] Type : 01 -[361h 0865 2] Length : 0040 -[363h 0867 1] Revision : 00 -[364h 0868 4] Reserved : 00000000 -[368h 0872 4] Mapping Count : 00000001 -[36Ch 0876 4] Mapping Offset : 0000002C - -[370h 0880 4] Node Flags : 00000000 -[374h 0884 8] Memory Properties : [IORT Memory Access Properties] -[374h 0884 4] Cache Coherency : 00000000 -[378h 0888 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[379h 0889 2] Reserved : 0000 -[37Bh 0891 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[37Ch 0892 1] Memory Size Limit : 00 -[37Dh 0893 11] Device Name : "_SB_.SAS0" -[388h 0904 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 00 01 00 00 \ - 88 00 00 00 01 00 00 00 - -[38Ch 0908 4] Input base : 00000000 -[390h 0912 4] ID Count : 00000001 -[394h 0916 4] Output Base : 00040900 -[398h 0920 4] Output Reference : 000001b0 -[39Ch 0924 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -[3A0h 0928 1] Type : 01 -[3A1h 0929 2] Length : 0040 -[3A3h 0931 1] Revision : 00 -[3A4h 0932 4] Reserved : 00000000 -[3A8h 0936 4] Mapping Count : 00000001 -[3ACh 0940 4] Mapping Offset : 0000002C - -[3B0h 0944 4] Node Flags : 00000000 -[3B4h 0948 8] Memory Properties : [IORT Memory Access Properties] -[3B4h 0948 4] Cache Coherency : 00000000 -[3B8h 0952 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[3B9h 0953 2] Reserved : 0000 -[3BBh 0955 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[3BCh 0956 1] Memory Size Limit : 00 -[3BDh 0957 11] Device Name : "_SB_.SAS1" -[3C8h 0968 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 00 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[3CCh 0972 4] Input base : 00000000 -[3D0h 0976 4] ID Count : 00000001 -[3D4h 0980 4] Output Base : 00040000 -[3D8h 0984 4] Output Reference : 000000F4 -[3DCh 0988 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -[3E0h 0992 1] Type : 01 -[3E1h 0993 2] Length : 0040 -[3E3h 0995 1] Revision : 00 -[3E4h 0996 4] Reserved : 00000000 -[3E8h 1000 4] Mapping Count : 00000001 -[3ECh 1004 4] Mapping Offset : 0000002C - -[3F0h 1008 4] Node Flags : 00000000 -[3F4h 1012 8] Memory Properties : [IORT Memory Access Properties] -[3F4h 1012 4] Cache Coherency : 00000000 -[3F8h 1016 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[3F9h 1017 2] Reserved : 0000 -[3FBh 1019 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[3FCh 1020 1] Memory Size Limit : 00 -[3FDh 1021 11] Device Name : "_SB_.SAS2" -[408h 1032 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 40 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[40Ch 1036 4] Input base : 00000000 -[410h 1040 4] ID Count : 00000001 -[414h 1044 4] Output Base : 00040040 -[418h 1048 4] Output Reference : 000000F4 -[41Ch 1052 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/*HNS smmu*/ -[420h 1056 1] Type : 01 -[421h 1057 2] Length : 0040 -[423h 1059 1] Revision : 00 -[424h 1060 4] Reserved : 00000000 -[428h 1064 4] Mapping Count : 00000001 -[42Ch 1068 4] Mapping Offset : 0000002C - -[430h 1072 4] Node Flags : 00000000 -[434h 1076 8] Memory Properties : [IORT Memory Access Properties] -[434h 1076 4] Cache Coherency : 00000000 -[438h 1080 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[439h 1081 2] Reserved : 0000 -[43Bh 1083 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[43Ch 1084 1] Memory Size Limit : 00 -[43Dh 1085 11] Device Name : "_SB_.DSF0" -[448h 1096 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 \ - 94 01 00 00 01 00 00 00 - -[44Ch 1100 4] Input base : 00000000 -[450h 1104 4] ID Count : 00000001 -[454h 1108 4] Output Base : 00000000 -[458h 1112 4] Output Reference : 000001b0 -[45Ch 1116 4] Flags (decoded below) : 00000001 - Single Mapping : 1 diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl new file mode 100644 index 0000000..9ae7a43 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl @@ -0,0 +1,976 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20151124-64 + * Copyright (c) 2000 - 2017 Intel Corporation + * + * Template for [IORT] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 000002e4 +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HIP07 " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124 + +[0004] Node Count : 00000008 +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00 + +/* ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 +//4c +/* ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000001 +//64 +/* ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000002 +//7c +/* ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000003 +//94 +/*Sec CPU ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000004 +//ac +/* SEC CPU ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000005 +//c4 +/* SEC CPU ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000006 +//dc +/* SEC CPU ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000007 + +//f4 +/* 1P NA PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0054 //length added 4 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000040 //new spec define the length + +[0008] Base Address : a0040000 +[0004] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000001 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 00 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 +/* this is the map for PCIe2 in 1P NA */ +[0004] Input base : 0002f800 +[0004] ID Count : 00000800 +[0004] Output Base : 0000f800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//148 +/* 2P NB PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0068 //length added 4 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000040 //new spec define the length + +[0008] Base Address : 700a0040000 +[0004] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000001 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 03 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 +/* this is the map for pcie0 in 2p nb */ +[0004] Input base : 00002000 +[0004] Id count : 00001000 +[0004] Output base : 00002000 +[0004] Output reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single mapping : 0 +/* this is the map for PCIe1 in 2P NB */ +[0004] Input base : 00013000 +[0004] ID Count : 00001000 +[0004] Output Base : 00003000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//1b0 +[088h 0136 1] Type : 04 +[089h 0137 2] Length : 0040 //length added 4 +[08Bh 0139 1] Revision : 00 +[08Ch 0140 4] Reserved : 00000000 +[090h 0144 4] Mapping Count : 00000000 +[094h 0148 4] Mapping Offset : 00000040 //new spec define the length + +[098h 0152 8] Base Address : 00000000C0040000 +[0A0h 0160 4] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0A4h 0164 4] Reserved : 00000000 +[0A8h 0168 8] VATOS Address : 0000000000000000 +[0B0h 0176 4] Model : 00000001 +[0B4h 0180 4] Event GSIV : 00000000 +[0B8h 0184 4] PRI GSIV : 00000000 +[0BCh 0188 4] GERR GSIV : 00000000 +[0C0h 0192 4] Sync GSIV : 00000000 +[0001] Proximity domain: 00 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 + +//1F0 +/* 1P NB PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0068 //length added 4 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000040 //new spec define the length + +[0008] Base Address : 8a0040000 +[0004] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000001 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 01 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 +/* this is the map for PCIe1 in 1P NB */ +[0004] Input base : 00017800 +[0004] ID Count : 00000800 +[0004] Output Base : 00007800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* this is the map for PCIe0 in 1P NB */ +[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//258 +/* 2P NA PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0054 //length added 4 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000040 //new spec define the length + +[0008] Base Address : 600a0040000 +[0004] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000001 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 02 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 +/* this is the map for PCIe2 in 2P NA */ +[0004] Input base : 00021000 +[0004] ID Count : 00001000 +[0004] Output Base : 00001000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* mbi-gen peri b, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI0" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 000120c7 //device id +[0004] Output Reference : 0000004C +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI1" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040800 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI9" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen dsa a - usb named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI5" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040080 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI2" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040900 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI3" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040000 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI4" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040040 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 alg a, i2c 0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI6" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B0E //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 alg a, i2c 2 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI7" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B10 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/*1P NA PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002 + +[0004] Input base : 0000f800 +[0004] ID Count : 00000800 +[0004] Output Base : 0002f800 +[0004] Output Reference : 000000f4 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 1P NB PCIe0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000004 + +[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 000001F0 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 1P NB PCIe1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000005 + +[0004] Input base : 00007800 +[0004] ID Count : 00000800 +[0004] Output Base : 00017800 +[0004] Output Reference : 000001F0 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 1P NB PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000006 + +[0004] Input base : 0000c000 +[0004] ID Count : 00000800 +[0004] Output Base : 0000c000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 1P NB PCIe3 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000007 + +[0004] Input base : 00009000 +[0004] ID Count : 00000800 +[0004] Output Base : 00009000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 2P NA PCIe2*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000a + +[0004] Input base : 00001000 +[0004] ID Count : 00001000 +[0004] Output Base : 00021000 +[0004] Output Reference : 00000258 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 2P NB PCIe0*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000c + +[0004] Input base : 00002000 +[0004] ID Count : 00001000 +[0004] Output Base : 00002000 +[0004] Output Reference : 00000148 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + + /* 2P NB PCIe1*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000d + +[0004] Input base : 00003000 +[0004] ID Count : 00001000 +[0004] Output Base : 00013000 +[0004] Output Reference : 00000148 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* mbi-gen1 P1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI8" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00044800 //device id +[0004] Output Reference : 000000c4 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[320h 0800 1] Type : 01 +[321h 0801 2] Length : 0040 +[323h 0803 1] Revision : 00 +[324h 0804 4] Reserved : 00000000 +[328h 0808 4] Mapping Count : 00000001 +[32Ch 0812 4] Mapping Offset : 0000002C + +[330h 0816 4] Node Flags : 00000000 +[334h 0820 8] Memory Properties : [IORT Memory Access Properties] +[334h 0820 4] Cache Coherency : 00000000 +[338h 0824 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[339h 0825 2] Reserved : 0000 +[33Bh 0827 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[33Ch 0828 1] Memory Size Limit : 00 +[33Dh 0829 11] Device Name : "_SB_.USB0" +[348h 0840 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[34Ch 0844 4] Input base : 00000000 +[350h 0848 4] ID Count : 00000001 +[354h 0852 4] Output Base : 00040080 +[358h 0856 4] Output Reference : 000000F4 +[35Ch 0860 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[360h 0864 1] Type : 01 +[361h 0865 2] Length : 0040 +[363h 0867 1] Revision : 00 +[364h 0868 4] Reserved : 00000000 +[368h 0872 4] Mapping Count : 00000001 +[36Ch 0876 4] Mapping Offset : 0000002C + +[370h 0880 4] Node Flags : 00000000 +[374h 0884 8] Memory Properties : [IORT Memory Access Properties] +[374h 0884 4] Cache Coherency : 00000000 +[378h 0888 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[379h 0889 2] Reserved : 0000 +[37Bh 0891 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[37Ch 0892 1] Memory Size Limit : 00 +[37Dh 0893 11] Device Name : "_SB_.SAS0" +[388h 0904 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 01 00 00 \ + 88 00 00 00 01 00 00 00 + +[38Ch 0908 4] Input base : 00000000 +[390h 0912 4] ID Count : 00000001 +[394h 0916 4] Output Base : 00040900 +[398h 0920 4] Output Reference : 000001b0 +[39Ch 0924 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[3A0h 0928 1] Type : 01 +[3A1h 0929 2] Length : 0040 +[3A3h 0931 1] Revision : 00 +[3A4h 0932 4] Reserved : 00000000 +[3A8h 0936 4] Mapping Count : 00000001 +[3ACh 0940 4] Mapping Offset : 0000002C + +[3B0h 0944 4] Node Flags : 00000000 +[3B4h 0948 8] Memory Properties : [IORT Memory Access Properties] +[3B4h 0948 4] Cache Coherency : 00000000 +[3B8h 0952 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[3B9h 0953 2] Reserved : 0000 +[3BBh 0955 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[3BCh 0956 1] Memory Size Limit : 00 +[3BDh 0957 11] Device Name : "_SB_.SAS1" +[3C8h 0968 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[3CCh 0972 4] Input base : 00000000 +[3D0h 0976 4] ID Count : 00000001 +[3D4h 0980 4] Output Base : 00040000 +[3D8h 0984 4] Output Reference : 000000F4 +[3DCh 0988 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[3E0h 0992 1] Type : 01 +[3E1h 0993 2] Length : 0040 +[3E3h 0995 1] Revision : 00 +[3E4h 0996 4] Reserved : 00000000 +[3E8h 1000 4] Mapping Count : 00000001 +[3ECh 1004 4] Mapping Offset : 0000002C + +[3F0h 1008 4] Node Flags : 00000000 +[3F4h 1012 8] Memory Properties : [IORT Memory Access Properties] +[3F4h 1012 4] Cache Coherency : 00000000 +[3F8h 1016 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[3F9h 1017 2] Reserved : 0000 +[3FBh 1019 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[3FCh 1020 1] Memory Size Limit : 00 +[3FDh 1021 11] Device Name : "_SB_.SAS2" +[408h 1032 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 40 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[40Ch 1036 4] Input base : 00000000 +[410h 1040 4] ID Count : 00000001 +[414h 1044 4] Output Base : 00040040 +[418h 1048 4] Output Reference : 000000F4 +[41Ch 1052 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/*HNS smmu*/ +[420h 1056 1] Type : 01 +[421h 1057 2] Length : 0040 +[423h 1059 1] Revision : 00 +[424h 1060 4] Reserved : 00000000 +[428h 1064 4] Mapping Count : 00000001 +[42Ch 1068 4] Mapping Offset : 0000002C + +[430h 1072 4] Node Flags : 00000000 +[434h 1076 8] Memory Properties : [IORT Memory Access Properties] +[434h 1076 4] Cache Coherency : 00000000 +[438h 1080 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[439h 1081 2] Reserved : 0000 +[43Bh 1083 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[43Ch 1084 1] Memory Size Limit : 00 +[43Dh 1085 11] Device Name : "_SB_.DSF0" +[448h 1096 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 \ + 94 01 00 00 01 00 00 00 + +[44Ch 1100 4] Input base : 00000000 +[450h 1104 4] ID Count : 00000001 +[454h 1108 4] Output Base : 00000000 +[458h 1112 4] Output Reference : 000001b0 +[45Ch 1116 4] Flags (decoded below) : 00000001 + Single Mapping : 1