Hi Leif, Achin,
These are the OpenPlatformPkg parts of the RAS with SDEI demo on the FVP. There is no intention of upstreaming this, it's intended as a short-lived staging/topic branch, to be replaced by a proper version incorporating the MM work. This is just a bunch of hacks that let us work on the ATF<->Linux and MM stuff separately.
Unfortunately this is based on an old commit: 4e9cfc934508 ("Platforms/ARM: Juno - add Uhci/Xhci drivers"). due to a mixture of ignorance and laziness, (shuffle compiler versions and branches until you find a combination that builds).
MangleHEST? This is a short-lived efi-application that runs before the kernel to fixup the hard-coded HEST by allocating memory for the CPER records and re-writing the table. Obviously no real system should ever do this, this too will be replaced by a proper version that generates a correct HEST all in one go.
Thanks,
James
Ard Biesheuvel (1): Platforms/FVP: Fix MADT to run the Foundation model in GICv3 mode with 4 CPUs
James Morse (4): Platforms/FVP: Update FADT to ACPIv6 Platforms/FVP: Build MangleHEST, not LinuxLoader Platforms/FVP: Add SDEI and HEST ACPI tables Platforms/FVP: Correct PMU IRQ and GTDT timer offset
.../AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf | 2 + .../VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl | 124 ++++----------------- .../VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl | 6 +- .../VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 2 +- .../VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl | 48 ++++++++ .../VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl | 18 +++ Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 2 + Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 2 +- Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 2 +- 9 files changed, 100 insertions(+), 106 deletions(-) create mode 100644 Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl create mode 100644 Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl
From: Ard Biesheuvel ard.biesheuvel@linaro.org
This upgrades the MADT table so that it exposes the GIC as a v3. The virtual base address and interrupt, and the hypervisor base address are corrected as well.
Since the Foundation model has 4 cores at the most, and since refactoring this code to update the ACPI tables dynamically based on the actual core count is more trouble that its worth, remove the second cluster while we are at it.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org Signed-off-by: James Morse james.morse@arm.com --- .../VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl | 116 ++++----------------- 1 file changed, 19 insertions(+), 97 deletions(-)
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl index 9cd3031..7d91562 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl @@ -61,9 +61,9 @@ [0004] Performance Interrupt : 00000000 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 /* armv8 FVP Base GIC address */ -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 +[0008] Virtual GIC Base Address : 000000002C02F000 +[0008] Hypervisor GIC Base Address : 000000002C010000 +[0004] Virtual GIC Interrupt : 00000019 [0008] Redistributor Base Address : 0 [0008] ARM MPIDR : 0 [0001] Efficiency Class : 00 @@ -82,9 +82,9 @@ [0004] Performance Interrupt : 00000000 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 +[0008] Virtual GIC Base Address : 000000002C02F000 +[0008] Hypervisor GIC Base Address : 000000002C010000 +[0004] Virtual GIC Interrupt : 00000019 [0008] Redistributor Base Address : 0 [0008] ARM MPIDR : 0000000000000001 [0001] Efficiency Class : 00 @@ -103,9 +103,9 @@ [0004] Performance Interrupt : 00000000 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 +[0008] Virtual GIC Base Address : 000000002C02F000 +[0008] Hypervisor GIC Base Address : 000000002C010000 +[0004] Virtual GIC Interrupt : 00000019 [0008] Redistributor Base Address : 0 [0008] ARM MPIDR : 0000000000000002 [0001] Efficiency Class : 00 @@ -124,103 +124,25 @@ [0004] Performance Interrupt : 00000000 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 +[0008] Virtual GIC Base Address : 000000002C02F000 +[0008] Hypervisor GIC Base Address : 000000002C010000 +[0004] Virtual GIC Interrupt : 00000019 [0008] Redistributor Base Address : 0 [0008] ARM MPIDR : 0000000000000003 [0001] Efficiency Class : 00 [0003] Reserved : 000000
-[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 50 -[0002] Reserved : 0000 -[0004] CPU Interface Number : 00000004 -[0004] Processor UID : 00000004 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Performance Interrupt Trigger Mode : 0 - Virtual GIC Interrupt Trigger Mode : 0 -[0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000000000000000 -[0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 -[0008] Redistributor Base Address : 0 -[0008] ARM MPIDR : 0000000000000100 -[0001] Efficiency Class : 00 -[0003] Reserved : 000000 - -[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 50 -[0002] Reserved : 0000 -[0004] CPU Interface Number : 00000005 -[0004] Processor UID : 00000005 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Performance Interrupt Trigger Mode : 0 - Virtual GIC Interrupt Trigger Mode : 0 -[0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000000000000000 -[0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 -[0008] Redistributor Base Address : 0 -[0008] ARM MPIDR : 0000000000000101 -[0001] Efficiency Class : 00 -[0003] Reserved : 000000 - -[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 50 -[0002] Reserved : 0000 -[0004] CPU Interface Number : 00000006 -[0004] Processor UID : 00000006 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Performance Interrupt Trigger Mode : 0 - Virtual GIC Interrupt Trigger Mode : 0 -[0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000000000000000 -[0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 -[0008] Redistributor Base Address : 0 -[0008] ARM MPIDR : 0000000000000102 -[0001] Efficiency Class : 00 -[0003] Reserved : 000000 - -[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 50 -[0002] Reserved : 0000 -[0004] CPU Interface Number : 00000007 -[0004] Processor UID : 00000007 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Performance Interrupt Trigger Mode : 0 - Virtual GIC Interrupt Trigger Mode : 0 -[0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000000000000000 -[0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 -[0008] Redistributor Base Address : 0 -[0008] ARM MPIDR : 0000000000000103 -[0001] Efficiency Class : 00 -[0003] Reserved : 000000 - [0001] Subtable Type : 0C [Generic Interrupt Distributor] [0001] Length : 18 [0002] Reserved : 0000 [0004] Local GIC Hardware ID : 00000000 [0008] Base Address : 000000002F000000 /* armv8 FVP Base GIC distributor base addr */ [0004] Interrupt Base : 00000000 -[0001] Version : 02 +[0001] Version : 03 [0003] Reserved : 000000 + +[0001] Subtable Type : 0E [Generic Interrupt Redistributor] +[0001] Length : 10 +[0002] Reserved : 0000 +[0008] Base Address : 000000002F100000 /* armv8 FVP Base GIC redistributor base addr */ +[0004] Region Size : 00200000
Linux enables some workarounds based on the version of the FADT. These prevent GICv3 in the FVP from working properly.
Update the FADT, this is just a case of adding the new fields and bumping the revision number.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: James Morse james.morse@arm.com --- Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl index c288ae2..46cfa62 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl @@ -35,8 +35,8 @@
[0004] Signature : "FACP" [0004] Table Length : 0000010C -[0001] Revision : 05 -[0001] Checksum : 18 +[0001] Revision : 06 +[0001] Checksum : 00 [0006] Oem ID : "LINARO" [0008] Oem Table ID : "RTSMVEV8" [0004] Oem Revision : 00000000 @@ -195,3 +195,5 @@ [0001] Encoded Access Width : 01 [Byte Access:8] [0008] Address : 0000000000000000
+[0008] Hypervisor ID : 0000000000000000 +
Make the FVP platform build MangleHEST.
LinuxLoader caused some build warnings/errors, turn it off.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: James Morse james.morse@arm.com --- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 2 ++ Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 2 +- Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index c0c80e2..51fd952 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -334,3 +334,5 @@ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf !endif + + MdeModulePkg/Application/MangleHEST/MangleHEST.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf index 9923081..e25d516 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf @@ -186,7 +186,7 @@ FvNameGuid = 87940482-fc81-41c3-87e6-399cf85ac8a0 !endif
# Legacy Linux Loader - INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf + #INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf
# FV Filesystem INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc index 61912ef..dea56e4 100644 --- a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc +++ b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc @@ -484,7 +484,7 @@ EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf
# Legacy Linux Loader - ArmPkg/Application/LinuxLoader/LinuxLoader.inf + #ArmPkg/Application/LinuxLoader/LinuxLoader.inf
# # UEFI application (Shell Embedded Boot Loader)
Add template tables for SDEI and HEST. The HEST contains a single GHES that uses SDEI, this will be rewritten at boot by MangleHEST.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: James Morse james.morse@arm.com --- .../AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf | 2 + .../VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl | 48 ++++++++++++++++++++++ .../VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl | 18 ++++++++ 3 files changed, 68 insertions(+) create mode 100644 Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl create mode 100644 Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf index ecb4ca6..3a37081 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf @@ -29,6 +29,8 @@ gtdt.asl dbg2.asl spcr.asl + sdei.asl + hest.asl
[Packages] MdePkg/MdePkg.dec diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl new file mode 100644 index 0000000..c16a295 --- /dev/null +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl @@ -0,0 +1,48 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20160930-64 + * Copyright (c) 2000 - 2016 Intel Corporation + * + * Template for [HEST] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "HEST" [Hardware Error Source Table] +[0004] Table Length : 00000000 +[0001] Revision : 01 +[0001] Checksum : 00 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Error Source Count : 00000001 + +[0002] Subtable Type : 0009 [Generic Hardware Error Source] +[0002] Source Id : 0001 +[0002] Related Source Id : FFFF +[0001] Reserved : 00 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Max Raw Data Length : 00001000 + +[0012] Error Status Address : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 0b [SDEI] +[0001] Notify Length : 1C +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000324 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000 + +[0004] Error Status Block Length : 00001000 diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl new file mode 100644 index 0000000..913cadd --- /dev/null +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl @@ -0,0 +1,18 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20160930-64 + * Copyright (c) 2000 - 2016 Intel Corporation + * + * Template for [SDEI] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "SDEI" +[0004] Table Length : 0000003E +[0001] Revision : 01 +[0001] Checksum : 59 +[0006] Oem ID : "ARM " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20160930 +
Linux v4.12 has started using the PMU IRQ and GTDT timer offset, discovering that this old version of edk2 is missing these values. Use the PMU IRQ values from the upstream kernel DT, and fix the GTDT: Platform timer offset to point at the time records.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: James Morse james.morse@arm.com --- Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl | 8 ++++---- Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl index 7d91562..ac1bfa8 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl @@ -58,7 +58,7 @@ Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 +[0004] Performance Interrupt : 00000060 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 /* armv8 FVP Base GIC address */ [0008] Virtual GIC Base Address : 000000002C02F000 @@ -79,7 +79,7 @@ Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 +[0004] Performance Interrupt : 00000061 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 [0008] Virtual GIC Base Address : 000000002C02F000 @@ -100,7 +100,7 @@ Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 +[0004] Performance Interrupt : 00000062 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 [0008] Virtual GIC Base Address : 000000002C02F000 @@ -121,7 +121,7 @@ Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 +[0004] Performance Interrupt : 00000063 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 [0008] Virtual GIC Base Address : 000000002C02F000 diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..0cb24c5 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -86,7 +86,7 @@ [0008] CntReadBase Physical address : 0000000000000000
[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Offset : 00000060
/* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00
On Mon, Jun 05, 2017 at 06:31:18PM +0100, James Morse wrote:
Hi Leif, Achin,
These are the OpenPlatformPkg parts of the RAS with SDEI demo on the FVP. There is no intention of upstreaming this, it's intended as a short-lived staging/topic branch, to be replaced by a proper version incorporating the MM work. This is just a bunch of hacks that let us work on the ATF<->Linux and MM stuff separately.
Unfortunately this is based on an old commit: 4e9cfc934508 ("Platforms/ARM: Juno - add Uhci/Xhci drivers"). due to a mixture of ignorance and laziness, (shuffle compiler versions and branches until you find a combination that builds).
MangleHEST? This is a short-lived efi-application that runs before the kernel to fixup the hard-coded HEST by allocating memory for the CPER records and re-writing the table. Obviously no real system should ever do this, this too will be replaced by a proper version that generates a correct HEST all in one go.
New branch mangle-HEST pushed to https://git.linaro.org/uefi/OpenPlatformPkg.git
Tweaked 3/5 to drop all references to LinuxLoader insted of commenting it out.
Do I need to point out that the Reviewed-by:s don't carry anywhere outside this branch? :)
/ Leif
Thanks,
James
Ard Biesheuvel (1): Platforms/FVP: Fix MADT to run the Foundation model in GICv3 mode with 4 CPUs
James Morse (4): Platforms/FVP: Update FADT to ACPIv6 Platforms/FVP: Build MangleHEST, not LinuxLoader Platforms/FVP: Add SDEI and HEST ACPI tables Platforms/FVP: Correct PMU IRQ and GTDT timer offset
.../AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf | 2 + .../VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl | 124 ++++----------------- .../VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl | 6 +- .../VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 2 +- .../VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl | 48 ++++++++ .../VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl | 18 +++ Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 2 + Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 2 +- Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 2 +- 9 files changed, 100 insertions(+), 106 deletions(-) create mode 100644 Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/hest.asl create mode 100644 Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/sdei.asl
-- 2.11.0
-
James Morse -
Leif Lindholm