Code can also be found in my linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-16.12-07-d02-d03
Patch 1 and 2 are for binary and too large to be sent to mailing list; please find it in the above git repo.
Changelog v1:
*Update D02/D03 platform binaries and bug fixed - Update Memory init code - Change ACPI OEM header - Support RoCE Reset through ACPI method
Chenhui Sun (6): D02/ACPI: Use HISI0031 HID for uart on Hip05 soc Platform/D02: Update ACPI table header Plarform/D03: Update ACPI table header D03: Update ACPI Oem table header id D02: Update ACPI table header id D02/D03: Update version to 16.08 RC1
Hanjun Guo (1): D03/DSDT: use irq producer/consumer to support mbi-gen
Heyi Guo (11): Platforms/D02: Update binaries Platforms/D03: Update binaries D02/D03/D05: Support Spd mirror mode Hisilicon/SMBIOS: Update ProcessorID from MIDR D03/OemMiscLib: Add interface for SAS driver D03: Set PcdArmArchTimerFreqInHz to 0 D03/FdtUpdateLib: Update refclk in DT D02: Disable memory test in BDS D03: Disable memory test in BDS D03/ACPI: Refine SAS ASL code indention D03/USB: fix ehci interrupt pin number
Kefeng Wang (1): D02/D03/ACPI: Fix wrong GTDT length
Kejian Yan (2): D02/D03/Dsdt: add media-type property for hns D02/D03/Dsdt/hns: fix the bug of serdes loopback
MaJun (1): D03/IORT:Change the single mapping flags of mbigen node to 1
Salil Mehta (3): D03/ACPI: Add RoCE device to ACPI & IORT Tables D03/ACPI: Add support of RoCE Reset in DSDT D03/ACPI/ROCE: Add node-guid parameter to DSDT
flyingnosky (1): D03/ACPI: support 50MHZ and 66MHZ boards in acpi mode
.../Library/Hi1610Serdes/Hi1610SerdesLib.lib | Bin 601828 -> 603524 bytes .../Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib | Bin 253328 -> 247176 bytes .../Binary/Hi1610/Library/LpcLib/LpcLib.lib | Bin 13870 -> 13998 bytes .../PlatformSysCtrlLibHi1610.lib | Bin 273980 -> 305230 bytes .../Uart/LpcSerialPortLib/LpcSerialPortLib.lib | Bin 17086 -> 17022 bytes .../Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib | Bin 439708 -> 431524 bytes .../ProcessorSubClassDxe/ProcessorSubClass.c | 6 +- .../Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf | 56 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 368 +++++++++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 85 +++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl | 88 +++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 36 ++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 692 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 305 +++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 261 ++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 367 +++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 136 ++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 29 + .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 91 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 96 +++ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 48 ++ .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 128 ++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc | 81 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc | 115 ++++ Chips/Hisilicon/Include/Library/HwMemInitLib.h | 5 +- .../Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf | 56 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl | 337 ---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc | 85 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 5 +- .../Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 558 ----------------- .../Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl | 125 ---- .../Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl | 261 -------- .../Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl | 247 -------- .../Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl | 136 ---- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- .../Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl | 29 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 16 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl | 25 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl | 152 ----- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl | 39 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 6 +- .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 128 ---- .../Pv660/Pv660AcpiTables/Pv660Platform.h | 10 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc | 81 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc | 115 ---- Platforms/Hisilicon/Binary/D02/Ebl/Ebl.efi | Bin 159744 -> 137056 bytes .../Binary/D02/MemoryInitPei/MemoryInit.efi | Bin 159136 -> 160672 bytes Platforms/Hisilicon/Binary/D02/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/Binary/D02/bl1.bin | Bin 14344 -> 12296 bytes Platforms/Hisilicon/Binary/D02/fip.bin | Bin 45621 -> 45621 bytes .../D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 22304 -> 21696 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 22240 -> 22208 bytes .../Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 26720 -> 25440 bytes .../D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 24704 -> 23712 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 18368 -> 18080 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 63648 -> 56832 bytes .../Binary/D03/Drivers/OhciDxe/NativeOhci.efi | Bin 55488 -> 48352 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 22752 -> 22112 bytes .../Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi | Bin 262144 -> 262144 bytes .../Binary/D03/Drivers/Sas/SasDriverDxe.efi | Bin 233408 -> 210752 bytes .../D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 38624 -> 36480 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 22112 -> 21408 bytes Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi | Bin 159744 -> 134240 bytes .../Library/OemAddressMap2P/OemAddressMap2P.lib | Bin 19568 -> 19486 bytes .../Binary/D03/MemoryInitPei/MemoryInit.efi | Bin 158944 -> 161344 bytes Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/Binary/D03/bl1.bin | Bin 14336 -> 14336 bytes Platforms/Hisilicon/Binary/D03/fip.bin | Bin 45601 -> 45601 bytes Platforms/Hisilicon/D02/Pv660D02.dsc | 4 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 24 +- Platforms/Hisilicon/D03/D03.dsc | 10 +- Platforms/Hisilicon/D03/D03.fdf | 10 +- .../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 64 ++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 8 +- .../D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 + 83 files changed, 3205 insertions(+), 2424 deletions(-) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc
Add Spd mirror mode related registers definitioni
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 955b9e4..305040a 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize; + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM]; }DDR_DIMM;
@@ -336,7 +337,7 @@ typedef struct _NVRAM{ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest; - UINT8 Config1[5]; + UINT8 Config1[6]; UINT32 Config2; }MEMORY;
@@ -789,6 +790,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM
#define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte
On Thu, Oct 27, 2016 at 11:15:06AM +0800, Heyi Guo wrote:
Add Spd mirror mode related registers definitioni
Truncated commit message?
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Include/Library/HwMemInitLib.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 955b9e4..305040a 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize;
- UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM];
}DDR_DIMM; @@ -336,7 +337,7 @@ typedef struct _NVRAM{ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest;
- UINT8 Config1[5];
- UINT8 Config1[6];
This does not obviously belong with the described changeset. If it does, please explain why in commit message.
UINT32 Config2;}MEMORY; @@ -789,6 +790,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte
#define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte
1.9.1
It is PORT_TP type if the service port is GE mode. It is wrong to judge the port type by using if it is service port. Adding the media type to know port type.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan yankejian@huawei.com --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 4 ++++ Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index aa83489..b62ee45 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -466,6 +466,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0}, + Package () {"media-type", "fiber"}, } }) } @@ -476,6 +477,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1}, + Package () {"media-type", "fiber"}, } }) } @@ -489,6 +491,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } @@ -502,6 +505,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 5945fc3..2b08a1f 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -439,6 +439,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0}, + Package () {"media-type", "fiber"}, } }) } @@ -449,6 +450,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1}, + Package () {"media-type", "fiber"}, } }) } @@ -462,6 +464,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } @@ -475,6 +478,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) }
Finally getting back to this, apologies for the delay.
Looks fine to me, but a nod from Graeme would be preferable.
Regards,
Leif
On Thu, Oct 27, 2016 at 11:15:07AM +0800, Heyi Guo wrote:
It is PORT_TP type if the service port is GE mode. It is wrong to judge the port type by using if it is service port. Adding the media type to know port type.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan yankejian@huawei.com
Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 4 ++++ Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index aa83489..b62ee45 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -466,6 +466,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0},
Package () {"media-type", "fiber"}, } })@@ -476,6 +477,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1},
Package () {"media-type", "fiber"}, } })@@ -489,6 +491,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){_SB.MDIO}},
Package () {"media-type", "copper"}, } })@@ -502,6 +505,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){_SB.MDIO}},
Package () {"media-type", "copper"}, } })diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 5945fc3..2b08a1f 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -439,6 +439,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0},
Package () {"media-type", "fiber"}, } })@@ -449,6 +450,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1},
Package () {"media-type", "fiber"}, } })@@ -462,6 +464,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){_SB.MDIO}},
Package () {"media-type", "copper"}, } })@@ -475,6 +478,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){_SB.MDIO}},
Package () {"media-type", "copper"}, } })-- 1.9.1
Hi Graeme,
Could you help to review the D02/D03 ACPI related patches?
Thanks and Regards.
在 11/6/2016 12:40 AM, Leif Lindholm 写道:
Finally getting back to this, apologies for the delay.
Looks fine to me, but a nod from Graeme would be preferable.
Regards,
Leif
On Thu, Oct 27, 2016 at 11:15:07AM +0800, Heyi Guo wrote:
It is PORT_TP type if the service port is GE mode. It is wrong to judge the port type by using if it is service port. Adding the media type to know port type.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan yankejian@huawei.com
Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 4 ++++ Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index aa83489..b62ee45 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -466,6 +466,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0},
Package () {"media-type", "fiber"}, } }) }@@ -476,6 +477,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1},
Package () {"media-type", "fiber"}, } }) }@@ -489,6 +491,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){_SB.MDIO}},
Package () {"media-type", "copper"}, } }) }@@ -502,6 +505,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){_SB.MDIO}},
Package () {"media-type", "copper"}, } }) }diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 5945fc3..2b08a1f 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -439,6 +439,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0},
Package () {"media-type", "fiber"}, } }) }@@ -449,6 +450,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1},
Package () {"media-type", "fiber"}, } }) }@@ -462,6 +464,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){_SB.MDIO}},
Package () {"media-type", "copper"}, } }) }@@ -475,6 +478,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){_SB.MDIO}},
Package () {"media-type", "copper"}, } }) }-- 1.9.1
The register of Hilink needs to be configed, but the current procedure does not do that. The temporary variable to be set to register is wrong, it must be Local0 instead of Local1.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan yankejian@huawei.com --- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 20 ++++++++++---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 12 ++++++------ 2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index b62ee45..d8d453a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -126,16 +126,16 @@ Scope(_SB) OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) Field(H4LR, DWordAcc, NoLock, Preserve) { H4L0, 16, // port0 - H4R0, 16, //RESERVED + , 16, //RESERVED Offset (0x400), H4L1, 16, // port1 - H4R1, 16, //RESERVED + , 16, //RESERVED Offset (0x800), H4L2, 16, // port2 - H4R2, 16, //RESERVED + , 16, //RESERVED Offset (0xc00), H4L3, 16, // port3 - H4R3, 16, //RESERVED + , 16, //RESERVED } OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) Field(H3LR, DWordAcc, NoLock, Preserve) { @@ -266,42 +266,42 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L0) + Store (Local0, H4L0) } case (0x1){ Store (0, HSEL) Store (H4L1, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L1) + Store (Local0, H4L1) } case (0x2){ Store (0, HSEL) Store (H4L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L2) + Store (Local0, H4L2) } case (0x3){ Store (0, HSEL) Store (H4L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L3) + Store (Local0, H4L3) } case (0x4){ Store (3, HSEL) Store (H3L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L2) + Store (Local0, H3L2) } case (0x5){ Store (3, HSEL) Store (H3L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L3) + Store (Local0, H3L3) } } } diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 2b08a1f..881aa14 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -250,37 +250,37 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L0) + Store (Local0, H4L0) } case (0x1){ Store (H4L1, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L1) + Store (Local0, H4L1) } case (0x2){ Store (H4L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L2) + Store (Local0, H4L2) } case (0x3){ Store (H4L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L3) + Store (Local0, H4L3) } case (0x4){ Store (H3L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L2) + Store (Local0, H3L2) } case (0x5){ Store (H3L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L3) + Store (Local0, H3L3) } } }
Graeme?
On Thu, Oct 27, 2016 at 11:15:08AM +0800, Heyi Guo wrote:
The register of Hilink needs to be configed, but the current procedure does not do that. The temporary variable to be set to register is wrong, it must be Local0 instead of Local1.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan yankejian@huawei.com
.../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 20 ++++++++++---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 12 ++++++------ 2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index b62ee45..d8d453a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -126,16 +126,16 @@ Scope(_SB) OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) Field(H4LR, DWordAcc, NoLock, Preserve) { H4L0, 16, // port0
H4R0, 16, //RESERVED
, 16, //RESERVED Offset (0x400), H4L1, 16, // port1
H4R1, 16, //RESERVED
, 16, //RESERVED Offset (0x800), H4L2, 16, // port2
H4R2, 16, //RESERVED
, 16, //RESERVED Offset (0xc00), H4L3, 16, // port3
H4R3, 16, //RESERVED
, 16, //RESERVED }@@ -266,42 +266,42 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H4L0)
Store (Local0, H4L0) } case (0x1){ Store (0, HSEL) Store (H4L1, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H4L1)
Store (Local0, H4L1) } case (0x2){ Store (0, HSEL) Store (H4L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H4L2)
Store (Local0, H4L2) } case (0x3){ Store (0, HSEL) Store (H4L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H4L3)
Store (Local0, H4L3) } case (0x4){ Store (3, HSEL) Store (H3L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H3L2)
Store (Local0, H3L2) } case (0x5){ Store (3, HSEL) Store (H3L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H3L3)
Store (Local0, H3L3) } }diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 2b08a1f..881aa14 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -250,37 +250,37 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H4L0)
Store (Local0, H4L0) } case (0x1){ Store (H4L1, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H4L1)
Store (Local0, H4L1) } case (0x2){ Store (H4L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H4L2)
Store (Local0, H4L2) } case (0x3){ Store (H4L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H4L3)
Store (Local0, H4L3) } case (0x4){ Store (H3L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H3L2)
Store (Local0, H3L2) } case (0x5){ Store (H3L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0)
Store (Local1, H3L3)
Store (Local0, H3L3) } }-- 1.9.1
The UART on Hip05 soc is not 16550 compatible, use appropriate ACPI ID for Hisi uart instead of APM one.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kefeng Wang wangkefeng.wang@huawei.com --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl index 43027e4..3bcc5fb 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl @@ -18,13 +18,12 @@
Scope(_SB) { - // UART 8250 Device(COM0) { - Name(_HID, "APMC0D08") //Or AMD0020, trick to use dw8250 serial driver + Name(_HID, "HISI0031") //it is not 16550 compatible Name(_CID, "8250dw") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0x80300000, 0x1000) //0x7FF80000, 0x1000 + Memory32Fixed(ReadWrite, 0x80300000, 0x1000) Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 } }) Name (_DSD, Package () {
On Thu, Oct 27, 2016 at 11:15:09AM +0800, Heyi Guo wrote:
The UART on Hip05 soc is not 16550 compatible, use appropriate ACPI ID for Hisi uart instead of APM one.
Is this expected to keep working seemlessly?
Graeme, any further comments?
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kefeng Wang wangkefeng.wang@huawei.com
Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl index 43027e4..3bcc5fb 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl @@ -18,13 +18,12 @@ Scope(_SB) {
- // UART 8250 Device(COM0) {
- Name(_HID, "APMC0D08") //Or AMD0020, trick to use dw8250 serial driver
- Name(_HID, "HISI0031") //it is not 16550 compatible Name(_CID, "8250dw") Name(_UID, Zero) Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x80300000, 0x1000) //0x7FF80000, 0x1000
Memory32Fixed(ReadWrite, 0x80300000, 0x1000)
This is unrelated cleanup.
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 } }) Name (_DSD, Package () {-- 1.9.1
Set all ACPI tables' ID as below:
EFI_ACPI_ARM_OEM_ID HISI EFI_ACPI_ARM_OEM_TABLE_ID HISI0660 EFI_ACPI_ARM_OEM_REVISION 0x00000000 EFI_ACPI_ARM_CREATOR_ID INTL EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
Note that D02 SATASSDT/SASSSDT tables are not updated because we need different SSDT OEM TABLE ID uesed for UninstallACPI driver
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com --- .../Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf | 56 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl | 337 ------------ Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc | 85 ---- .../Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 562 --------------------- .../Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl | 125 ----- .../Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl | 261 ---------- .../Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl | 247 --------- .../Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl | 136 ----- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- .../Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl | 29 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl | 25 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl | 152 ------ .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl | 39 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 6 +- .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 128 ----- .../Pv660/Pv660AcpiTables/Pv660Platform.h | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc | 81 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc | 115 ----- 18 files changed, 8 insertions(+), 2386 deletions(-) delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf b/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf deleted file mode 100644 index b6be3d9..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf +++ /dev/null @@ -1,56 +0,0 @@ -## @file -# -# ACPI table data and ASL sources required to boot the platform. -# -# Copyright (c) 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -# -## - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = Hi1610AcpiTables - FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD - MODULE_TYPE = USER_DEFINED - VERSION_STRING = 1.0 - -[Sources] - Dsdt/DsdtHi1610.asl - Facs.aslc - Fadt.aslc - Gtdt.aslc - MadtHi1610.aslc - D03Mcfg.aslc - D03Iort.asl - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - - OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdCoreCount - gArmTokenSpaceGuid.PcdGicDistributorBase - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - - gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl deleted file mode 100644 index 07660df..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Intel ACPI Component Architecture - * iASL Compiler/Disassembler version 20151124-64 - * Copyright (c) 2000 - 2015 Intel Corporation - * - * Template for [IORT] ACPI Table (static data table) - * Format: [ByteLength] FieldName : HexFieldValue - */ -[0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 0000029e -[0001] Revision : 00 -[0001] Checksum : BC -[0006] Oem ID : "HISI " -[0008] Oem Table ID : "D03" -[0004] Oem Revision : 00000000 -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20150410 - -[0004] Node Count : 00000008 -[0004] Node Offset : 00000034 -[0004] Reserved : 00000000 -[0004] Optional Padding : 00 00 00 00 - -/* ITS 0, for dsa */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000000 - -/* mbi-gen dsa mbi0 - usb, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0017] Device Name : "_SB_.MBI0" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040080 // device id -[0004] Output Reference : 00000034 // point to its dsa -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi1 - sas1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI1" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi2 - sas2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI2" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040040 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi3 - dsa0, srv named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI3" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040800 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI4" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1c -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI5" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1d -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi6 - dsa sas0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI6" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040900 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* RC 0 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000000 - -[0004] Input base : 00000000 -[0004] ID Count : 00002000 -[0004] Output Base : 00000000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* RC 1 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000001 - -[0004] Input base : 0000e000 -[0004] ID Count : 00002000 -[0004] Output Base : 0000e000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* RC 2 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000002 - -[0004] Input base : 00008000 -[0004] ID Count : 00002000 -[0004] Output Base : 00008000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc deleted file mode 100644 index 9f60803..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2016 Hisilicon Limited - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the BSD License which accompanies - * this distribution, and is available at - * http://opensource.org/licenses/bsd-license.php - * - */ - -#include <IndustryStandard/Acpi.h> -#include "Pv660Platform.h" - -#define ACPI_5_0_MCFG_VERSION 0x1 - -#pragma pack(1) -typedef struct -{ - UINT64 ullBaseAddress; - UINT16 usSegGroupNum; - UINT8 ucStartBusNum; - UINT8 ucEndBusNum; - UINT32 Reserved2; -}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; - -typedef struct -{ - EFI_ACPI_DESCRIPTION_HEADER Header; - UINT64 Reserved1; -}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; - -typedef struct -{ - EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3]; -}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; -#pragma pack() - -EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= -{ - { - { - EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - ACPI_5_0_MCFG_VERSION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION - }, - 0x0000000000000000, //Reserved - }, - { - - { - 0xb0000000, //Base Address - 0x0, //Segment Group Number - 0x0, //Start Bus Number - 0x1f, //End Bus Number - 0x00000000, //Reserved - }, - { - 0xb0000000, //Base Address - 0x1, //Segment Group Number - 0xe0, //Start Bus Number - 0xff, //End Bus Number - 0x00000000, //Reserved - }, - { - 0xa0000000, //Base Address - 0x2, //Segment Group Number - 0x80, //Start Bus Number - 0x9f, //End Bus Number - 0x00000000, //Reserved - }, - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl deleted file mode 100644 index d8d453a..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ /dev/null @@ -1,562 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -Scope(_SB) -{ - Device (MDIO) - { - OperationRegion(CLKR, SystemMemory, 0x60000338, 8) - Field(CLKR, DWordAcc, NoLock, Preserve) { - CLKE, 1, // clock enable - , 31, - CLKD, 1, // clode disable - , 31, - } - OperationRegion(RSTR, SystemMemory, 0x60000A38, 8) - Field(RSTR, DWordAcc, NoLock, Preserve) { - RSTE, 1, // reset - , 31, - RSTD, 1, // de-reset - , 31, - } - - Name(_HID, "HISI0141") - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000) - }) - - Method(_RST, 0, Serialized) { - Store (0x1, RSTE) - Sleep (10) - Store (0x1, CLKD) - Sleep (10) - Store (0x1, RSTD) - Sleep (10) - Store (0x1, CLKE) - Sleep (10) - } - } - - Device (DSF0) - { - OperationRegion(H3SR, SystemMemory, 0xC0000184, 4) - Field(H3SR, DWordAcc, NoLock, Preserve) { - H3ST, 1, - , 31, //RESERVED - } - OperationRegion(H4SR, SystemMemory, 0xC0000194, 4) - Field(H4SR, DWordAcc, NoLock, Preserve) { - H4ST, 1, - , 31, //RESERVED - } - // DSAF RESET - OperationRegion(DRER, SystemMemory, 0xC0000A00, 8) - Field(DRER, DWordAcc, NoLock, Preserve) { - DRTE, 1, - , 31, //RESERVED - DRTD, 1, - , 31, //RESERVED - } - // NT RESET - OperationRegion(NRER, SystemMemory, 0xC0000A08, 8) - Field(NRER, DWordAcc, NoLock, Preserve) { - NRTE, 1, - , 31, //RESERVED - NRTD, 1, - , 31, //RESERVED - } - // XGE RESET - OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) - Field(XRER, DWordAcc, NoLock, Preserve) { - XRTE, 31, - , 1, //RESERVED - XRTD, 31, - , 1, //RESERVED - } - - // GE RESET - OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) - Field(GRTR, DWordAcc, NoLock, Preserve) { - GR0E, 30, - , 2, //RESERVED - GR0D, 30, - , 2, //RESERVED - GR1E, 18, - , 14, //RESERVED - GR1D, 18, - , 14, //RESERVED - } - // PPE RESET - OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) - Field(PRTR, DWordAcc, NoLock, Preserve) { - PRTE, 10, - , 22, //RESERVED - PRTD, 10, - , 22, //RESERVED - } - - // RCB PPE COM RESET - OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8) - Field(RRTR, DWordAcc, NoLock, Preserve) { - RRTE, 1, - , 31, //RESERVED - RRTD, 1, - , 31, //RESERVED - } - - // Hilink access sel cfg reg - OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) - Field(HSER, DWordAcc, NoLock, Preserve) { - HSEL, 2, // hilink_access_sel & hilink_access_wr_pul - , 30, // RESERVED - } - - // Serdes - OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) - Field(H4LR, DWordAcc, NoLock, Preserve) { - H4L0, 16, // port0 - , 16, //RESERVED - Offset (0x400), - H4L1, 16, // port1 - , 16, //RESERVED - Offset (0x800), - H4L2, 16, // port2 - , 16, //RESERVED - Offset (0xc00), - H4L3, 16, // port3 - , 16, //RESERVED - } - OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) - Field(H3LR, DWordAcc, NoLock, Preserve) { - H3L2, 16, // port4 - , 16, //RESERVED - Offset (0x400), - H3L3, 16, // port5 - , 16, //RESERVED - } - Name (_HID, "HISI00B2") - Name (_CCA, 1) // Cache-coherent controller - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) - Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"mode", "6port-16rss"}, - Package () {"buf-size", 4096}, - Package () {"desc-num", 1024}, - Package () {"interrupt-parent", Package() {_SB.MBI3}}, - } - }) - - //reset XGE port - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XRST, 2, Serialized) { - ShiftLeft (0x2082082, Arg0, Local0) - Or (Local0, 0x1, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset XGE core - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XCRT, 2, Serialized) { - ShiftLeft (0x2080, Arg0, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset GE port - //Arg0 : GE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(GRST, 2, Serialized) { - If (LLessEqual (Arg0, 5)) { - //Service port - ShiftLeft (0x2082082, Arg0, Local0) - ShiftLeft (0x1, Arg0, Local1) - - If (LEqual (Arg1, 0)) { - Store(Local1, GR1E) - Store(Local0, GR0E) - } Else { - Store(Local0, GR0D) - Store(Local1, GR1D) - } - } - } - - //reset PPE port - //Arg0 : PPE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(PRST, 2, Serialized) { - ShiftLeft (0x1, Arg0, Local0) - If (LEqual (Arg1, 0)) { - Store(Local0, PRTE) - } Else { - Store(Local0, PRTD) - } - } - - // Set Serdes Loopback - //Arg0 : port - //Arg1 : 0 disable, 1 enable - Method(SRLP, 2, Serialized) { - ShiftLeft (Arg1, 10, Local0) - Switch (ToInteger(Arg0)) - { - case (0x0){ - Store (0, HSEL) - Store (H4L0, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L0) - } - case (0x1){ - Store (0, HSEL) - Store (H4L1, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L1) - } - case (0x2){ - Store (0, HSEL) - Store (H4L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L2) - } - case (0x3){ - Store (0, HSEL) - Store (H4L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L3) - } - case (0x4){ - Store (3, HSEL) - Store (H3L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L2) - } - case (0x5){ - Store (3, HSEL) - Store (H3L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L3) - } - } - } - - //Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) - //Arg1 : port - //Arg2 : 0 disable, 1 enable - Method(DRST, 3, Serialized) - { - Switch (ToInteger(Arg0)) - { - //DSAF reset - case (0x1) - { - Store (Arg2, Local0) - If (LEqual (Local0, 0)) - { - Store (0x1, DRTE) - Store (0x1, NRTE) - Sleep (10) - Store (0x1, RRTE) - } - Else - { - Store (0x1, DRTD) - Store (0x1, NRTD) - Sleep (10) - Store (0x1, RRTD) - } - } - //Reset PPE port - case (0x2) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - PRST (Local0, Local1) - } - - //Reset XGE core - case (0x3) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XCRT (Local0, Local1) - } - //Reset XGE port - case (0x4) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XRST (Local0, Local1) - } - - //Reset GE port - case (0x5) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - GRST (Local0, Local1) - } - } - } - - // _DSM Device Specific Method - // - // Arg0: UUID Unique function identifier - // Arg1: Integer Revision Level - // Arg2: Integer Function Index - // 0 : Return Supported Functions bit mask - // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) - // Arg3[1] : port index in dsaf - // Arg3[2] : 0 reset, 1 cancle reset - // 2 : Set Serdes Loopback - // Arg3[0] : port - // Arg3[1] : 0 disable, 1 enable - // 3 : LED op set - // Arg3[0] : op type - // Arg3[1] : port - // Arg3[2] : para - // 4 : Get port type (GE or XGE) - // Arg3[0] : port index in dsaf - // Return : 0 GE, 1 XGE - // 5 : Get sfp status - // Arg3[0] : port index in dsaf - // Return : 0 no sfp, 1 have sfp - // Arg3: Package Parameters - Method (_DSM, 4, Serialized) - { - If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) - { - If (LEqual (Arg1, 0x00)) - { - Switch (ToInteger(Arg2)) - { - case (0x0) - { - Return (Buffer () {0x3F}) - } - - //Reset Sequence - case (0x1) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - Store (DeRefOf (Index (Arg3, 2)), Local2) - DRST (Local0, Local1, Local2) - } - - //Set Serdes Loopback - case (0x2) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - SRLP (Local0, Local1) - } - - //LED op set - case (0x3) - { - - } - - // Get port type (GE or XGE) - case (0x4) - { - Store (0, Local1) - Store (DeRefOf (Index (Arg3, 0)), Local0) - If (LLessEqual (Local0, 3)) - { - // mac0: Hilink4 Lane0 - // mac1: Hilink4 Lane1 - // mac2: Hilink4 Lane2 - // mac3: Hilink4 Lane3 - Store (H4ST, Local1) - } - ElseIf (LLessEqual (Local0, 5)) - { - // mac4: Hilink3 Lane2 - // mac5: Hilink3 Lane3 - Store (H3ST, Local1) - } - - Return (Local1) - } - - //Get sfp status - case (0x5) - { - - } - } - } - } - Return (Buffer() {0x00}) - } - Device (PRT0) - { - Name (_ADR, 0x0) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 0}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT1) - { - Name (_ADR, 0x1) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 1}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT4) - { - Name (_ADR, 0x4) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 4}, - Package () {"phy-mode", "sgmii"}, - Package () {"phy-addr", 0}, - Package () {"mdio-node", Package (){_SB.MDIO}}, - Package () {"media-type", "copper"}, - } - }) - } - Device (PRT5) - { - Name (_ADR, 0x5) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 5}, - Package () {"phy-mode", "sgmii"}, - Package () {"phy-addr", 1}, - Package () {"mdio-node", Package (){_SB.MDIO}}, - Package () {"media-type", "copper"}, - } - }) - } - } - Device (ETH4) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){_SB.DSF0}}, - Package () {"port-idx-in-ae", 4}, - } - }) - } - Device (ETH5) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){_SB.DSF0}}, - Package () {"port-idx-in-ae", 5}, - } - }) - } - Device (ETH0) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){_SB.DSF0}}, - Package () {"port-idx-in-ae", 0}, - } - }) - } - Device (ETH1) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){_SB.DSF0}}, - Package () {"port-idx-in-ae", 1}, - } - }) - } - -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl deleted file mode 100644 index 4eaa073..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl +++ /dev/null @@ -1,125 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -Scope(_SB) -{ - // Mbi-gen pcie subsys - Device(MBI0) { - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 2} - } - }) - } - - // Mbi-gen sas1 intc - Device(MBI1) { - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - - Device(MBI2) { // Mbi-gen sas2 intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - - Device(MBI3) { // Mbi-gen dsa0 srv intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 409} - } - }) - } - - Device(MBI4) { // Mbi-gen dsa1 dbg0 intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 9} - } - }) - } - - Device(MBI5) { // Mbi-gen dsa2 dbg1 intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 9} - } - }) - } - - Device(MBI6) { // Mbi-gen dsa sas0 intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl deleted file mode 100644 index 573c0a3..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl +++ /dev/null @@ -1,261 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -//#include "ArmPlatform.h" -Scope(_SB) -{ - // PCIe Root bus - Device (PCI0) - { - Name (_HID, "HISI0080") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x1f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xb2000000, // Min Base Address pci address - 0xb7feffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xb7ff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - - Device (RES0) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000) - }) - } - - OperationRegion(SCTR, SystemMemory, 0xa009131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } - } // Device(PCI0) - - // PCIe Root bus - Device (PCI1) - { - Name (_HID, "HISI0080") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 1) // Segment of this Root complex - Name(_BBN, 0xe0) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0xe0, // AddressMinimum - Minimum Bus Number - 0xff, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xb8000000, // Min Base Address pci address - 0xbdfeffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xbdff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - - Device (RES1) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) - }) - } - - OperationRegion(SCTR, SystemMemory, 0xa020131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { - - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } - } // Device(PCI1) - - // PCIe Root bus - Device (PCI2) - { - Name (_HID, "HISI0080") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x9f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xaa000000, // Min Base Address - 0xaffeffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xafff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - - Device (RES2) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) - }) - } - - OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) - { - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } - } // Device(PCI2) -} - diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl deleted file mode 100644 index ce8ccd6..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl +++ /dev/null @@ -1,247 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> - Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -Scope(_SB) -{ - Device(SAS0) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 64,65,66,67,68, - 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) - { - 601,602,603,604, - 605,606,607,608,609, - 610,611,612,613,614, - 615,616,617,618,619, - 620,621,622,623,624, - 625,626,627,628,629, - 630,631,632, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI6}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x338), - CLK, 32, - CLKD, 32, - Offset (0xa60), - RST, 32, - DRST, 32, - Offset (0x5a30), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - } - - Device(SAS1) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 64,65,66,67,68, - 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) - { - 576,577,578,579,580, - 581,582,583,584,585, - 586,587,588,589,590, - 591,592,593,594,595, - 596,597,598,599,600, - 601,602,603,604,605, - 606,607, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI1}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - Package () {"hip06-sas-v2-quirk-amt", 1}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x318), - CLK, 32, - CLKD, 32, - Offset (0xa18), - RST, 32, - DRST, 32, - Offset (0x5a0c), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - } - - Device(SAS2) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 192,193,194,195,196, - 197,198,199,200,201, - 202,203,204,205,206, - 207,208,209,210,211, - 212,213,214,215,216, - 217,218,219,220,221, - 222,223,224,225,226, - 227,228,229,230,231, - 232,233,234,235,236, - 237,238,239,240,241, - 242,243,244,245,246, - 247,248,249,250,251, - 252,253,254,255,256, - 257,258,259,260,261, - 262,263,264,265,266, - 267,268,269,270,271, - 272,273,274,275,276, - 277,278,279,280,281, - 282,283,284,285,286, - 287, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) - { - 608,609,610,611, - 612,613,614,615,616, - 617,618,619,620,621, - 622,623,624,625,626, - 627,628,629,630,631, - 632,633,634,635,636, - 637,638,639, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI2}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x3a8), - CLK, 32, - CLKD, 32, - Offset (0xae0), - RST, 32, - DRST, 32, - Offset (0x5a70), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - } - -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl deleted file mode 100644 index 28ba03d..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl +++ /dev/null @@ -1,136 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> - Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -//#include "ArmPlatform.h" -Scope(_SB) -{ - Device (USB0) - { - Name (_HID, "PNP0D20") // _HID: Hardware ID - Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID - Name (_CCA, One) // _CCA: Cache Coherency Attribute - Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings - { - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, - 0xa7020000, // Address Base - 0x00010000, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 0x00000041, - } - }) - Return (RBUF) /* _SB_.USB0._CRS.RBUF */ - } - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"interrupt-parent",Package() {_SB.MBI0}} - } - }) - - Device (RHUB) - { - Name (_ADR, Zero) // _ADR: Address - Device (PRT1) - { - Name (_ADR, One) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - Zero, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0, - PLD_VerticalOffset = 0x0, - PLD_HorizontalOffset = 0x0) - - }) - } - - Device (PRT2) - { - Name (_ADR, 0x02) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - - Device (PRT3) - { - Name (_ADR, 0x03) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - - Device (PRT4) - { - Name (_ADR, 0x04) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - } - } -} - diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl index ce5a085..f156e1b 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl @@ -18,7 +18,7 @@
#include "Pv660Platform.h"
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI-D02", EFI_ACPI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI0660", EFI_ACPI_ARM_OEM_REVISION) { include ("Mbig.asl") include ("CPU.asl") include ("Com.asl") diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl deleted file mode 100644 index 06c05aa..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl +++ /dev/null @@ -1,29 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> - Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -#include "Pv660Platform.h" - -DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI-EVB", EFI_ACPI_ARM_OEM_REVISION) { - include ("Lpc.asl") - include ("D03Mbig.asl") - include ("CPU.asl") - include ("D03Usb.asl") - include ("D03Hns.asl") - include ("D03Sas.asl") - include ("D03Pci.asl") -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl deleted file mode 100644 index 0965afc..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl +++ /dev/null @@ -1,25 +0,0 @@ -/** @file -* -* Copyright (c) 2016 Hisilicon Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -// -// LPC -// - -Device (LPC0) -{ - Name(_HID, "HISI0191") // HiSi LPC - Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) - }) -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl deleted file mode 100644 index 4c3c642..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl +++ /dev/null @@ -1,152 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -Scope(_SB) -{ - Device(SAS0) { - Name(_HID, "HISI0161") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc1000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - //phy irq(0~79) - 259,263,264, - 269,273,274, - 279,283,284, - 289,293,294, - 299,303,304, - 309,313,314, - 319,323,324, - 329,333,334, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) - { - //cq irq (80~111) - 336,337,338,339,340,341,342,343, - 344,345,346,347,348,349,350,351, - 352,353,354,355,356,357,358,359, - 360,361,362,363,364,365,366,367, - } - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 376, //chip fatal error irq(120) - 381, //chip fatal error irq(125) - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI1}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x0a}}, - Package () {"queue-count", 32}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x338), - CLK, 32, - CLKD, 32, - Offset (0xa60), - RST, 32, - DRST, 32, - Offset (0x5a30), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - } - - Device(SAS1) { - Name(_HID, "HISI0161") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xb1000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - //phy irq(0~79) - 259,263,264, - 269,273,274, - 279,283,284, - 289,293,294, - 299,303,304, - 309,313,314, - 319,323,324, - 329,333,334, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) - { - //cq irq (80~111) - 336,337,338,339,340,341,342,343, - 344,345,346,347,348,349,350,351, - 352,353,354,355,356,357,358,359, - 360,361,362,363,364,365,366,367, - } - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 376, //chip fatal error irq(120) - 381, //chip fatal error irq(125) - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI3}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 32}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xB0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x318), - CLK, 32, - CLKD, 32, - Offset (0xa18), - RST, 32, - DRST, 32, - Offset (0x5a0c), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - } -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl deleted file mode 100644 index 9ad2d96..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl +++ /dev/null @@ -1,39 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -// -// SATA AHCI -// - -Device (AHCI) -{ - Name(_HID, "HISI0001") // HiSi AHCI - Name (_CCA, 1) // Cache-coherent controller - Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0xb1002800, 0x00000B00) - Memory32Fixed (ReadWrite, 0xb1000000, 0x00002800) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 382 } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI3}} - } - }) -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index 44056b5..9ba3d55 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -10,11 +10,11 @@ [0004] Table Length : 0000010C [0001] Revision : 00 [0001] Checksum : BC -[0006] Oem ID : "INTEL " -[0008] Oem Table ID : "TEMPLATE" +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HISI0660" [0004] Oem Revision : 00000000 [0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20150410 +[0004] Asl Compiler Revision : 20151124
[0004] Node Count : 0000000A [0004] Node Offset : 00000034 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc deleted file mode 100644 index 6e8557e..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc +++ /dev/null @@ -1,128 +0,0 @@ -/** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Pv660Platform.h" - -#include <Library/AcpiLib.h> -#include <Library/ArmLib.h> -#include <Library/PcdLib.h> -#include <IndustryStandard/Acpi.h> -#include <Library/AcpiNextLib.h> - -// Differs from Juno, we have another affinity level beyond cluster and core -// 0x20000 is only for socket 0 -#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) - -// -// Multiple APIC Description Table -// -#pragma pack (1) - -typedef struct { - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1]; -} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; - -#pragma pack () - -EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { - { - ARM_ACPI_HEADER ( - EFI_ACPI_1_0_APIC_SIGNATURE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION - ), - // - // MADT specific fields - // - 0, // LocalApicAddress - 0, // Flags - }, - { - // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, - // GsivId, GicRBase, Mpidr) - // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of - // ACPI v5.1). - // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses - // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), - }, - - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), - { - EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000), - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h index 5af8f1a..3d69d96 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h @@ -24,10 +24,10 @@ // ACPI table information used to initialize tables. // #define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','-','D','0','2') // OEM table id 8 bytes long -#define EFI_ACPI_ARM_OEM_REVISION 0x20140727 -#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('H','I','S','I') -#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099 +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','0','6','6','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
// A macro to initialise the common header part of EFI ACPI tables as defined by // EFI_ACPI_DESCRIPTION_HEADER structure. diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc deleted file mode 100644 index 2fa2959..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2013 Linaro Limited - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the BSD License which accompanies - * this distribution, and is available at - * http://opensource.org/licenses/bsd-license.php - * - * Contributors: - * Yi Li - yi.li@linaro.org -*/ - -#include <IndustryStandard/Acpi.h> -#include "Pv660Platform.h" - -#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014 - -#pragma pack(1) -typedef struct { - UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; -} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; - -typedef struct { - EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; - EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; - -} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE; -#pragma pack() - -// -// System Locality Information Table -// Please modify all values in Slit.h only. -// -EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { - { - { - EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE), - EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION, - }, - // - // Beginning of SLIT specific fields - // - EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, - }, - { - {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality 0 - {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality 1 - {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality 2 - {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality 3 - {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality 4 - {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality 5 - {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality 6 - {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality 7 - {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality 8 - {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality 9 - {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality 10 - {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality 11 - {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality 12 - {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality 13 - {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality 14 - {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality 15 - {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality 16 - {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality 17 - {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality 18 - {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality 19 - }, -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Slit; - diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc deleted file mode 100644 index 1d38191..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2013 Linaro Limited - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the BSD License which accompanies - * this distribution, and is available at - * http://opensource.org/licenses/bsd-license.php - * - * Contributors: - * Yi Li - yi.li@linaro.org - * - * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -*/ - -#include <IndustryStandard/Acpi.h> -#include "Pv660Platform.h" -#include <Library/AcpiLib.h> -#include <Library/AcpiNextLib.h> - - -// -// Define the number of each table type. -// This is where the table layout is modified. -// -#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT 4 -#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 4 - - -#pragma pack(1) -typedef struct { - EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; - EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE Apic; - EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE Memory[2]; - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE GICC[16]; -} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE; - -#pragma pack() - - -// -// Static Resource Affinity Table definition -// -EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = { - { - {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE), - EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION}, - /*Reserved*/ - 0x00000001, // Reserved to be 1 for backward compatibility - EFI_ACPI_RESERVED_QWORD - }, - /**/ - { - 0x00, // Subtable Type:Processor Local APIC/SAPIC Affinity - sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE), //Length - 0x00, //Proximity Domain Low(8) - 0x00, //Apic ID - 0x00000001, //Flags - 0x00, //Local Sapic EID - {0,0,0}, //Proximity Domain High(24) - 0x00000000, //ClockDomain - }, - // - // - // Memory Affinity - // - { - EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001), - EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001), - }, - - /*Processor Local x2APIC Affinity*/ - //{ - // 0x02, // Subtable Type:Processor Local x2APIC Affinity - // sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE), - // {0,0}, //Reserved1 - // 0x00000000, //Proximity Domain - // 0x00000000, //Apic ID - // 0x00000001, //Flags - // 0x00000000, //Clock Domain - // {0,0,0,0}, //Reserved2 - //}, - - { - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 - EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000) //GICC Affinity Processor 15 - }, -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Srat; -
On Thu, Oct 27, 2016 at 11:15:10AM +0800, Heyi Guo wrote:
Set all ACPI tables' ID as below:
EFI_ACPI_ARM_OEM_ID HISI EFI_ACPI_ARM_OEM_TABLE_ID HISI0660 EFI_ACPI_ARM_OEM_REVISION 0x00000000 EFI_ACPI_ARM_CREATOR_ID INTL EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
Note that D02 SATASSDT/SASSSDT tables are not updated because we need different SSDT OEM TABLE ID uesed for UninstallACPI driver
The commit message and title do not match the patch, which simply deletes lots of things. Was there an accident in rebasing?
Regards,
Leif
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com
.../Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf | 56 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl | 337 ------------ Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc | 85 ---- .../Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 562 --------------------- .../Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl | 125 ----- .../Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl | 261 ---------- .../Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl | 247 --------- .../Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl | 136 ----- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- .../Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl | 29 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl | 25 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl | 152 ------ .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl | 39 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 6 +- .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 128 ----- .../Pv660/Pv660AcpiTables/Pv660Platform.h | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc | 81 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc | 115 ----- 18 files changed, 8 insertions(+), 2386 deletions(-) delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf b/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf deleted file mode 100644 index b6be3d9..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf +++ /dev/null @@ -1,56 +0,0 @@ -## @file -# -# ACPI table data and ASL sources required to boot the platform. -# -# Copyright (c) 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -# -##
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = Hi1610AcpiTables
- FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
-[Sources]
- Dsdt/DsdtHi1610.asl
- Facs.aslc
- Fadt.aslc
- Gtdt.aslc
- MadtHi1610.aslc
- D03Mcfg.aslc
- D03Iort.asl
-[Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
-[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl deleted file mode 100644 index 07660df..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl +++ /dev/null @@ -1,337 +0,0 @@ -/*
- Intel ACPI Component Architecture
- iASL Compiler/Disassembler version 20151124-64
- Copyright (c) 2000 - 2015 Intel Corporation
- Template for [IORT] ACPI Table (static data table)
- Format: [ByteLength] FieldName : HexFieldValue
- */
-[0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 0000029e -[0001] Revision : 00 -[0001] Checksum : BC -[0006] Oem ID : "HISI " -[0008] Oem Table ID : "D03" -[0004] Oem Revision : 00000000 -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20150410
-[0004] Node Count : 00000008 -[0004] Node Offset : 00000034 -[0004] Reserved : 00000000 -[0004] Optional Padding : 00 00 00 00
-/* ITS 0, for dsa */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000
-[0004] ItsCount : 00000001 -[0004] Identifiers : 00000000
-/* mbi-gen dsa mbi0 - usb, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032
-[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0001] Memory Size Limit : 00 -[0017] Device Name : "_SB_.MBI0" -[0004] Padding : 00 00 00 00
-[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040080 // device id -[0004] Output Reference : 00000034 // point to its dsa -[0004] Flags (decoded below) : 00000000
Single Mapping : 1-/* mbi-gen dsa mbi1 - sas1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032
-[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI1" -[0004] Padding : 00 00 00 00
-[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 1-/* mbi-gen dsa mbi2 - sas2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032
-[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI2" -[0004] Padding : 00 00 00 00
-[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040040 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 1-/* mbi-gen dsa mbi3 - dsa0, srv named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032
-[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI3" -[0004] Padding : 00 00 00 00
-[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040800 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 1-/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032
-[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI4" -[0004] Padding : 00 00 00 00
-[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1c -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 1-/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032
-[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI5" -[0004] Padding : 00 00 00 00
-[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1d -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 1-/* mbi-gen dsa mbi6 - dsa sas0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032
-[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI6" -[0004] Padding : 00 00 00 00
-[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040900 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 1-/* RC 0 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020
-[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000000
-[0004] Input base : 00000000 -[0004] ID Count : 00002000 -[0004] Output Base : 00000000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 0-/* RC 1 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020
-[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000001
-[0004] Input base : 0000e000 -[0004] ID Count : 00002000 -[0004] Output Base : 0000e000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 0-/* RC 2 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020
-[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0-[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0-[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000002
-[0004] Input base : 00008000 -[0004] ID Count : 00002000 -[0004] Output Base : 00008000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000
Single Mapping : 0diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc deleted file mode 100644 index 9f60803..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc +++ /dev/null @@ -1,85 +0,0 @@ -/*
- Copyright (c) 2016 Hisilicon Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- */
-#include <IndustryStandard/Acpi.h> -#include "Pv660Platform.h"
-#define ACPI_5_0_MCFG_VERSION 0x1
-#pragma pack(1) -typedef struct -{
- UINT64 ullBaseAddress;
- UINT16 usSegGroupNum;
- UINT8 ucStartBusNum;
- UINT8 ucEndBusNum;
- UINT32 Reserved2;
-}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
-typedef struct -{
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 Reserved1;
-}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
-typedef struct -{
- EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
- EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3];
-}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; -#pragma pack()
-EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= -{
- {
{EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),ACPI_5_0_MCFG_VERSION,0x00, // Checksum will be updated at runtime{EFI_ACPI_ARM_OEM_ID},EFI_ACPI_ARM_OEM_TABLE_ID,EFI_ACPI_ARM_OEM_REVISION,EFI_ACPI_ARM_CREATOR_ID,EFI_ACPI_ARM_CREATOR_REVISION},0x0000000000000000, //Reserved- },
- {
- {
0xb0000000, //Base Address0x0, //Segment Group Number0x0, //Start Bus Number0x1f, //End Bus Number0x00000000, //Reserved- },
- {
0xb0000000, //Base Address0x1, //Segment Group Number0xe0, //Start Bus Number0xff, //End Bus Number0x00000000, //Reserved- },
- {
0xa0000000, //Base Address0x2, //Segment Group Number0x80, //Start Bus Number0x9f, //End Bus Number0x00000000, //Reserved- },
- }
-};
-// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl deleted file mode 100644 index d8d453a..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ /dev/null @@ -1,562 +0,0 @@ -/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-Scope(_SB) -{
- Device (MDIO)
- {
- OperationRegion(CLKR, SystemMemory, 0x60000338, 8)
- Field(CLKR, DWordAcc, NoLock, Preserve) {
CLKE, 1, // clock enable, 31,CLKD, 1, // clode disable, 31,- }
- OperationRegion(RSTR, SystemMemory, 0x60000A38, 8)
- Field(RSTR, DWordAcc, NoLock, Preserve) {
RSTE, 1, // reset, 31,RSTD, 1, // de-reset, 31,- }
- Name(_HID, "HISI0141")
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)})- Method(_RST, 0, Serialized) {
Store (0x1, RSTE)Sleep (10)Store (0x1, CLKD)Sleep (10)Store (0x1, RSTD)Sleep (10)Store (0x1, CLKE)Sleep (10)- }
- }
- Device (DSF0)
- {
- OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
H3ST, 1,, 31, //RESERVED}- OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
- Field(H4SR, DWordAcc, NoLock, Preserve) {
H4ST, 1,, 31, //RESERVED}- // DSAF RESET
- OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
- Field(DRER, DWordAcc, NoLock, Preserve) {
DRTE, 1,, 31, //RESERVEDDRTD, 1,, 31, //RESERVED}- // NT RESET
- OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
- Field(NRER, DWordAcc, NoLock, Preserve) {
NRTE, 1,, 31, //RESERVEDNRTD, 1,, 31, //RESERVED}- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
XRTE, 31,, 1, //RESERVEDXRTD, 31,, 1, //RESERVED}- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
GR0E, 30,, 2, //RESERVEDGR0D, 30,, 2, //RESERVEDGR1E, 18,, 14, //RESERVEDGR1D, 18,, 14, //RESERVED}- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
PRTE, 10,, 22, //RESERVEDPRTD, 10,, 22, //RESERVED}- // RCB PPE COM RESET
- OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
- Field(RRTR, DWordAcc, NoLock, Preserve) {
RRTE, 1,, 31, //RESERVEDRRTD, 1,, 31, //RESERVED}- // Hilink access sel cfg reg
- OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
- Field(HSER, DWordAcc, NoLock, Preserve) {
HSEL, 2, // hilink_access_sel & hilink_access_wr_pul, 30, // RESERVED}- // Serdes
- OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
- Field(H4LR, DWordAcc, NoLock, Preserve) {
H4L0, 16, // port0, 16, //RESERVEDOffset (0x400),H4L1, 16, // port1, 16, //RESERVEDOffset (0x800),H4L2, 16, // port2, 16, //RESERVEDOffset (0xc00),H4L3, 16, // port3, 16, //RESERVED}- OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
H3L2, 16, // port4, 16, //RESERVEDOffset (0x400),H3L3, 16, // port5, 16, //RESERVED}Name (_HID, "HISI00B2")Name (_CCA, 1) // Cache-coherent controllerName (_CRS, ResourceTemplate (){Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,){576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,){960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,){1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"mode", "6port-16rss"},Package () {"buf-size", 4096},Package () {"desc-num", 1024},Package () {"interrupt-parent", Package() {\_SB.MBI3}},}})- //reset XGE port
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XRST, 2, Serialized) {
ShiftLeft (0x2082082, Arg0, Local0)Or (Local0, 0x1, Local0)If (LEqual (Arg1, 0)) {Store(Local0, XRTE)} Else {Store(Local0, XRTD)}- }
- //reset XGE core
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XCRT, 2, Serialized) {
ShiftLeft (0x2080, Arg0, Local0)If (LEqual (Arg1, 0)) {Store(Local0, XRTE)} Else {Store(Local0, XRTD)}- }
- //reset GE port
- //Arg0 : GE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(GRST, 2, Serialized) {
If (LLessEqual (Arg0, 5)) {//Service portShiftLeft (0x2082082, Arg0, Local0)ShiftLeft (0x1, Arg0, Local1)If (LEqual (Arg1, 0)) {Store(Local1, GR1E)Store(Local0, GR0E)} Else {Store(Local0, GR0D)Store(Local1, GR1D)}}- }
- //reset PPE port
- //Arg0 : PPE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(PRST, 2, Serialized) {
ShiftLeft (0x1, Arg0, Local0)If (LEqual (Arg1, 0)) {Store(Local0, PRTE)} Else {Store(Local0, PRTD)}- }
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 2, Serialized) {
ShiftLeft (Arg1, 10, Local0)Switch (ToInteger(Arg0)){case (0x0){Store (0, HSEL)Store (H4L0, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H4L0)}case (0x1){Store (0, HSEL)Store (H4L1, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H4L1)}case (0x2){Store (0, HSEL)Store (H4L2, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H4L2)}case (0x3){Store (0, HSEL)Store (H4L3, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H4L3)}case (0x4){Store (3, HSEL)Store (H3L2, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H3L2)}case (0x5){Store (3, HSEL)Store (H3L3, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H3L3)}}- }
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
- //Arg1 : port
- //Arg2 : 0 disable, 1 enable
- Method(DRST, 3, Serialized)
- {
Switch (ToInteger(Arg0)){//DSAF resetcase (0x1){Store (Arg2, Local0)If (LEqual (Local0, 0)){Store (0x1, DRTE)Store (0x1, NRTE)Sleep (10)Store (0x1, RRTE)}Else{Store (0x1, DRTD)Store (0x1, NRTD)Sleep (10)Store (0x1, RRTD)}}//Reset PPE portcase (0x2){Store (Arg1, Local0)Store (Arg2, Local1)PRST (Local0, Local1)}//Reset XGE corecase (0x3){Store (Arg1, Local0)Store (Arg2, Local1)XCRT (Local0, Local1)}//Reset XGE portcase (0x4){Store (Arg1, Local0)Store (Arg2, Local1)XRST (Local0, Local1)}//Reset GE portcase (0x5){Store (Arg1, Local0)Store (Arg2, Local1)GRST (Local0, Local1)}}- }
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset Sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
- // Arg3[1] : port index in dsaf
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : port
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : port
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : port index in dsaf
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : port index in dsaf
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))){If (LEqual (Arg1, 0x00)){Switch (ToInteger(Arg2)){case (0x0){Return (Buffer () {0x3F})}//Reset Sequencecase (0x1){Store (DeRefOf (Index (Arg3, 0)), Local0)Store (DeRefOf (Index (Arg3, 1)), Local1)Store (DeRefOf (Index (Arg3, 2)), Local2)DRST (Local0, Local1, Local2)}//Set Serdes Loopbackcase (0x2){Store (DeRefOf (Index (Arg3, 0)), Local0)Store (DeRefOf (Index (Arg3, 1)), Local1)SRLP (Local0, Local1)}//LED op setcase (0x3){}// Get port type (GE or XGE)case (0x4){Store (0, Local1)Store (DeRefOf (Index (Arg3, 0)), Local0)If (LLessEqual (Local0, 3)){// mac0: Hilink4 Lane0// mac1: Hilink4 Lane1// mac2: Hilink4 Lane2// mac3: Hilink4 Lane3Store (H4ST, Local1)}ElseIf (LLessEqual (Local0, 5)){// mac4: Hilink3 Lane2// mac5: Hilink3 Lane3Store (H3ST, Local1)}Return (Local1)}//Get sfp statuscase (0x5){}}}}Return (Buffer() {0x00})- }
- Device (PRT0)
- {
Name (_ADR, 0x0)Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"reg", 0},Package () {"media-type", "fiber"},}})- }
- Device (PRT1)
- {
Name (_ADR, 0x1)Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"reg", 1},Package () {"media-type", "fiber"},}})- }
- Device (PRT4)
- {
Name (_ADR, 0x4)Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"reg", 4},Package () {"phy-mode", "sgmii"},Package () {"phy-addr", 0},Package () {"mdio-node", Package (){\_SB.MDIO}},Package () {"media-type", "copper"},}})- }
- Device (PRT5)
- {
Name (_ADR, 0x5)Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"reg", 5},Package () {"phy-mode", "sgmii"},Package () {"phy-addr", 1},Package () {"mdio-node", Package (){\_SB.MDIO}},Package () {"media-type", "copper"},}})- }
- }
- Device (ETH4) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytesPackage () {"ae-handle", Package (){\_SB.DSF0}},Package () {"port-idx-in-ae", 4},}- })
- }
- Device (ETH5) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytesPackage () {"ae-handle", Package (){\_SB.DSF0}},Package () {"port-idx-in-ae", 5},}- })
- }
- Device (ETH0) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytesPackage () {"ae-handle", Package (){\_SB.DSF0}},Package () {"port-idx-in-ae", 0},}- })
- }
- Device (ETH1) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytesPackage () {"ae-handle", Package (){\_SB.DSF0}},Package () {"port-idx-in-ae", 1},}- })
- }
-} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl deleted file mode 100644 index 4eaa073..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl +++ /dev/null @@ -1,125 +0,0 @@ -/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-Scope(_SB) -{
- // Mbi-gen pcie subsys
- Device(MBI0) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 2}}- })
- }
- // Mbi-gen sas1 intc
- Device(MBI1) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 128}}- })
- }
- Device(MBI2) { // Mbi-gen sas2 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 128}}- })
- }
- Device(MBI3) { // Mbi-gen dsa0 srv intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 409}}- })
- }
- Device(MBI4) { // Mbi-gen dsa1 dbg0 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 9}}- })
- }
- Device(MBI5) { // Mbi-gen dsa2 dbg1 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 9}}- })
- }
- Device(MBI6) { // Mbi-gen dsa sas0 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 128}}- })
- }
-} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl deleted file mode 100644 index 573c0a3..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl +++ /dev/null @@ -1,261 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/
-//#include "ArmPlatform.h" -Scope(_SB) -{
- // PCIe Root bus
- Device (PCI0)
- {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0) // Segment of this Root complex
- Name(_BBN, 0) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {WordBusNumber ( // Bus numbers assigned to this rootResourceProducer, MinFixed, MaxFixed, PosDecode,0, // AddressGranularity0x0, // AddressMinimum - Minimum Bus Number0x1f, // AddressMaximum - Maximum Bus Number0, // AddressTranslation - Set to 00x20 // RangeLength - Number of Busses)QWordMemory ( // 64-bit BAR WindowsResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,ReadWrite,0x0, // Granularity0xb2000000, // Min Base Address pci address0xb7feffff, // Max Base Address0x0, // Translate0x5ff0000 // Length)QWordIO (ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,0x0, // Granularity0x0, // Min Base Address0xffff, // Max Base Address0xb7ff0000, // Translate0x10000 // Length)}) // Name(RBUF)Return (RBUF)- } // Method(_CRS)
- Device (RES0)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base addressName (_CRS, ResourceTemplate (){Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)})- }
- OperationRegion(SCTR, SystemMemory, 0xa009131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- }
- } // Device(PCI0)
- // PCIe Root bus
- Device (PCI1)
- {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 1) // Segment of this Root complex
- Name(_BBN, 0xe0) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {WordBusNumber ( // Bus numbers assigned to this rootResourceProducer, MinFixed, MaxFixed, PosDecode,0, // AddressGranularity0xe0, // AddressMinimum - Minimum Bus Number0xff, // AddressMaximum - Maximum Bus Number0, // AddressTranslation - Set to 00x20 // RangeLength - Number of Busses)QWordMemory ( // 64-bit BAR WindowsResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,ReadWrite,0x0, // Granularity0xb8000000, // Min Base Address pci address0xbdfeffff, // Max Base Address0x0, // Translate0x5ff0000 // Length)QWordIO (ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,0x0, // Granularity0x0, // Min Base Address0xffff, // Max Base Address0xbdff0000, // Translate0x10000 // Length)}) // Name(RBUF)Return (RBUF)- } // Method(_CRS)
- Device (RES1)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base addressName (_CRS, ResourceTemplate (){Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)})- }
- OperationRegion(SCTR, SystemMemory, 0xa020131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- }
- } // Device(PCI1)
- // PCIe Root bus
- Device (PCI2)
- {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 2) // Segment of this Root complex
- Name(_BBN, 0x80) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {WordBusNumber ( // Bus numbers assigned to this rootResourceProducer, MinFixed, MaxFixed, PosDecode,0, // AddressGranularity0x80, // AddressMinimum - Minimum Bus Number0x9f, // AddressMaximum - Maximum Bus Number0, // AddressTranslation - Set to 00x20 // RangeLength - Number of Busses)QWordMemory ( // 64-bit BAR WindowsResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,ReadWrite,0x0, // Granularity0xaa000000, // Min Base Address0xaffeffff, // Max Base Address0x0, // Translate0x5ff0000 // Length)QWordIO (ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,0x0, // Granularity0x0, // Min Base Address0xffff, // Max Base Address0xafff0000, // Translate0x10000 // Length)}) // Name(RBUF)Return (RBUF)- } // Method(_CRS)
- Device (RES2)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base addressName (_CRS, ResourceTemplate (){Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)})- }
- OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))){switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- }
- } // Device(PCI2)
-}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl deleted file mode 100644 index ce8ccd6..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl +++ /dev/null @@ -1,247 +0,0 @@ -/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-Scope(_SB) -{
- Device(SAS0) {
Name(_HID, "HISI0162")- Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ){601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI6}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},Package () {"queue-count", 16},Package () {"phy-count", 8},}})- OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x338),CLK, 32,CLKD, 32,Offset (0xa60),RST, 32,DRST, 32,Offset (0x5a30),STS, 32,- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)Store(0x7ffff, CLKD)Sleep(1)Store(0x7ffff, DRST)Store(0x7ffff, CLK)Sleep(1)- }
- }
- Device(SAS1) {
Name(_HID, "HISI0162")- Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ){576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI1}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 16},Package () {"phy-count", 8},Package () {"hip06-sas-v2-quirk-amt", 1},}})- OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x318),CLK, 32,CLKD, 32,Offset (0xa18),RST, 32,DRST, 32,Offset (0x5a0c),STS, 32,- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)Store(0x7ffff, CLKD)Sleep(1)Store(0x7ffff, DRST)Store(0x7ffff, CLK)Sleep(1)- }
- }
- Device(SAS2) {
Name(_HID, "HISI0162")- Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ){608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI2}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 16},Package () {"phy-count", 8},}})- OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x3a8),CLK, 32,CLKD, 32,Offset (0xae0),RST, 32,DRST, 32,Offset (0x5a70),STS, 32,- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)Store(0x7ffff, CLKD)Sleep(1)Store(0x7ffff, DRST)Store(0x7ffff, CLK)Sleep(1)- }
- }
-} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl deleted file mode 100644 index 28ba03d..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl +++ /dev/null @@ -1,136 +0,0 @@ -/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-**/
-//#include "ArmPlatform.h" -Scope(_SB) -{
- Device (USB0)
{Name (_HID, "PNP0D20") // _HID: Hardware IDName (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible IDName (_CCA, One) // _CCA: Cache Coherency AttributeMethod (_CRS, 0, Serialized) // _CRS: Current Resource Settings{Name (RBUF, ResourceTemplate (){Memory32Fixed (ReadWrite,0xa7020000, // Address Base0x00010000, // Address Length)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){0x00000041,}})Return (RBUF) /* \_SB_.USB0._CRS.RBUF */}Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"interrupt-parent",Package() {\_SB.MBI0}}}})Device (RHUB){Name (_ADR, Zero) // _ADR: AddressDevice (PRT1){Name (_ADR, One) // _ADR: AddressName (_UPC, Package (0x04) // _UPC: USB Port Capabilities{0xFF,Zero,Zero,Zero})Name (_PLD, Package (0x01) // _PLD: Physical Location of Device{ToPLD (PLD_Revision = 0x1,PLD_IgnoreColor = 0x1,PLD_Red = 0x0,PLD_Green = 0x0,PLD_Blue = 0x0,PLD_Width = 0x0,PLD_Height = 0x0,PLD_UserVisible = 0x1,PLD_Dock = 0x0,PLD_Lid = 0x0,PLD_Panel = "UNKNOWN",PLD_VerticalPosition = "UPPER",PLD_HorizontalPosition = "LEFT",PLD_Shape = "UNKNOWN",PLD_GroupOrientation = 0x0,PLD_GroupToken = 0x0,PLD_GroupPosition = 0x0,PLD_Bay = 0x0,PLD_Ejectable = 0x0,PLD_EjectRequired = 0x0,PLD_CabinetNumber = 0x0,PLD_CardCageNumber = 0x0,PLD_Reference = 0x0,PLD_Rotation = 0x0,PLD_Order = 0x0,PLD_VerticalOffset = 0x0,PLD_HorizontalOffset = 0x0)})}Device (PRT2){Name (_ADR, 0x02) // _ADR: AddressName (_UPC, Package (0x04) // _UPC: USB Port Capabilities{Zero,0xFF,Zero,Zero})}Device (PRT3){Name (_ADR, 0x03) // _ADR: AddressName (_UPC, Package (0x04) // _UPC: USB Port Capabilities{Zero,0xFF,Zero,Zero})}Device (PRT4){Name (_ADR, 0x04) // _ADR: AddressName (_UPC, Package (0x04) // _UPC: USB Port Capabilities{Zero,0xFF,Zero,Zero})}}}-}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl index ce5a085..f156e1b 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl @@ -18,7 +18,7 @@ #include "Pv660Platform.h" -DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI-D02", EFI_ACPI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI0660", EFI_ACPI_ARM_OEM_REVISION) { include ("Mbig.asl") include ("CPU.asl") include ("Com.asl") diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl deleted file mode 100644 index 06c05aa..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl +++ /dev/null @@ -1,29 +0,0 @@ -/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-**/
-#include "Pv660Platform.h"
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI-EVB", EFI_ACPI_ARM_OEM_REVISION) {
include ("Lpc.asl")include ("D03Mbig.asl")include ("CPU.asl")include ("D03Usb.asl")include ("D03Hns.asl")include ("D03Sas.asl")include ("D03Pci.asl")-} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl deleted file mode 100644 index 0965afc..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl +++ /dev/null @@ -1,25 +0,0 @@ -/** @file -* -* Copyright (c) 2016 Hisilicon Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/
-// -// LPC -//
-Device (LPC0) -{
- Name(_HID, "HISI0191") // HiSi LPC
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
- })
-} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl deleted file mode 100644 index 4c3c642..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl +++ /dev/null @@ -1,152 +0,0 @@ -/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-Scope(_SB) -{
- Device(SAS0) {
Name(_HID, "HISI0161")- Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xc1000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){//phy irq(0~79)259,263,264,269,273,274,279,283,284,289,293,294,299,303,304,309,313,314,319,323,324,329,333,334,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ){//cq irq (80~111)336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,}Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){376, //chip fatal error irq(120)381, //chip fatal error irq(125)}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI1}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x0a}},Package () {"queue-count", 32},Package () {"phy-count", 8},}})- OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x338),CLK, 32,CLKD, 32,Offset (0xa60),RST, 32,DRST, 32,Offset (0x5a30),STS, 32,- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)Store(0x7ffff, CLKD)Sleep(1)Store(0x7ffff, DRST)Store(0x7ffff, CLK)Sleep(1)- }
- }
- Device(SAS1) {
Name(_HID, "HISI0161")- Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xb1000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){//phy irq(0~79)259,263,264,269,273,274,279,283,284,289,293,294,299,303,304,309,313,314,319,323,324,329,333,334,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ){//cq irq (80~111)336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,}Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){376, //chip fatal error irq(120)381, //chip fatal error irq(125)}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI3}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 32},Package () {"phy-count", 8},}})- OperationRegion (CTL, SystemMemory, 0xB0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x318),CLK, 32,CLKD, 32,Offset (0xa18),RST, 32,DRST, 32,Offset (0x5a0c),STS, 32,- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)Store(0x7ffff, CLKD)Sleep(1)Store(0x7ffff, DRST)Store(0x7ffff, CLK)Sleep(1)- }
- }
-} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl deleted file mode 100644 index 9ad2d96..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl +++ /dev/null @@ -1,39 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/
-// -// SATA AHCI -//
-Device (AHCI) -{
- Name(_HID, "HISI0001") // HiSi AHCI
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xb1002800, 0x00000B00)
- Memory32Fixed (ReadWrite, 0xb1000000, 0x00002800)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 382 }
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
Package () {"interrupt-parent",Package() {\_SB.MBI3}}- }
- })
-} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index 44056b5..9ba3d55 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -10,11 +10,11 @@ [0004] Table Length : 0000010C [0001] Revision : 00 [0001] Checksum : BC -[0006] Oem ID : "INTEL " -[0008] Oem Table ID : "TEMPLATE" +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HISI0660" [0004] Oem Revision : 00000000 [0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20150410 +[0004] Asl Compiler Revision : 20151124 [0004] Node Count : 0000000A [0004] Node Offset : 00000034 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc deleted file mode 100644 index 6e8557e..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc +++ /dev/null @@ -1,128 +0,0 @@ -/** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/
-#include "Pv660Platform.h"
-#include <Library/AcpiLib.h> -#include <Library/ArmLib.h> -#include <Library/PcdLib.h> -#include <IndustryStandard/Acpi.h> -#include <Library/AcpiNextLib.h>
-// Differs from Juno, we have another affinity level beyond cluster and core -// 0x20000 is only for socket 0 -#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId))
-// -// Multiple APIC Description Table -// -#pragma pack (1)
-typedef struct {
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16];
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1];
-} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
-#pragma pack ()
-EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
- {
- ARM_ACPI_HEADER (
EFI_ACPI_1_0_APIC_SIGNATURE,EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION- ),
- //
- // MADT specific fields
- //
- 0, // LocalApicAddress
- 0, // Flags
- },
- {
- // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
- // GsivId, GicRBase, Mpidr)
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
- // ACPI v5.1).
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */),- },
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4),
- {
- EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000),
- }
-};
-// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h index 5af8f1a..3d69d96 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h @@ -24,10 +24,10 @@ // ACPI table information used to initialize tables. // #define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','-','D','0','2') // OEM table id 8 bytes long -#define EFI_ACPI_ARM_OEM_REVISION 0x20140727 -#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('H','I','S','I') -#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099 +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','0','6','6','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 // A macro to initialise the common header part of EFI ACPI tables as defined by // EFI_ACPI_DESCRIPTION_HEADER structure. diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc deleted file mode 100644 index 2fa2959..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc +++ /dev/null @@ -1,81 +0,0 @@ -/*
- Copyright (c) 2013 Linaro Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- Contributors:
Yi Li - yi.li@linaro.org-*/
-#include <IndustryStandard/Acpi.h> -#include "Pv660Platform.h"
-#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014
-#pragma pack(1) -typedef struct {
- UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
-} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
-typedef struct {
- EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header;
- EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
-} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE; -#pragma pack()
-// -// System Locality Information Table -// Please modify all values in Slit.h only. -// -EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
- {
- {
EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE),EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,0x00, // Checksum will be updated at runtime{EFI_ACPI_ARM_OEM_ID},EFI_ACPI_ARM_OEM_TABLE_ID,EFI_ACPI_ARM_OEM_REVISION,EFI_ACPI_ARM_CREATOR_ID,EFI_ACPI_ARM_CREATOR_REVISION,- },
- //
- // Beginning of SLIT specific fields
- //
- EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
- },
- {
- {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality 0
- {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality 1
- {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality 2
- {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality 3
- {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality 4
- {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality 5
- {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality 6
- {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality 7
- {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality 8
- {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality 9
- {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality 10
- {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality 11
- {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality 12
- {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality 13
- {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality 14
- {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality 15
- {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality 16
- {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality 17
- {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality 18
- {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality 19
- },
-};
-// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Slit;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc deleted file mode 100644 index 1d38191..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc +++ /dev/null @@ -1,115 +0,0 @@ -/*
- Copyright (c) 2013 Linaro Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- Contributors:
Yi Li - yi.li@linaro.org
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*/
-#include <IndustryStandard/Acpi.h> -#include "Pv660Platform.h" -#include <Library/AcpiLib.h> -#include <Library/AcpiNextLib.h>
-// -// Define the number of each table type. -// This is where the table layout is modified. -// -#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT 4 -#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 4
-#pragma pack(1) -typedef struct {
- EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
- EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE Apic;
- EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE Memory[2];
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE GICC[16];
-} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE;
-#pragma pack()
-// -// Static Resource Affinity Table definition -// -EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = {
- {
- {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
- sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE),
- EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
- 0x00, // Checksum will be updated at runtime
- {EFI_ACPI_ARM_OEM_ID},
- EFI_ACPI_ARM_OEM_TABLE_ID,
- EFI_ACPI_ARM_OEM_REVISION,
- EFI_ACPI_ARM_CREATOR_ID,
- EFI_ACPI_ARM_CREATOR_REVISION},
- /*Reserved*/
- 0x00000001, // Reserved to be 1 for backward compatibility
- EFI_ACPI_RESERVED_QWORD
- },
- /**/
- {
0x00, // Subtable Type:Processor Local APIC/SAPIC Affinitysizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE), //Length0x00, //Proximity Domain Low(8)0x00, //Apic ID0x00000001, //Flags0x00, //Local Sapic EID{0,0,0}, //Proximity Domain High(24)0x00000000, //ClockDomain- },
- //
- //
- // Memory Affinity
- //
- {
- EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001),
- EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001),
- },
- /*Processor Local x2APIC Affinity*/
- //{
- // 0x02, // Subtable Type:Processor Local x2APIC Affinity
- // sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE),
- // {0,0}, //Reserved1
- // 0x00000000, //Proximity Domain
- // 0x00000000, //Apic ID
- // 0x00000001, //Flags
- // 0x00000000, //Clock Domain
- // {0,0,0,0}, //Reserved2
- //},
- {
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000) //GICC Affinity Processor 15
- },
-};
-// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Srat;
-- 1.9.1
Set all ACPI tables ID as below:
EFI_ACPI_ARM_OEM_ID HISI EFI_ACPI_ARM_OEM_TABLE_ID HISI1610 EFI_ACPI_ARM_OEM_REVISION 0x00000000 EFI_ACPI_ARM_CREATOR_ID INTL EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com --- .../Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf | 56 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 337 ++++++++++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 85 ++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl | 88 ++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 36 ++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 562 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 125 +++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 261 ++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 247 +++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 136 +++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 29 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 67 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 91 ++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 96 ++++ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 48 ++ .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 128 +++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc | 81 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc | 115 +++++ Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- 21 files changed, 2615 insertions(+), 2 deletions(-) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf new file mode 100644 index 0000000..b6be3d9 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf @@ -0,0 +1,56 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Hi1610AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt/DsdtHi1610.asl + Facs.aslc + Fadt.aslc + Gtdt.aslc + MadtHi1610.aslc + D03Mcfg.aslc + D03Iort.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl new file mode 100644 index 0000000..e02b4d5 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -0,0 +1,337 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20151124-64 + * Copyright (c) 2000 - 2015 Intel Corporation + * + * Template for [IORT] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 0000029e +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HISI1610" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124 + +[0004] Node Count : 00000008 +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00 + +/* ITS 0, for dsa */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 + +/* mbi-gen dsa mbi0 - usb, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0017] Device Name : "_SB_.MBI0" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040080 // device id +[0004] Output Reference : 00000034 // point to its dsa +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi1 - sas1, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI1" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi2 - sas2, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI2" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040040 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi3 - dsa0, srv named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI3" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040800 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI4" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1c +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI5" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1d +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi6 - dsa sas0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI6" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040900 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* RC 0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000000 + +[0004] Input base : 00000000 +[0004] ID Count : 00002000 +[0004] Output Base : 00000000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* RC 1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000001 + +[0004] Input base : 0000e000 +[0004] ID Count : 00002000 +[0004] Output Base : 0000e000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* RC 2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002 + +[0004] Input base : 00008000 +[0004] ID Count : 00002000 +[0004] Output Base : 00008000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc new file mode 100644 index 0000000..ed47a44 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2016 Hisilicon Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + */ + +#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h" + +#define ACPI_5_0_MCFG_VERSION 0x1 + +#pragma pack(1) +typedef struct +{ + UINT64 ullBaseAddress; + UINT16 usSegGroupNum; + UINT8 ucStartBusNum; + UINT8 ucEndBusNum; + UINT32 Reserved2; +}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; + +typedef struct +{ + EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3]; +}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack() + +EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{ + { + { + EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_5_0_MCFG_VERSION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION + }, + 0x0000000000000000, //Reserved + }, + { + + { + 0xb0000000, //Base Address + 0x0, //Segment Group Number + 0x0, //Start Bus Number + 0x1f, //End Bus Number + 0x00000000, //Reserved + }, + { + 0xb0000000, //Base Address + 0x1, //Segment Group Number + 0xe0, //Start Bus Number + 0xff, //End Bus Number + 0x00000000, //Reserved + }, + { + 0xa0000000, //Base Address + 0x2, //Segment Group Number + 0x80, //Start Bus Number + 0x9f, //End Bus Number + 0x00000000, //Reserved + }, + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000..e995295 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,88 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + // + // A57x16 Processor declaration + // + Device(CPU0) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + Device(CPU1) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + Device(CPU2) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + Device(CPU3) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + Device(CPU4) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + Device(CPU5) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + Device(CPU6) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + Device(CPU7) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } + Device(CPU8) { + Name(_HID, "ACPI0007") + Name(_UID, 8) + } + Device(CPU9) { + Name(_HID, "ACPI0007") + Name(_UID, 9) + } + Device(CP10) { + Name(_HID, "ACPI0007") + Name(_UID, 10) + } + Device(CP11) { + Name(_HID, "ACPI0007") + Name(_UID, 11) + } + Device(CP12) { + Name(_HID, "ACPI0007") + Name(_UID, 12) + } + Device(CP13) { + Name(_HID, "ACPI0007") + Name(_UID, 13) + } + Device(CP14) { + Name(_HID, "ACPI0007") + Name(_UID, 14) + } + Device(CP15) { + Name(_HID, "ACPI0007") + Name(_UID, 15) + } +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000..3bcc5fb --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl @@ -0,0 +1,36 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + Device(COM0) { + Name(_HID, "HISI0031") //it is not 16550 compatible + Name(_CID, "8250dw") + Name(_UID, Zero) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x80300000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-frequency", 200000000}, + } + }) + } +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl new file mode 100644 index 0000000..d8d453a --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -0,0 +1,562 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + Device (MDIO) + { + OperationRegion(CLKR, SystemMemory, 0x60000338, 8) + Field(CLKR, DWordAcc, NoLock, Preserve) { + CLKE, 1, // clock enable + , 31, + CLKD, 1, // clode disable + , 31, + } + OperationRegion(RSTR, SystemMemory, 0x60000A38, 8) + Field(RSTR, DWordAcc, NoLock, Preserve) { + RSTE, 1, // reset + , 31, + RSTD, 1, // de-reset + , 31, + } + + Name(_HID, "HISI0141") + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000) + }) + + Method(_RST, 0, Serialized) { + Store (0x1, RSTE) + Sleep (10) + Store (0x1, CLKD) + Sleep (10) + Store (0x1, RSTD) + Sleep (10) + Store (0x1, CLKE) + Sleep (10) + } + } + + Device (DSF0) + { + OperationRegion(H3SR, SystemMemory, 0xC0000184, 4) + Field(H3SR, DWordAcc, NoLock, Preserve) { + H3ST, 1, + , 31, //RESERVED + } + OperationRegion(H4SR, SystemMemory, 0xC0000194, 4) + Field(H4SR, DWordAcc, NoLock, Preserve) { + H4ST, 1, + , 31, //RESERVED + } + // DSAF RESET + OperationRegion(DRER, SystemMemory, 0xC0000A00, 8) + Field(DRER, DWordAcc, NoLock, Preserve) { + DRTE, 1, + , 31, //RESERVED + DRTD, 1, + , 31, //RESERVED + } + // NT RESET + OperationRegion(NRER, SystemMemory, 0xC0000A08, 8) + Field(NRER, DWordAcc, NoLock, Preserve) { + NRTE, 1, + , 31, //RESERVED + NRTD, 1, + , 31, //RESERVED + } + // XGE RESET + OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) + Field(XRER, DWordAcc, NoLock, Preserve) { + XRTE, 31, + , 1, //RESERVED + XRTD, 31, + , 1, //RESERVED + } + + // GE RESET + OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) + Field(GRTR, DWordAcc, NoLock, Preserve) { + GR0E, 30, + , 2, //RESERVED + GR0D, 30, + , 2, //RESERVED + GR1E, 18, + , 14, //RESERVED + GR1D, 18, + , 14, //RESERVED + } + // PPE RESET + OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) + Field(PRTR, DWordAcc, NoLock, Preserve) { + PRTE, 10, + , 22, //RESERVED + PRTD, 10, + , 22, //RESERVED + } + + // RCB PPE COM RESET + OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8) + Field(RRTR, DWordAcc, NoLock, Preserve) { + RRTE, 1, + , 31, //RESERVED + RRTD, 1, + , 31, //RESERVED + } + + // Hilink access sel cfg reg + OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) + Field(HSER, DWordAcc, NoLock, Preserve) { + HSEL, 2, // hilink_access_sel & hilink_access_wr_pul + , 30, // RESERVED + } + + // Serdes + OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) + Field(H4LR, DWordAcc, NoLock, Preserve) { + H4L0, 16, // port0 + , 16, //RESERVED + Offset (0x400), + H4L1, 16, // port1 + , 16, //RESERVED + Offset (0x800), + H4L2, 16, // port2 + , 16, //RESERVED + Offset (0xc00), + H4L3, 16, // port3 + , 16, //RESERVED + } + OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) + Field(H3LR, DWordAcc, NoLock, Preserve) { + H3L2, 16, // port4 + , 16, //RESERVED + Offset (0x400), + H3L3, 16, // port5 + , 16, //RESERVED + } + Name (_HID, "HISI00B2") + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) + Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"mode", "6port-16rss"}, + Package () {"buf-size", 4096}, + Package () {"desc-num", 1024}, + Package () {"interrupt-parent", Package() {_SB.MBI3}}, + } + }) + + //reset XGE port + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XRST, 2, Serialized) { + ShiftLeft (0x2082082, Arg0, Local0) + Or (Local0, 0x1, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset XGE core + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XCRT, 2, Serialized) { + ShiftLeft (0x2080, Arg0, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset GE port + //Arg0 : GE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(GRST, 2, Serialized) { + If (LLessEqual (Arg0, 5)) { + //Service port + ShiftLeft (0x2082082, Arg0, Local0) + ShiftLeft (0x1, Arg0, Local1) + + If (LEqual (Arg1, 0)) { + Store(Local1, GR1E) + Store(Local0, GR0E) + } Else { + Store(Local0, GR0D) + Store(Local1, GR1D) + } + } + } + + //reset PPE port + //Arg0 : PPE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(PRST, 2, Serialized) { + ShiftLeft (0x1, Arg0, Local0) + If (LEqual (Arg1, 0)) { + Store(Local0, PRTE) + } Else { + Store(Local0, PRTD) + } + } + + // Set Serdes Loopback + //Arg0 : port + //Arg1 : 0 disable, 1 enable + Method(SRLP, 2, Serialized) { + ShiftLeft (Arg1, 10, Local0) + Switch (ToInteger(Arg0)) + { + case (0x0){ + Store (0, HSEL) + Store (H4L0, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L0) + } + case (0x1){ + Store (0, HSEL) + Store (H4L1, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L1) + } + case (0x2){ + Store (0, HSEL) + Store (H4L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L2) + } + case (0x3){ + Store (0, HSEL) + Store (H4L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L3) + } + case (0x4){ + Store (3, HSEL) + Store (H3L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L2) + } + case (0x5){ + Store (3, HSEL) + Store (H3L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L3) + } + } + } + + //Reset + //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) + //Arg1 : port + //Arg2 : 0 disable, 1 enable + Method(DRST, 3, Serialized) + { + Switch (ToInteger(Arg0)) + { + //DSAF reset + case (0x1) + { + Store (Arg2, Local0) + If (LEqual (Local0, 0)) + { + Store (0x1, DRTE) + Store (0x1, NRTE) + Sleep (10) + Store (0x1, RRTE) + } + Else + { + Store (0x1, DRTD) + Store (0x1, NRTD) + Sleep (10) + Store (0x1, RRTD) + } + } + //Reset PPE port + case (0x2) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + PRST (Local0, Local1) + } + + //Reset XGE core + case (0x3) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XCRT (Local0, Local1) + } + //Reset XGE port + case (0x4) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XRST (Local0, Local1) + } + + //Reset GE port + case (0x5) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + GRST (Local0, Local1) + } + } + } + + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // 0 : Return Supported Functions bit mask + // 1 : Reset Sequence + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) + // Arg3[1] : port index in dsaf + // Arg3[2] : 0 reset, 1 cancle reset + // 2 : Set Serdes Loopback + // Arg3[0] : port + // Arg3[1] : 0 disable, 1 enable + // 3 : LED op set + // Arg3[0] : op type + // Arg3[1] : port + // Arg3[2] : para + // 4 : Get port type (GE or XGE) + // Arg3[0] : port index in dsaf + // Return : 0 GE, 1 XGE + // 5 : Get sfp status + // Arg3[0] : port index in dsaf + // Return : 0 no sfp, 1 have sfp + // Arg3: Package Parameters + Method (_DSM, 4, Serialized) + { + If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) + { + If (LEqual (Arg1, 0x00)) + { + Switch (ToInteger(Arg2)) + { + case (0x0) + { + Return (Buffer () {0x3F}) + } + + //Reset Sequence + case (0x1) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + Store (DeRefOf (Index (Arg3, 2)), Local2) + DRST (Local0, Local1, Local2) + } + + //Set Serdes Loopback + case (0x2) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + SRLP (Local0, Local1) + } + + //LED op set + case (0x3) + { + + } + + // Get port type (GE or XGE) + case (0x4) + { + Store (0, Local1) + Store (DeRefOf (Index (Arg3, 0)), Local0) + If (LLessEqual (Local0, 3)) + { + // mac0: Hilink4 Lane0 + // mac1: Hilink4 Lane1 + // mac2: Hilink4 Lane2 + // mac3: Hilink4 Lane3 + Store (H4ST, Local1) + } + ElseIf (LLessEqual (Local0, 5)) + { + // mac4: Hilink3 Lane2 + // mac5: Hilink3 Lane3 + Store (H3ST, Local1) + } + + Return (Local1) + } + + //Get sfp status + case (0x5) + { + + } + } + } + } + Return (Buffer() {0x00}) + } + Device (PRT0) + { + Name (_ADR, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 0}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT1) + { + Name (_ADR, 0x1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 1}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT4) + { + Name (_ADR, 0x4) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 4}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 0}, + Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, + } + }) + } + Device (PRT5) + { + Name (_ADR, 0x5) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 5}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 1}, + Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, + } + }) + } + } + Device (ETH4) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 4}, + } + }) + } + Device (ETH5) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 5}, + } + }) + } + Device (ETH0) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 0}, + } + }) + } + Device (ETH1) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 1}, + } + }) + } + +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl new file mode 100644 index 0000000..4eaa073 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -0,0 +1,125 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + // Mbi-gen pcie subsys + Device(MBI0) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 2} + } + }) + } + + // Mbi-gen sas1 intc + Device(MBI1) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + + Device(MBI2) { // Mbi-gen sas2 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + + Device(MBI3) { // Mbi-gen dsa0 srv intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 409} + } + }) + } + + Device(MBI4) { // Mbi-gen dsa1 dbg0 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 9} + } + }) + } + + Device(MBI5) { // Mbi-gen dsa2 dbg1 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 9} + } + }) + } + + Device(MBI6) { // Mbi-gen dsa sas0 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl new file mode 100644 index 0000000..573c0a3 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl @@ -0,0 +1,261 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +//#include "ArmPlatform.h" +Scope(_SB) +{ + // PCIe Root bus + Device (PCI0) + { + Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 0) // Segment of this Root complex + Name(_BBN, 0) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x0, // AddressMinimum - Minimum Bus Number + 0x1f, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x20 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xb2000000, // Min Base Address pci address + 0xb7feffff, // Max Base Address + 0x0, // Translate + 0x5ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0xb7ff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000) + }) + } + + OperationRegion(SCTR, SystemMemory, 0xa009131c, 4) + Field(SCTR, AnyAcc, NoLock, Preserve) { + LSTA, 32, + } + Method(_DSM, 0x4, Serialized) { + If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { + switch(ToInteger(Arg2)) + { + // Function 0: Return LinkStatus + case(0) { + Store (0, Local0) + Store (LSTA, Local0) + Return (Local0) + } + default { + } + } + } + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return(Buffer(){0}) + } + } // Device(PCI0) + + // PCIe Root bus + Device (PCI1) + { + Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 1) // Segment of this Root complex + Name(_BBN, 0xe0) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0xe0, // AddressMinimum - Minimum Bus Number + 0xff, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x20 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xb8000000, // Min Base Address pci address + 0xbdfeffff, // Max Base Address + 0x0, // Translate + 0x5ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0xbdff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + + Device (RES1) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) + }) + } + + OperationRegion(SCTR, SystemMemory, 0xa020131c, 4) + Field(SCTR, AnyAcc, NoLock, Preserve) { + LSTA, 32, + } + Method(_DSM, 0x4, Serialized) { + If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { + + switch(ToInteger(Arg2)) + { + // Function 0: Return LinkStatus + case(0) { + Store (0, Local0) + Store (LSTA, Local0) + Return (Local0) + } + default { + } + } + } + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return(Buffer(){0}) + } + } // Device(PCI1) + + // PCIe Root bus + Device (PCI2) + { + Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 2) // Segment of this Root complex + Name(_BBN, 0x80) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x80, // AddressMinimum - Minimum Bus Number + 0x9f, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x20 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xaa000000, // Min Base Address + 0xaffeffff, // Max Base Address + 0x0, // Translate + 0x5ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0xafff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) + }) + } + + OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4) + Field(SCTR, AnyAcc, NoLock, Preserve) { + LSTA, 32, + } + Method(_DSM, 0x4, Serialized) { + If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) + { + switch(ToInteger(Arg2)) + { + // Function 0: Return LinkStatus + case(0) { + Store (0, Local0) + Store (LSTA, Local0) + Return (Local0) + } + default { + } + } + } + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return(Buffer(){0}) + } + } // Device(PCI2) +} + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl new file mode 100644 index 0000000..ce8ccd6 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -0,0 +1,247 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + Device(SAS0) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI6}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x338), + CLK, 32, + CLKD, 32, + Offset (0xa60), + RST, 32, + DRST, 32, + Offset (0x5a30), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + + Device(SAS1) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) + + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI1}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + Package () {"hip06-sas-v2-quirk-amt", 1}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x318), + CLK, 32, + CLKD, 32, + Offset (0xa18), + RST, 32, + DRST, 32, + Offset (0x5a0c), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + + Device(SAS2) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) + + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI2}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x3a8), + CLK, 32, + CLKD, 32, + Offset (0xae0), + RST, 32, + DRST, 32, + Offset (0x5a70), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl new file mode 100644 index 0000000..28ba03d --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -0,0 +1,136 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +//#include "ArmPlatform.h" +Scope(_SB) +{ + Device (USB0) + { + Name (_HID, "PNP0D20") // _HID: Hardware ID + Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xa7020000, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + Return (RBUF) /* _SB_.USB0._CRS.RBUF */ + } + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"interrupt-parent",Package() {_SB.MBI0}} + } + }) + + Device (RHUB) + { + Name (_ADR, Zero) // _ADR: Address + Device (PRT1) + { + Name (_ADR, One) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + Zero, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0x0, + PLD_HorizontalOffset = 0x0) + + }) + } + + Device (PRT2) + { + Name (_ADR, 0x02) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + + Device (PRT3) + { + Name (_ADR, 0x03) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + + Device (PRT4) + { + Name (_ADR, 0x04) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + } + } +} + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl new file mode 100644 index 0000000..ca8b2dc --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -0,0 +1,29 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include "Hi1610Platform.h" + +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI1610", EFI_ACPI_ARM_OEM_REVISION) { + include ("Lpc.asl") + include ("D03Mbig.asl") + include ("CPU.asl") + include ("D03Usb.asl") + include ("D03Hns.asl") + include ("D03Sas.asl") + include ("D03Pci.asl") +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl new file mode 100644 index 0000000..0965afc --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl @@ -0,0 +1,25 @@ +/** @file +* +* Copyright (c) 2016 Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +// +// LPC +// + +Device (LPC0) +{ + Name(_HID, "HISI0191") // HiSi LPC + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) + }) +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc new file mode 100644 index 0000000..72cc66c --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc @@ -0,0 +1,67 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length + 0xA152, // UINT32 HardwareSignature + 0, // UINT32 FirmwareWakingVector + 0, // UINT32 GlobalLock + 0, // UINT32 Flags + 0, // UINT64 XFirmwareWakingVector + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] + EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] + 0, // UINT32 OspmFlags "Platform firmware must + // initialize this field to zero." + { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] + EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23] +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs; + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc new file mode 100644 index 0000000..5307041 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc @@ -0,0 +1,91 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Hi1610Platform.h" + +#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..4032382 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -0,0 +1,96 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Hi1610Platform.h" + +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT]; +} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + ARM_ACPI_HEADER( + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress +#ifdef notyet + PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, + { + EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), + 0, 0, 0, 0), + EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + 0, 0, 0, 0) + } +#else /* !notyet */ + 0, 0 + } +#endif + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h new file mode 100644 index 0000000..e8a1577 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + + +#ifndef _HI1610_PLATFORM_H_ +#define _HI1610_PLATFORM_H_ + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','1','6','1','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define HI1610_WATCHDOG_COUNT 2 + +#endif diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc new file mode 100644 index 0000000..7bebe8f --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc @@ -0,0 +1,128 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Hi1610Platform.h" + +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiNextLib.h> + +// Differs from Juno, we have another affinity level beyond cluster and core +// 0x20000 is only for socket 0 +#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) + +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1]; +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_1_0_APIC_SIGNATURE, + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // GsivId, GicRBase, Mpidr) + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of + // ACPI v5.1). + // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses + // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), + }, + + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), + { + EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000), + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc new file mode 100644 index 0000000..8b7aee4 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013 Linaro Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org +*/ + +#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h" + +#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014 + +#pragma pack(1) +typedef struct { + UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; +} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; + +typedef struct { + EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; + EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; + +} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE; +#pragma pack() + +// +// System Locality Information Table +// Please modify all values in Slit.h only. +// +EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { + { + { + EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE), + EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION, + }, + // + // Beginning of SLIT specific fields + // + EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, + }, + { + {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality 0 + {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality 1 + {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality 2 + {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality 3 + {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality 4 + {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality 5 + {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality 6 + {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality 7 + {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality 8 + {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality 9 + {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality 10 + {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality 11 + {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality 12 + {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality 13 + {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality 14 + {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality 15 + {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality 16 + {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality 17 + {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality 18 + {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality 19 + }, +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Slit; + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc new file mode 100644 index 0000000..99df1a4 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2013 Linaro Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org + * + * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +*/ + +#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h" +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h> + + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT 4 +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 4 + + +#pragma pack(1) +typedef struct { + EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE Apic; + EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE Memory[2]; + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE GICC[16]; +} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE; + +#pragma pack() + + +// +// Static Resource Affinity Table definition +// +EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = { + { + {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE), + EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION}, + /*Reserved*/ + 0x00000001, // Reserved to be 1 for backward compatibility + EFI_ACPI_RESERVED_QWORD + }, + /**/ + { + 0x00, // Subtable Type:Processor Local APIC/SAPIC Affinity + sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE), //Length + 0x00, //Proximity Domain Low(8) + 0x00, //Apic ID + 0x00000001, //Flags + 0x00, //Local Sapic EID + {0,0,0}, //Proximity Domain High(24) + 0x00000000, //ClockDomain + }, + // + // + // Memory Affinity + // + { + EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001), + EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001), + }, + + /*Processor Local x2APIC Affinity*/ + //{ + // 0x02, // Subtable Type:Processor Local x2APIC Affinity + // sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE), + // {0,0}, //Reserved1 + // 0x00000000, //Proximity Domain + // 0x00000000, //Apic ID + // 0x00000001, //Flags + // 0x00000000, //Clock Domain + // {0,0,0,0}, //Reserved2 + //}, + + { + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000) //GICC Affinity Processor 15 + }, +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Srat; + diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 7c72c84..29cc043 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -415,7 +415,7 @@ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf + OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
# diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 3150601..b57a74b 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -235,7 +235,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf + INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
On Thu, Oct 27, 2016 at 11:15:11AM +0800, Heyi Guo wrote:
Set all ACPI tables ID as below:
EFI_ACPI_ARM_OEM_ID HISI EFI_ACPI_ARM_OEM_TABLE_ID HISI1610 EFI_ACPI_ARM_OEM_REVISION 0x00000000 EFI_ACPI_ARM_CREATOR_ID INTL EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
And this looks to add back in all of the things that were deleted in the previous one. Please address for v2.
Regards,
Leif
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com
.../Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf | 56 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 337 ++++++++++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 85 ++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl | 88 ++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 36 ++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 562 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 125 +++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 261 ++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 247 +++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 136 +++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 29 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 67 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 91 ++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 96 ++++ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 48 ++ .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 128 +++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc | 81 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc | 115 +++++ Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- 21 files changed, 2615 insertions(+), 2 deletions(-) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf new file mode 100644 index 0000000..b6be3d9 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf @@ -0,0 +1,56 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +# +##
+[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = Hi1610AcpiTables
- FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
+[Sources]
- Dsdt/DsdtHi1610.asl
- Facs.aslc
- Fadt.aslc
- Gtdt.aslc
- MadtHi1610.aslc
- D03Mcfg.aslc
- D03Iort.asl
+[Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl new file mode 100644 index 0000000..e02b4d5 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -0,0 +1,337 @@ +/*
- Intel ACPI Component Architecture
- iASL Compiler/Disassembler version 20151124-64
- Copyright (c) 2000 - 2015 Intel Corporation
- Template for [IORT] ACPI Table (static data table)
- Format: [ByteLength] FieldName : HexFieldValue
- */
+[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 0000029e +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HISI1610" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124
+[0004] Node Count : 00000008 +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00
+/* ITS 0, for dsa */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000
+/* mbi-gen dsa mbi0 - usb, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0001] Memory Size Limit : 00 +[0017] Device Name : "_SB_.MBI0" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040080 // device id +[0004] Output Reference : 00000034 // point to its dsa +[0004] Flags (decoded below) : 00000000
Single Mapping : 1+/* mbi-gen dsa mbi1 - sas1, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI1" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 1+/* mbi-gen dsa mbi2 - sas2, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI2" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040040 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 1+/* mbi-gen dsa mbi3 - dsa0, srv named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI3" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040800 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 1+/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI4" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1c +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 1+/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI5" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1d +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 1+/* mbi-gen dsa mbi6 - dsa sas0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI6" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040900 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 1+/* RC 0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000000
+[0004] Input base : 00000000 +[0004] ID Count : 00002000 +[0004] Output Base : 00000000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 0+/* RC 1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000001
+[0004] Input base : 0000e000 +[0004] ID Count : 00002000 +[0004] Output Base : 0000e000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 0+/* RC 2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002
+[0004] Input base : 00008000 +[0004] ID Count : 00002000 +[0004] Output Base : 00008000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 0diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc new file mode 100644 index 0000000..ed47a44 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc @@ -0,0 +1,85 @@ +/*
- Copyright (c) 2016 Hisilicon Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- */
+#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h"
+#define ACPI_5_0_MCFG_VERSION 0x1
+#pragma pack(1) +typedef struct +{
- UINT64 ullBaseAddress;
- UINT16 usSegGroupNum;
- UINT8 ucStartBusNum;
- UINT8 ucEndBusNum;
- UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+typedef struct +{
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+typedef struct +{
- EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
- EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack()
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{
- {
{EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),ACPI_5_0_MCFG_VERSION,0x00, // Checksum will be updated at runtime{EFI_ACPI_ARM_OEM_ID},EFI_ACPI_ARM_OEM_TABLE_ID,EFI_ACPI_ARM_OEM_REVISION,EFI_ACPI_ARM_CREATOR_ID,EFI_ACPI_ARM_CREATOR_REVISION},0x0000000000000000, //Reserved- },
- {
- {
0xb0000000, //Base Address0x0, //Segment Group Number0x0, //Start Bus Number0x1f, //End Bus Number0x00000000, //Reserved- },
- {
0xb0000000, //Base Address0x1, //Segment Group Number0xe0, //Start Bus Number0xff, //End Bus Number0x00000000, //Reserved- },
- {
0xa0000000, //Base Address0x2, //Segment Group Number0x80, //Start Bus Number0x9f, //End Bus Number0x00000000, //Reserved- },
- }
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000..e995295 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,88 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+Scope(_SB) +{
- //
- // A57x16 Processor declaration
- //
- Device(CPU0) {
Name(_HID, "ACPI0007")Name(_UID, 0)- }
- Device(CPU1) {
Name(_HID, "ACPI0007")Name(_UID, 1)- }
- Device(CPU2) {
Name(_HID, "ACPI0007")Name(_UID, 2)- }
- Device(CPU3) {
Name(_HID, "ACPI0007")Name(_UID, 3)- }
- Device(CPU4) {
Name(_HID, "ACPI0007")Name(_UID, 4)- }
- Device(CPU5) {
Name(_HID, "ACPI0007")Name(_UID, 5)- }
- Device(CPU6) {
Name(_HID, "ACPI0007")Name(_UID, 6)- }
- Device(CPU7) {
Name(_HID, "ACPI0007")Name(_UID, 7)- }
- Device(CPU8) {
Name(_HID, "ACPI0007")Name(_UID, 8)- }
- Device(CPU9) {
Name(_HID, "ACPI0007")Name(_UID, 9)- }
- Device(CP10) {
Name(_HID, "ACPI0007")Name(_UID, 10)- }
- Device(CP11) {
Name(_HID, "ACPI0007")Name(_UID, 11)- }
- Device(CP12) {
Name(_HID, "ACPI0007")Name(_UID, 12)- }
- Device(CP13) {
Name(_HID, "ACPI0007")Name(_UID, 13)- }
- Device(CP14) {
Name(_HID, "ACPI0007")Name(_UID, 14)- }
- Device(CP15) {
Name(_HID, "ACPI0007")Name(_UID, 15)- }
+} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000..3bcc5fb --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl @@ -0,0 +1,36 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+Scope(_SB) +{
- Device(COM0) {
- Name(_HID, "HISI0031") //it is not 16550 compatible
- Name(_CID, "8250dw")
- Name(_UID, Zero)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x80300000, 0x1000)Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 }- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"clock-frequency", 200000000},}- })
- }
+} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl new file mode 100644 index 0000000..d8d453a --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -0,0 +1,562 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- Device (MDIO)
- {
- OperationRegion(CLKR, SystemMemory, 0x60000338, 8)
- Field(CLKR, DWordAcc, NoLock, Preserve) {
CLKE, 1, // clock enable, 31,CLKD, 1, // clode disable, 31,- }
- OperationRegion(RSTR, SystemMemory, 0x60000A38, 8)
- Field(RSTR, DWordAcc, NoLock, Preserve) {
RSTE, 1, // reset, 31,RSTD, 1, // de-reset, 31,- }
- Name(_HID, "HISI0141")
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)})- Method(_RST, 0, Serialized) {
Store (0x1, RSTE)Sleep (10)Store (0x1, CLKD)Sleep (10)Store (0x1, RSTD)Sleep (10)Store (0x1, CLKE)Sleep (10)- }
- }
- Device (DSF0)
- {
- OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
H3ST, 1,, 31, //RESERVED}- OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
- Field(H4SR, DWordAcc, NoLock, Preserve) {
H4ST, 1,, 31, //RESERVED}- // DSAF RESET
- OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
- Field(DRER, DWordAcc, NoLock, Preserve) {
DRTE, 1,, 31, //RESERVEDDRTD, 1,, 31, //RESERVED}- // NT RESET
- OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
- Field(NRER, DWordAcc, NoLock, Preserve) {
NRTE, 1,, 31, //RESERVEDNRTD, 1,, 31, //RESERVED}- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
XRTE, 31,, 1, //RESERVEDXRTD, 31,, 1, //RESERVED}- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
GR0E, 30,, 2, //RESERVEDGR0D, 30,, 2, //RESERVEDGR1E, 18,, 14, //RESERVEDGR1D, 18,, 14, //RESERVED}- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
PRTE, 10,, 22, //RESERVEDPRTD, 10,, 22, //RESERVED}- // RCB PPE COM RESET
- OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
- Field(RRTR, DWordAcc, NoLock, Preserve) {
RRTE, 1,, 31, //RESERVEDRRTD, 1,, 31, //RESERVED}- // Hilink access sel cfg reg
- OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
- Field(HSER, DWordAcc, NoLock, Preserve) {
HSEL, 2, // hilink_access_sel & hilink_access_wr_pul, 30, // RESERVED}- // Serdes
- OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
- Field(H4LR, DWordAcc, NoLock, Preserve) {
H4L0, 16, // port0, 16, //RESERVEDOffset (0x400),H4L1, 16, // port1, 16, //RESERVEDOffset (0x800),H4L2, 16, // port2, 16, //RESERVEDOffset (0xc00),H4L3, 16, // port3, 16, //RESERVED}- OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
H3L2, 16, // port4, 16, //RESERVEDOffset (0x400),H3L3, 16, // port5, 16, //RESERVED}Name (_HID, "HISI00B2")Name (_CCA, 1) // Cache-coherent controllerName (_CRS, ResourceTemplate (){Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,){576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,){960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,){1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"mode", "6port-16rss"},Package () {"buf-size", 4096},Package () {"desc-num", 1024},Package () {"interrupt-parent", Package() {\_SB.MBI3}},}})- //reset XGE port
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XRST, 2, Serialized) {
ShiftLeft (0x2082082, Arg0, Local0)Or (Local0, 0x1, Local0)If (LEqual (Arg1, 0)) {Store(Local0, XRTE)} Else {Store(Local0, XRTD)}- }
- //reset XGE core
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XCRT, 2, Serialized) {
ShiftLeft (0x2080, Arg0, Local0)If (LEqual (Arg1, 0)) {Store(Local0, XRTE)} Else {Store(Local0, XRTD)}- }
- //reset GE port
- //Arg0 : GE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(GRST, 2, Serialized) {
If (LLessEqual (Arg0, 5)) {//Service portShiftLeft (0x2082082, Arg0, Local0)ShiftLeft (0x1, Arg0, Local1)If (LEqual (Arg1, 0)) {Store(Local1, GR1E)Store(Local0, GR0E)} Else {Store(Local0, GR0D)Store(Local1, GR1D)}}- }
- //reset PPE port
- //Arg0 : PPE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(PRST, 2, Serialized) {
ShiftLeft (0x1, Arg0, Local0)If (LEqual (Arg1, 0)) {Store(Local0, PRTE)} Else {Store(Local0, PRTD)}- }
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 2, Serialized) {
ShiftLeft (Arg1, 10, Local0)Switch (ToInteger(Arg0)){case (0x0){Store (0, HSEL)Store (H4L0, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H4L0)}case (0x1){Store (0, HSEL)Store (H4L1, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H4L1)}case (0x2){Store (0, HSEL)Store (H4L2, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H4L2)}case (0x3){Store (0, HSEL)Store (H4L3, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H4L3)}case (0x4){Store (3, HSEL)Store (H3L2, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H3L2)}case (0x5){Store (3, HSEL)Store (H3L3, Local1)And (Local1, 0xfffffbff, Local1)Or (Local0, Local1, Local0)Store (Local0, H3L3)}}- }
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
- //Arg1 : port
- //Arg2 : 0 disable, 1 enable
- Method(DRST, 3, Serialized)
- {
Switch (ToInteger(Arg0)){//DSAF resetcase (0x1){Store (Arg2, Local0)If (LEqual (Local0, 0)){Store (0x1, DRTE)Store (0x1, NRTE)Sleep (10)Store (0x1, RRTE)}Else{Store (0x1, DRTD)Store (0x1, NRTD)Sleep (10)Store (0x1, RRTD)}}//Reset PPE portcase (0x2){Store (Arg1, Local0)Store (Arg2, Local1)PRST (Local0, Local1)}//Reset XGE corecase (0x3){Store (Arg1, Local0)Store (Arg2, Local1)XCRT (Local0, Local1)}//Reset XGE portcase (0x4){Store (Arg1, Local0)Store (Arg2, Local1)XRST (Local0, Local1)}//Reset GE portcase (0x5){Store (Arg1, Local0)Store (Arg2, Local1)GRST (Local0, Local1)}}- }
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset Sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
- // Arg3[1] : port index in dsaf
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : port
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : port
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : port index in dsaf
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : port index in dsaf
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))){If (LEqual (Arg1, 0x00)){Switch (ToInteger(Arg2)){case (0x0){Return (Buffer () {0x3F})}//Reset Sequencecase (0x1){Store (DeRefOf (Index (Arg3, 0)), Local0)Store (DeRefOf (Index (Arg3, 1)), Local1)Store (DeRefOf (Index (Arg3, 2)), Local2)DRST (Local0, Local1, Local2)}//Set Serdes Loopbackcase (0x2){Store (DeRefOf (Index (Arg3, 0)), Local0)Store (DeRefOf (Index (Arg3, 1)), Local1)SRLP (Local0, Local1)}//LED op setcase (0x3){}// Get port type (GE or XGE)case (0x4){Store (0, Local1)Store (DeRefOf (Index (Arg3, 0)), Local0)If (LLessEqual (Local0, 3)){// mac0: Hilink4 Lane0// mac1: Hilink4 Lane1// mac2: Hilink4 Lane2// mac3: Hilink4 Lane3Store (H4ST, Local1)}ElseIf (LLessEqual (Local0, 5)){// mac4: Hilink3 Lane2// mac5: Hilink3 Lane3Store (H3ST, Local1)}Return (Local1)}//Get sfp statuscase (0x5){}}}}Return (Buffer() {0x00})- }
- Device (PRT0)
- {
Name (_ADR, 0x0)Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"reg", 0},Package () {"media-type", "fiber"},}})- }
- Device (PRT1)
- {
Name (_ADR, 0x1)Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"reg", 1},Package () {"media-type", "fiber"},}})- }
- Device (PRT4)
- {
Name (_ADR, 0x4)Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"reg", 4},Package () {"phy-mode", "sgmii"},Package () {"phy-addr", 0},Package () {"mdio-node", Package (){\_SB.MDIO}},Package () {"media-type", "copper"},}})- }
- Device (PRT5)
- {
Name (_ADR, 0x5)Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"reg", 5},Package () {"phy-mode", "sgmii"},Package () {"phy-addr", 1},Package () {"mdio-node", Package (){\_SB.MDIO}},Package () {"media-type", "copper"},}})- }
- }
- Device (ETH4) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytesPackage () {"ae-handle", Package (){\_SB.DSF0}},Package () {"port-idx-in-ae", 4},}- })
- }
- Device (ETH5) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytesPackage () {"ae-handle", Package (){\_SB.DSF0}},Package () {"port-idx-in-ae", 5},}- })
- }
- Device (ETH0) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytesPackage () {"ae-handle", Package (){\_SB.DSF0}},Package () {"port-idx-in-ae", 0},}- })
- }
- Device (ETH1) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytesPackage () {"ae-handle", Package (){\_SB.DSF0}},Package () {"port-idx-in-ae", 1},}- })
- }
+} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl new file mode 100644 index 0000000..4eaa073 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -0,0 +1,125 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- // Mbi-gen pcie subsys
- Device(MBI0) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 2}}- })
- }
- // Mbi-gen sas1 intc
- Device(MBI1) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 128}}- })
- }
- Device(MBI2) { // Mbi-gen sas2 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 128}}- })
- }
- Device(MBI3) { // Mbi-gen dsa0 srv intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 409}}- })
- }
- Device(MBI4) { // Mbi-gen dsa1 dbg0 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 9}}- })
- }
- Device(MBI5) { // Mbi-gen dsa2 dbg1 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 9}}- })
- }
- Device(MBI6) { // Mbi-gen dsa sas0 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 128}}- })
- }
+} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl new file mode 100644 index 0000000..573c0a3 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl @@ -0,0 +1,261 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+//#include "ArmPlatform.h" +Scope(_SB) +{
- // PCIe Root bus
- Device (PCI0)
- {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0) // Segment of this Root complex
- Name(_BBN, 0) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {WordBusNumber ( // Bus numbers assigned to this rootResourceProducer, MinFixed, MaxFixed, PosDecode,0, // AddressGranularity0x0, // AddressMinimum - Minimum Bus Number0x1f, // AddressMaximum - Maximum Bus Number0, // AddressTranslation - Set to 00x20 // RangeLength - Number of Busses)QWordMemory ( // 64-bit BAR WindowsResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,ReadWrite,0x0, // Granularity0xb2000000, // Min Base Address pci address0xb7feffff, // Max Base Address0x0, // Translate0x5ff0000 // Length)QWordIO (ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,0x0, // Granularity0x0, // Min Base Address0xffff, // Max Base Address0xb7ff0000, // Translate0x10000 // Length)}) // Name(RBUF)Return (RBUF)- } // Method(_CRS)
- Device (RES0)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base addressName (_CRS, ResourceTemplate (){Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)})- }
- OperationRegion(SCTR, SystemMemory, 0xa009131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- }
- } // Device(PCI0)
- // PCIe Root bus
- Device (PCI1)
- {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 1) // Segment of this Root complex
- Name(_BBN, 0xe0) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {WordBusNumber ( // Bus numbers assigned to this rootResourceProducer, MinFixed, MaxFixed, PosDecode,0, // AddressGranularity0xe0, // AddressMinimum - Minimum Bus Number0xff, // AddressMaximum - Maximum Bus Number0, // AddressTranslation - Set to 00x20 // RangeLength - Number of Busses)QWordMemory ( // 64-bit BAR WindowsResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,ReadWrite,0x0, // Granularity0xb8000000, // Min Base Address pci address0xbdfeffff, // Max Base Address0x0, // Translate0x5ff0000 // Length)QWordIO (ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,0x0, // Granularity0x0, // Min Base Address0xffff, // Max Base Address0xbdff0000, // Translate0x10000 // Length)}) // Name(RBUF)Return (RBUF)- } // Method(_CRS)
- Device (RES1)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base addressName (_CRS, ResourceTemplate (){Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)})- }
- OperationRegion(SCTR, SystemMemory, 0xa020131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- }
- } // Device(PCI1)
- // PCIe Root bus
- Device (PCI2)
- {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 2) // Segment of this Root complex
- Name(_BBN, 0x80) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {WordBusNumber ( // Bus numbers assigned to this rootResourceProducer, MinFixed, MaxFixed, PosDecode,0, // AddressGranularity0x80, // AddressMinimum - Minimum Bus Number0x9f, // AddressMaximum - Maximum Bus Number0, // AddressTranslation - Set to 00x20 // RangeLength - Number of Busses)QWordMemory ( // 64-bit BAR WindowsResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,ReadWrite,0x0, // Granularity0xaa000000, // Min Base Address0xaffeffff, // Max Base Address0x0, // Translate0x5ff0000 // Length)QWordIO (ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,0x0, // Granularity0x0, // Min Base Address0xffff, // Max Base Address0xafff0000, // Translate0x10000 // Length)}) // Name(RBUF)Return (RBUF)- } // Method(_CRS)
- Device (RES2)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base addressName (_CRS, ResourceTemplate (){Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)})- }
- OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))){switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- }
- } // Device(PCI2)
+}
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl new file mode 100644 index 0000000..ce8ccd6 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -0,0 +1,247 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- Device(SAS0) {
Name(_HID, "HISI0162")- Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ){601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI6}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},Package () {"queue-count", 16},Package () {"phy-count", 8},}})- OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x338),CLK, 32,CLKD, 32,Offset (0xa60),RST, 32,DRST, 32,Offset (0x5a30),STS, 32,- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)Store(0x7ffff, CLKD)Sleep(1)Store(0x7ffff, DRST)Store(0x7ffff, CLK)Sleep(1)- }
- }
- Device(SAS1) {
Name(_HID, "HISI0162")- Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ){576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI1}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 16},Package () {"phy-count", 8},Package () {"hip06-sas-v2-quirk-amt", 1},}})- OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x318),CLK, 32,CLKD, 32,Offset (0xa18),RST, 32,DRST, 32,Offset (0x5a0c),STS, 32,- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)Store(0x7ffff, CLKD)Sleep(1)Store(0x7ffff, DRST)Store(0x7ffff, CLK)Sleep(1)- }
- }
- Device(SAS2) {
Name(_HID, "HISI0162")- Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,}Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ){608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,}})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI2}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 16},Package () {"phy-count", 8},}})- OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x3a8),CLK, 32,CLKD, 32,Offset (0xae0),RST, 32,DRST, 32,Offset (0x5a70),STS, 32,- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)Store(0x7ffff, CLKD)Sleep(1)Store(0x7ffff, DRST)Store(0x7ffff, CLK)Sleep(1)- }
- }
+} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl new file mode 100644 index 0000000..28ba03d --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -0,0 +1,136 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+//#include "ArmPlatform.h" +Scope(_SB) +{
- Device (USB0)
{Name (_HID, "PNP0D20") // _HID: Hardware IDName (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible IDName (_CCA, One) // _CCA: Cache Coherency AttributeMethod (_CRS, 0, Serialized) // _CRS: Current Resource Settings{Name (RBUF, ResourceTemplate (){Memory32Fixed (ReadWrite,0xa7020000, // Address Base0x00010000, // Address Length)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){0x00000041,}})Return (RBUF) /* \_SB_.USB0._CRS.RBUF */}Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"interrupt-parent",Package() {\_SB.MBI0}}}})Device (RHUB){Name (_ADR, Zero) // _ADR: AddressDevice (PRT1){Name (_ADR, One) // _ADR: AddressName (_UPC, Package (0x04) // _UPC: USB Port Capabilities{0xFF,Zero,Zero,Zero})Name (_PLD, Package (0x01) // _PLD: Physical Location of Device{ToPLD (PLD_Revision = 0x1,PLD_IgnoreColor = 0x1,PLD_Red = 0x0,PLD_Green = 0x0,PLD_Blue = 0x0,PLD_Width = 0x0,PLD_Height = 0x0,PLD_UserVisible = 0x1,PLD_Dock = 0x0,PLD_Lid = 0x0,PLD_Panel = "UNKNOWN",PLD_VerticalPosition = "UPPER",PLD_HorizontalPosition = "LEFT",PLD_Shape = "UNKNOWN",PLD_GroupOrientation = 0x0,PLD_GroupToken = 0x0,PLD_GroupPosition = 0x0,PLD_Bay = 0x0,PLD_Ejectable = 0x0,PLD_EjectRequired = 0x0,PLD_CabinetNumber = 0x0,PLD_CardCageNumber = 0x0,PLD_Reference = 0x0,PLD_Rotation = 0x0,PLD_Order = 0x0,PLD_VerticalOffset = 0x0,PLD_HorizontalOffset = 0x0)})}Device (PRT2){Name (_ADR, 0x02) // _ADR: AddressName (_UPC, Package (0x04) // _UPC: USB Port Capabilities{Zero,0xFF,Zero,Zero})}Device (PRT3){Name (_ADR, 0x03) // _ADR: AddressName (_UPC, Package (0x04) // _UPC: USB Port Capabilities{Zero,0xFF,Zero,Zero})}Device (PRT4){Name (_ADR, 0x04) // _ADR: AddressName (_UPC, Package (0x04) // _UPC: USB Port Capabilities{Zero,0xFF,Zero,Zero})}}}+}
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl new file mode 100644 index 0000000..ca8b2dc --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -0,0 +1,29 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+#include "Hi1610Platform.h"
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI1610", EFI_ACPI_ARM_OEM_REVISION) {
include ("Lpc.asl")include ("D03Mbig.asl")include ("CPU.asl")include ("D03Usb.asl")include ("D03Hns.asl")include ("D03Sas.asl")include ("D03Pci.asl")+} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl new file mode 100644 index 0000000..0965afc --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl @@ -0,0 +1,25 @@ +/** @file +* +* Copyright (c) 2016 Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+// +// LPC +//
+Device (LPC0) +{
- Name(_HID, "HISI0191") // HiSi LPC
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
- })
+} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc new file mode 100644 index 0000000..72cc66c --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc @@ -0,0 +1,67 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include <IndustryStandard/Acpi.h>
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
- sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
- 0xA152, // UINT32 HardwareSignature
- 0, // UINT32 FirmwareWakingVector
- 0, // UINT32 GlobalLock
- 0, // UINT32 Flags
- 0, // UINT64 XFirmwareWakingVector
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]- 0, // UINT32 OspmFlags "Platform firmware must
// initialize this field to zero."- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs;
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc new file mode 100644 index 0000000..5307041 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc @@ -0,0 +1,91 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include "Hi1610Platform.h"
+#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h>
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
- ARM_ACPI_HEADER (
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
- ),
- 0, // UINT32 FirmwareCtrl
- 0, // UINT32 Dsdt
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
- EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
- 0, // UINT16 SciInt
- 0, // UINT32 SmiCmd
- 0, // UINT8 AcpiEnable
- 0, // UINT8 AcpiDisable
- 0, // UINT8 S4BiosReq
- 0, // UINT8 PstateCnt
- 0, // UINT32 Pm1aEvtBlk
- 0, // UINT32 Pm1bEvtBlk
- 0, // UINT32 Pm1aCntBlk
- 0, // UINT32 Pm1bCntBlk
- 0, // UINT32 Pm2CntBlk
- 0, // UINT32 PmTmrBlk
- 0, // UINT32 Gpe0Blk
- 0, // UINT32 Gpe1Blk
- 0, // UINT8 Pm1EvtLen
- 0, // UINT8 Pm1CntLen
- 0, // UINT8 Pm2CntLen
- 0, // UINT8 PmTmrLen
- 0, // UINT8 Gpe0BlkLen
- 0, // UINT8 Gpe1BlkLen
- 0, // UINT8 Gpe1Base
- 0, // UINT8 CstCnt
- 0, // UINT16 PLvl2Lat
- 0, // UINT16 PLvl3Lat
- 0, // UINT16 FlushSize
- 0, // UINT16 FlushStride
- 0, // UINT8 DutyOffset
- 0, // UINT8 DutyWidth
- 0, // UINT8 DayAlrm
- 0, // UINT8 MonAlrm
- 0, // UINT8 Century
- 0, // UINT16 IaPcBootArch
- 0, // UINT8 Reserved1
- EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
- 0, // UINT8 ResetValue
- EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
- 0, // UINT64 XFirmwareCtrl
- 0, // UINT64 XDsdt
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
- NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..4032382 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -0,0 +1,96 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include "Hi1610Platform.h"
+#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h>
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
- #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+#pragma pack (1)
+typedef struct {
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
- EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT];
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+#pragma pack ()
+EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
- {
- ARM_ACPI_HEADER(
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE,EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION- ),
- SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
- 0, // UINT32 Reserved
- FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
- FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
- FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
- FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
- 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+#ifdef notyet
- PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
- sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
- },
- {
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
//FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),0, 0, 0, 0),- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
//FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)0, 0, 0, 0)- }
+#else /* !notyet */
- 0, 0
- }
+#endif
- };
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h new file mode 100644 index 0000000..e8a1577 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#ifndef _HI1610_PLATFORM_H_ +#define _HI1610_PLATFORM_H_
+// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','1','6','1','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
- Signature, /* UINT32 Signature */ \
- sizeof (Type), /* UINT32 Length */ \
- Revision, /* UINT8 Revision */ \
- 0, /* UINT8 Checksum */ \
- { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
- EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
- EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
- EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
- EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
- }
+#define HI1610_WATCHDOG_COUNT 2
+#endif diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc new file mode 100644 index 0000000..7bebe8f --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc @@ -0,0 +1,128 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include "Hi1610Platform.h"
+#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiNextLib.h>
+// Differs from Juno, we have another affinity level beyond cluster and core +// 0x20000 is only for socket 0 +#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId))
+// +// Multiple APIC Description Table +// +#pragma pack (1)
+typedef struct {
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16];
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1];
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+#pragma pack ()
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
- {
- ARM_ACPI_HEADER (
EFI_ACPI_1_0_APIC_SIGNATURE,EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION- ),
- //
- // MADT specific fields
- //
- 0, // LocalApicAddress
- 0, // Flags
- },
- {
- // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
- // GsivId, GicRBase, Mpidr)
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
- // ACPI v5.1).
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */),- },
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4),
- {
- EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000),
- }
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc new file mode 100644 index 0000000..8b7aee4 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc @@ -0,0 +1,81 @@ +/*
- Copyright (c) 2013 Linaro Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- Contributors:
Yi Li - yi.li@linaro.org+*/
+#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h"
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014
+#pragma pack(1) +typedef struct {
- UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+typedef struct {
- EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header;
- EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE; +#pragma pack()
+// +// System Locality Information Table +// Please modify all values in Slit.h only. +// +EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
- {
- {
EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE),EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,0x00, // Checksum will be updated at runtime{EFI_ACPI_ARM_OEM_ID},EFI_ACPI_ARM_OEM_TABLE_ID,EFI_ACPI_ARM_OEM_REVISION,EFI_ACPI_ARM_CREATOR_ID,EFI_ACPI_ARM_CREATOR_REVISION,- },
- //
- // Beginning of SLIT specific fields
- //
- EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
- },
- {
- {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality 0
- {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality 1
- {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality 2
- {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality 3
- {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality 4
- {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality 5
- {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality 6
- {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality 7
- {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality 8
- {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality 9
- {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality 10
- {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality 11
- {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality 12
- {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality 13
- {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality 14
- {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality 15
- {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality 16
- {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality 17
- {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality 18
- {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality 19
- },
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Slit;
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc new file mode 100644 index 0000000..99df1a4 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc @@ -0,0 +1,115 @@ +/*
- Copyright (c) 2013 Linaro Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- Contributors:
Yi Li - yi.li@linaro.org
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h" +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h>
+// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT 4 +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 4
+#pragma pack(1) +typedef struct {
- EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
- EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE Apic;
- EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE Memory[2];
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE GICC[16];
+} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE;
+#pragma pack()
+// +// Static Resource Affinity Table definition +// +EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = {
- {
- {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
- sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE),
- EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
- 0x00, // Checksum will be updated at runtime
- {EFI_ACPI_ARM_OEM_ID},
- EFI_ACPI_ARM_OEM_TABLE_ID,
- EFI_ACPI_ARM_OEM_REVISION,
- EFI_ACPI_ARM_CREATOR_ID,
- EFI_ACPI_ARM_CREATOR_REVISION},
- /*Reserved*/
- 0x00000001, // Reserved to be 1 for backward compatibility
- EFI_ACPI_RESERVED_QWORD
- },
- /**/
- {
0x00, // Subtable Type:Processor Local APIC/SAPIC Affinitysizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE), //Length0x00, //Proximity Domain Low(8)0x00, //Apic ID0x00000001, //Flags0x00, //Local Sapic EID{0,0,0}, //Proximity Domain High(24)0x00000000, //ClockDomain- },
- //
- //
- // Memory Affinity
- //
- {
- EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001),
- EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001),
- },
- /*Processor Local x2APIC Affinity*/
- //{
- // 0x02, // Subtable Type:Processor Local x2APIC Affinity
- // sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE),
- // {0,0}, //Reserved1
- // 0x00000000, //Proximity Domain
- // 0x00000000, //Apic ID
- // 0x00000001, //Flags
- // 0x00000000, //Clock Domain
- // {0,0,0,0}, //Reserved2
- //},
- {
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14
- EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000) //GICC Affinity Processor 15
- },
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Srat;
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 7c72c84..29cc043 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -415,7 +415,7 @@ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
# diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 3150601..b57a74b 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -235,7 +235,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
1.9.1
Use irq producer/consumer to represent the topology of device and mbi-gen:
We are using _PRS methd to indicate number of irq pins instead of num_pins in DT.
For mbi-gen, Device(MBI0) { Name(_HID, "HISI0152") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
Name (_PRS, ResourceTemplate() { Interrupt(ResourceProducer,...) {12,14,....} }) }
For devices,
Device(COM0) { Name(_HID, "ACPIIDxx") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xb0030000, 0x10000) Interrupt(ResourceConsumer,..., "_SB.MBI0") {12} }) }
Update the DSDT as above.
Change-Id: I39140bd47c2e39ec2bbdf5e71faba7bab775d635 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hanjun Guo hanjun.guo@linaro.org --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 6 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 163 ++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 18 +-- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 4 files changed, 174 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index d8d453a..9a7fdb0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -150,12 +150,12 @@ Scope(_SB) Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI3") { 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI3") { 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, @@ -170,7 +170,7 @@ Scope(_SB) 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI3") { 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 4eaa073..5456bd8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -22,6 +22,10 @@ Scope(_SB) Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
+ Name(_PRS, ResourceTemplate() { + Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42} + }) + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () @@ -38,6 +42,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, + } + }) + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () @@ -53,6 +95,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ) + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } + }) + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () @@ -68,6 +148,45 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) }) + +Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } +}) + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () @@ -76,7 +195,7 @@ Scope(_SB) } }) } - +/* Device(MBI4) { // Mbi-gen dsa1 dbg0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") @@ -106,13 +225,53 @@ Scope(_SB) } }) } - +*/ Device(MBI6) { // Mbi-gen dsa sas0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) }) + + Name(_PRS, ResourceTemplate() { + Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } + }) + + + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index ce8ccd6..de21b2d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -21,8 +21,8 @@ Scope(_SB) Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI6") + { 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79, @@ -45,7 +45,7 @@ Scope(_SB) 160, }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI6" ) { 601,602,603,604, 605,606,607,608,609, @@ -93,12 +93,12 @@ Scope(_SB)
Device(SAS1) { Name(_HID, "HISI0162") - Name(_CCA, 1) + Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI1") + { 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79, @@ -121,7 +121,7 @@ Scope(_SB) 160, }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") { 576,577,578,579,580, 581,582,583,584,585, @@ -174,7 +174,7 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI2") { 192,193,194,195,196, 197,198,199,200,201, @@ -198,7 +198,7 @@ Scope(_SB) 287, }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI2") { 608,609,610,611, 612,613,614,615,616, diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 28ba03d..8429a4b 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -32,7 +32,7 @@ Scope(_SB) 0xa7020000, // Address Base 0x00010000, // Address Length ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI0") { 0x00000041, }
Graeme?
Looks plausible to me, but I don't have the ACPI background.
Regards,
Leif
On Thu, Oct 27, 2016 at 11:15:12AM +0800, Heyi Guo wrote:
Use irq producer/consumer to represent the topology of device and mbi-gen:
We are using _PRS methd to indicate number of irq pins instead of num_pins in DT.
For mbi-gen, Device(MBI0) { Name(_HID, "HISI0152") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) }) Name (_PRS, ResourceTemplate() { Interrupt(ResourceProducer,...) {12,14,....} }) } For devices, Device(COM0) { Name(_HID, "ACPIIDxx") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xb0030000, 0x10000) Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12} }) }Update the DSDT as above.
Change-Id: I39140bd47c2e39ec2bbdf5e71faba7bab775d635 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hanjun Guo hanjun.guo@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 6 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 163 ++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 18 +-- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 4 files changed, 174 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index d8d453a..9a7fdb0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -150,12 +150,12 @@ Scope(_SB) Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,@@ -170,7 +170,7 @@ Scope(_SB) 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 4eaa073..5456bd8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -22,6 +22,10 @@ Scope(_SB) Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -38,6 +42,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ){576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -53,6 +95,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
Name(_PRS, ResourceTemplate() {Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ){192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ){608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -68,6 +148,45 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) })
+Name(_PRS, ResourceTemplate() {
- Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
{576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,){960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,){1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,}+})
- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -76,7 +195,7 @@ Scope(_SB) } }) }
+/* Device(MBI4) { // Mbi-gen dsa1 dbg0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") @@ -106,13 +225,53 @@ Scope(_SB) } }) }
+*/ Device(MBI6) { // Mbi-gen dsa sas0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ){601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index ce8ccd6..de21b2d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -21,8 +21,8 @@ Scope(_SB) Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6"){ 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79,@@ -45,7 +45,7 @@ Scope(_SB) 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI6" ) { 601,602,603,604, 605,606,607,608,609,@@ -93,12 +93,12 @@ Scope(_SB) Device(SAS1) { Name(_HID, "HISI0162")
- Name(_CCA, 1)
Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI1"){ 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79,@@ -121,7 +121,7 @@ Scope(_SB) 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") { 576,577,578,579,580, 581,582,583,584,585,@@ -174,7 +174,7 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") { 192,193,194,195,196, 197,198,199,200,201,@@ -198,7 +198,7 @@ Scope(_SB) 287, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") { 608,609,610,611, 612,613,614,615,616,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 28ba03d..8429a4b 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -32,7 +32,7 @@ Scope(_SB) 0xa7020000, // Address Base 0x00010000, // Address Length )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 0x00000041, }-- 1.9.1
Hi Leif,
On 2016/11/6 0:49, Leif Lindholm wrote:
Graeme?
Looks plausible to me, but I don't have the ACPI background.
This is mirroring the new ECR for ACPI spec, which is:
https://mantis.uefi.org/mantis/view.php?id=1588
"Clarifies how interrupt producers and consumers are handled in ACPI. The concept of interrupt producers is easily described and supported in device tree based systems, but it seems this is not really covered by currently ACPI based systems. Consider an example use-case with the following components: - We have device A, which is an “interrupt combiner” that multiplexes a large group of interrupt wires and produces a single summary interrupt (in a very similar way to GPIO controllers). This device can be considered as an interrupt producer, but outputs virtual interrupts rather than physical interrupts. - We have device B with its interrupt wire going into the interrupt combiner. - The device driver for Device B is some standard driver that expects to register for an interrupt resource.
To solve this problem, we could make device A as a GPIO controller (i.e. device A would produce GPIO interrupts instead of *real* interrupts), but that would require a change to the driver for device B, which is not a valid option for a lot of standard/common drivers. There does seem to be a concept of interrupt producers and consumers in the ACPI specification, but it seems to only be used in reference to PCI. Note that generally the OSPM seems to ignore the Producer/Consumer flag and Resource Source fields when given in the Extended Interrupt Descriptor. This is handled quite easily in device tree based systems. - Device A is implemented as an irqchip - Device B interrupt resource references Device A as the source of the interrupt. - Device A raises handles summary interrupt, determines it needs to interrupt device B, raises a virtual interrupt to device B.
It is a desirable capability (on both mobile and server platforms), and we would like to have a mechanism to handle this in ACPI. This ECR attempts to better define the language around the extended interrupt descriptor to enable this functionality without significant change to the actual ACPI specification."
This ECR was approved, please let me know if you have further questions.
Thanks Hanjun
Regards,
Leif
On Thu, Oct 27, 2016 at 11:15:12AM +0800, Heyi Guo wrote:
Use irq producer/consumer to represent the topology of device and mbi-gen:
We are using _PRS methd to indicate number of irq pins instead of num_pins in DT.
For mbi-gen, Device(MBI0) { Name(_HID, "HISI0152") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) }) Name (_PRS, ResourceTemplate() { Interrupt(ResourceProducer,...) {12,14,....} }) } For devices, Device(COM0) { Name(_HID, "ACPIIDxx") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xb0030000, 0x10000) Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12} }) }Update the DSDT as above.
Change-Id: I39140bd47c2e39ec2bbdf5e71faba7bab775d635 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hanjun Guo hanjun.guo@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 6 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 163 ++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 18 +-- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 4 files changed, 174 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index d8d453a..9a7fdb0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -150,12 +150,12 @@ Scope(_SB) Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,@@ -170,7 +170,7 @@ Scope(_SB) 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 4eaa073..5456bd8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -22,6 +22,10 @@ Scope(_SB) Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -38,6 +42,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ){576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -53,6 +95,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
Name(_PRS, ResourceTemplate() {Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ){192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ){608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -68,6 +148,45 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) })
+Name(_PRS, ResourceTemplate() {
- Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
{576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,){960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,){1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,}+})
- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -76,7 +195,7 @@ Scope(_SB) } }) }
+/* Device(MBI4) { // Mbi-gen dsa1 dbg0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") @@ -106,13 +225,53 @@ Scope(_SB) } }) }
+*/ Device(MBI6) { // Mbi-gen dsa sas0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ){601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index ce8ccd6..de21b2d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -21,8 +21,8 @@ Scope(_SB) Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6"){ 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79,@@ -45,7 +45,7 @@ Scope(_SB) 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI6" ) { 601,602,603,604, 605,606,607,608,609,@@ -93,12 +93,12 @@ Scope(_SB)
Device(SAS1) { Name(_HID, "HISI0162")
- Name(_CCA, 1)
Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI1"){ 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79,@@ -121,7 +121,7 @@ Scope(_SB) 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") { 576,577,578,579,580, 581,582,583,584,585,@@ -174,7 +174,7 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") { 192,193,194,195,196, 197,198,199,200,201,@@ -198,7 +198,7 @@ Scope(_SB) 287, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") { 608,609,610,611, 612,613,614,615,616,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 28ba03d..8429a4b 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -32,7 +32,7 @@ Scope(_SB) 0xa7020000, // Address Base 0x00010000, // Address Length )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 0x00000041, }-- 1.9.1
Thanks.
Can I take that as a reviewed-by?
/ Leif
On Tue, Nov 15, 2016 at 01:32:19PM +0800, Hanjun Guo wrote:
Hi Leif,
On 2016/11/6 0:49, Leif Lindholm wrote:
Graeme?
Looks plausible to me, but I don't have the ACPI background.
This is mirroring the new ECR for ACPI spec, which is:
https://mantis.uefi.org/mantis/view.php?id=1588
"Clarifies how interrupt producers and consumers are handled in ACPI. The concept of interrupt producers is easily described and supported in device tree based systems, but it seems this is not really covered by currently ACPI based systems. Consider an example use-case with the following components:
- We have device A, which is an “interrupt combiner” that multiplexes a
large group of interrupt wires and produces a single summary interrupt (in a very similar way to GPIO controllers). This device can be considered as an interrupt producer, but outputs virtual interrupts rather than physical interrupts.
- We have device B with its interrupt wire going into the interrupt
combiner.
- The device driver for Device B is some standard driver that expects to
register for an interrupt resource.
To solve this problem, we could make device A as a GPIO controller (i.e. device A would produce GPIO interrupts instead of *real* interrupts), but that would require a change to the driver for device B, which is not a valid option for a lot of standard/common drivers. There does seem to be a concept of interrupt producers and consumers in the ACPI specification, but it seems to only be used in reference to PCI. Note that generally the OSPM seems to ignore the Producer/Consumer flag and Resource Source fields when given in the Extended Interrupt Descriptor. This is handled quite easily in device tree based systems.
- Device A is implemented as an irqchip
- Device B interrupt resource references Device A as the source of the
interrupt.
- Device A raises handles summary interrupt, determines it needs to
interrupt device B, raises a virtual interrupt to device B.
It is a desirable capability (on both mobile and server platforms), and we would like to have a mechanism to handle this in ACPI. This ECR attempts to better define the language around the extended interrupt descriptor to enable this functionality without significant change to the actual ACPI specification."
This ECR was approved, please let me know if you have further questions.
Thanks Hanjun
Regards,
Leif
On Thu, Oct 27, 2016 at 11:15:12AM +0800, Heyi Guo wrote:
Use irq producer/consumer to represent the topology of device and mbi-gen:
We are using _PRS methd to indicate number of irq pins instead of num_pins in DT.
For mbi-gen, Device(MBI0) { Name(_HID, "HISI0152") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
Name (_PRS, ResourceTemplate() { Interrupt(ResourceProducer,...) {12,14,....} }) }For devices,
Device(COM0) { Name(_HID, "ACPIIDxx") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xb0030000, 0x10000) Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12} }) }Update the DSDT as above.
Change-Id: I39140bd47c2e39ec2bbdf5e71faba7bab775d635 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hanjun Guo hanjun.guo@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 6 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 163 ++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 18 +-- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 4 files changed, 174 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index d8d453a..9a7fdb0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -150,12 +150,12 @@ Scope(_SB) Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,@@ -170,7 +170,7 @@ Scope(_SB) 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 4eaa073..5456bd8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -22,6 +22,10 @@ Scope(_SB) Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -38,6 +42,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ){576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -53,6 +95,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
Name(_PRS, ResourceTemplate() {Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ){192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ){608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -68,6 +148,45 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) })
+Name(_PRS, ResourceTemplate() {
- Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
{576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,){960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,){1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,}+})
- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -76,7 +195,7 @@ Scope(_SB) } }) }
+/* Device(MBI4) { // Mbi-gen dsa1 dbg0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") @@ -106,13 +225,53 @@ Scope(_SB) } }) }
+*/ Device(MBI6) { // Mbi-gen dsa sas0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ){601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index ce8ccd6..de21b2d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -21,8 +21,8 @@ Scope(_SB) Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6"){ 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79,@@ -45,7 +45,7 @@ Scope(_SB) 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI6" ) { 601,602,603,604, 605,606,607,608,609,@@ -93,12 +93,12 @@ Scope(_SB)
Device(SAS1) { Name(_HID, "HISI0162")
- Name(_CCA, 1)
Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI1"){ 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79,@@ -121,7 +121,7 @@ Scope(_SB) 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") { 576,577,578,579,580, 581,582,583,584,585,@@ -174,7 +174,7 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") { 192,193,194,195,196, 197,198,199,200,201,@@ -198,7 +198,7 @@ Scope(_SB) 287, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") { 608,609,610,611, 612,613,614,615,616,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 28ba03d..8429a4b 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -32,7 +32,7 @@ Scope(_SB) 0xa7020000, // Address Base 0x00010000, // Address Length )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 0x00000041, }-- 1.9.1
On 2016/11/16 20:40, Leif Lindholm wrote:
Thanks.
Can I take that as a reviewed-by?
Yes, please :)
Thanks Hanjun
/ Leif
On Tue, Nov 15, 2016 at 01:32:19PM +0800, Hanjun Guo wrote:
Hi Leif,
On 2016/11/6 0:49, Leif Lindholm wrote:
Graeme?
Looks plausible to me, but I don't have the ACPI background.
This is mirroring the new ECR for ACPI spec, which is:
https://mantis.uefi.org/mantis/view.php?id=1588
"Clarifies how interrupt producers and consumers are handled in ACPI. The concept of interrupt producers is easily described and supported in device tree based systems, but it seems this is not really covered by currently ACPI based systems. Consider an example use-case with the following components:
- We have device A, which is an “interrupt combiner” that multiplexes a
large group of interrupt wires and produces a single summary interrupt (in a very similar way to GPIO controllers). This device can be considered as an interrupt producer, but outputs virtual interrupts rather than physical interrupts.
- We have device B with its interrupt wire going into the interrupt
combiner.
- The device driver for Device B is some standard driver that expects to
register for an interrupt resource.
To solve this problem, we could make device A as a GPIO controller (i.e. device A would produce GPIO interrupts instead of *real* interrupts), but that would require a change to the driver for device B, which is not a valid option for a lot of standard/common drivers. There does seem to be a concept of interrupt producers and consumers in the ACPI specification, but it seems to only be used in reference to PCI. Note that generally the OSPM seems to ignore the Producer/Consumer flag and Resource Source fields when given in the Extended Interrupt Descriptor. This is handled quite easily in device tree based systems.
- Device A is implemented as an irqchip
- Device B interrupt resource references Device A as the source of the
interrupt.
- Device A raises handles summary interrupt, determines it needs to
interrupt device B, raises a virtual interrupt to device B.
It is a desirable capability (on both mobile and server platforms), and we would like to have a mechanism to handle this in ACPI. This ECR attempts to better define the language around the extended interrupt descriptor to enable this functionality without significant change to the actual ACPI specification."
This ECR was approved, please let me know if you have further questions.
Thanks Hanjun
Regards,
Leif
On Thu, Oct 27, 2016 at 11:15:12AM +0800, Heyi Guo wrote:
Use irq producer/consumer to represent the topology of device and mbi-gen:
We are using _PRS methd to indicate number of irq pins instead of num_pins in DT.
For mbi-gen, Device(MBI0) { Name(_HID, "HISI0152") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
Name (_PRS, ResourceTemplate() { Interrupt(ResourceProducer,...) {12,14,....} }) }For devices,
Device(COM0) { Name(_HID, "ACPIIDxx") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xb0030000, 0x10000) Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12} }) }Update the DSDT as above.
Change-Id: I39140bd47c2e39ec2bbdf5e71faba7bab775d635 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hanjun Guo hanjun.guo@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 6 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 163 ++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 18 +-- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 4 files changed, 174 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index d8d453a..9a7fdb0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -150,12 +150,12 @@ Scope(_SB) Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,@@ -170,7 +170,7 @@ Scope(_SB) 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") { 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 4eaa073..5456bd8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -22,6 +22,10 @@ Scope(_SB) Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -38,6 +42,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ){576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -53,6 +95,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
Name(_PRS, ResourceTemplate() {Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ){192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ){608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -68,6 +148,45 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) })
+Name(_PRS, ResourceTemplate() {
- Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
{576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,){960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,}Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,){1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,}+})
- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
@@ -76,7 +195,7 @@ Scope(_SB) } }) }
+/* Device(MBI4) { // Mbi-gen dsa1 dbg0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") @@ -106,13 +225,53 @@ Scope(_SB) } }) }
+*/ Device(MBI6) { // Mbi-gen dsa sas0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) })
- Name(_PRS, ResourceTemplate() {
Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, ){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,}Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ){601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,}})- Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package ()
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index ce8ccd6..de21b2d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -21,8 +21,8 @@ Scope(_SB) Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6"){ 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79,@@ -45,7 +45,7 @@ Scope(_SB) 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI6" ) { 601,602,603,604, 605,606,607,608,609,@@ -93,12 +93,12 @@ Scope(_SB)
Device(SAS1) { Name(_HID, "HISI0162")
- Name(_CCA, 1)
Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ){
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI1"){ 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79,@@ -121,7 +121,7 @@ Scope(_SB) 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1") { 576,577,578,579,580, 581,582,583,584,585,@@ -174,7 +174,7 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") { 192,193,194,195,196, 197,198,199,200,201,@@ -198,7 +198,7 @@ Scope(_SB) 287, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") { 608,609,610,611, 612,613,614,615,616,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 28ba03d..8429a4b 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -32,7 +32,7 @@ Scope(_SB) 0xa7020000, // Address Base 0x00010000, // Address Length )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 0x00000041, }-- 1.9.1
This patch adds the support of RoCE to the DSDT and IORT ACPI Tables. Following are the changes: 1. adds the support of a RoCE device to the HNS DSDT file. RoCE DEVICE node properties added are: * eth-handle * dsaf-handle * interrupt-parent * interrupt-names 2. Interrupt node 3. Addition of MbiGen RoCE "named-component" node in the IORT Table.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta salil.mehta@huawei.com --- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 33 ++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 56 +++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 23 ++++++++- 3 files changed, 109 insertions(+), 3 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index e02b4d5..db98305 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -7,7 +7,7 @@ * Format: [ByteLength] FieldName : HexFieldValue */ [0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 0000029e +[0004] Table Length : 000002e4 [0001] Revision : 00 [0001] Checksum : BC [0006] Oem ID : "HISI " @@ -249,6 +249,37 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 1
+/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI7" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + /* RC 0 */ [0001] Type : 02 [0002] Length : 0034 diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 9a7fdb0..83cea5e 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -558,5 +558,59 @@ Scope(_SB) } }) } - + Device (ROCE) { + Name(_HID, "HISI00D1") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"eth-handle", Package () {_SB.ETH0, _SB.ETH1, 0, 0, _SB.ETH4, _SB.ETH5}}, + Package () {"dsaf-handle", Package (){_SB.DSF0}}, + Package () {"interrupt-parent", Package() {_SB.MBI7}}, + Package () {"interrupt-names", Package() {"hns-roce-comp-0", + "hns-roce-comp-1", + "hns-roce-comp-2", + "hns-roce-comp-3", + "hns-roce-comp-4", + "hns-roce-comp-5", + "hns-roce-comp-6", + "hns-roce-comp-7", + "hns-roce-comp-8", + "hns-roce-comp-9", + "hns-roce-comp-10", + "hns-roce-comp-11", + "hns-roce-comp-12", + "hns-roce-comp-13", + "hns-roce-comp-14", + "hns-roce-comp-15", + "hns-roce-comp-16", + "hns-roce-comp-17", + "hns-roce-comp-18", + "hns-roce-comp-19", + "hns-roce-comp-20", + "hns-roce-comp-21", + "hns-roce-comp-22", + "hns-roce-comp-23", + "hns-roce-comp-24", + "hns-roce-comp-25", + "hns-roce-comp-26", + "hns-roce-comp-27", + "hns-roce-comp-28", + "hns-roce-comp-29", + "hns-roce-comp-30", + "hns-roce-comp-31", + "hns-roce-async", + "hns-roce-common"}}, + } + }) + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI7") + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) + } } diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 5456bd8..afd6b47 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -280,5 +280,26 @@ Name(_PRS, ResourceTemplate() { } }) } - + Device(MBI7) { // Mbi-gen roce intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name (_PRS, ResourceTemplate (){ + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 34} + } + }) + } }
Graeme, help :)
Regards,
Leif
On Thu, Oct 27, 2016 at 11:15:13AM +0800, Heyi Guo wrote:
This patch adds the support of RoCE to the DSDT and IORT ACPI Tables. Following are the changes:
- adds the support of a RoCE device to the HNS DSDT file. RoCE DEVICE node properties added are:
- eth-handle
- dsaf-handle
- interrupt-parent
- interrupt-names
- Interrupt node
- Addition of MbiGen RoCE "named-component" node in the IORT Table.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta salil.mehta@huawei.com
.../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 33 ++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 56 +++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 23 ++++++++- 3 files changed, 109 insertions(+), 3 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index e02b4d5..db98305 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -7,7 +7,7 @@
- Format: [ByteLength] FieldName : HexFieldValue
*/ [0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 0000029e +[0004] Table Length : 000002e4 [0001] Revision : 00 [0001] Checksum : BC [0006] Oem ID : "HISI " @@ -249,6 +249,37 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 1 +/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0Write Allocate : 0Read Allocate : 0Override : 0+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0Device Attribute : 0+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI7" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000
Single Mapping : 1/* RC 0 */ [0001] Type : 02 [0002] Length : 0034 diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 9a7fdb0..83cea5e 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -558,5 +558,59 @@ Scope(_SB) } }) }
- Device (ROCE) {
- Name(_HID, "HISI00D1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}},Package () {"dsaf-handle", Package (){\_SB.DSF0}},Package () {"interrupt-parent", Package() {\_SB.MBI7}},Package () {"interrupt-names", Package() {"hns-roce-comp-0","hns-roce-comp-1","hns-roce-comp-2","hns-roce-comp-3","hns-roce-comp-4","hns-roce-comp-5","hns-roce-comp-6","hns-roce-comp-7","hns-roce-comp-8","hns-roce-comp-9","hns-roce-comp-10","hns-roce-comp-11","hns-roce-comp-12","hns-roce-comp-13","hns-roce-comp-14","hns-roce-comp-15","hns-roce-comp-16","hns-roce-comp-17","hns-roce-comp-18","hns-roce-comp-19","hns-roce-comp-20","hns-roce-comp-21","hns-roce-comp-22","hns-roce-comp-23","hns-roce-comp-24","hns-roce-comp-25","hns-roce-comp-26","hns-roce-comp-27","hns-roce-comp-28","hns-roce-comp-29","hns-roce-comp-30","hns-roce-comp-31","hns-roce-async","hns-roce-common"}},}- })
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000)Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI7"){722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,746, 747, 748, 749, 750, 751, 752, 753, 785, 754,}- })
- }
} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 5456bd8..afd6b47 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -280,5 +280,26 @@ Name(_PRS, ResourceTemplate() { } }) }
- Device(MBI7) { // Mbi-gen roce intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)- })
- Name (_PRS, ResourceTemplate (){
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,){722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,746, 747, 748, 749, 750, 751, 752, 753, 785, 754,}- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 34}}- })
- }
}
1.9.1
In the Hip06 SoC, the RoCE Engine is part of the HiSilicon Network Subsystem and is dependent upon DSAF module. Therefore, certain functions like RESET are exposed through the common registers of HNS module which are memory-mapped by the HNS driver and currently can only be accessed through DT/syscon interface.
This patch adds the support of the RoCE Reset functionality through ACPI interface. This functionality would be exposed to the HiSilicon HNS Driver using the _DSM() ACPI Method. This method shall be called by the wrapper API in HNS driver. Further, HiSilicon RoCE driver shall call the HNS Driver exported RoCE Reset API.
In this patch, DSDT ACPI Table have been amended to facilitate such support.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta salil.mehta@huawei.com --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 79 +++++++++++++++++++++- 1 file changed, 77 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 83cea5e..192e76d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -115,6 +115,33 @@ Scope(_SB) , 31, //RESERVED }
+ // DSAF Channel RESET + OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8) + Field(DCRR, DWordAcc, NoLock, Preserve) { + DCRE, 1, + , 31, //RESERVED + DCRD, 1, + , 31, //RESERVED + } + + // RoCE RESET + OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8) + Field(RKRR, DWordAcc, NoLock, Preserve) { + RKRE, 1, + , 31, //RESERVED + RKRD, 1, + , 31, //RESERVED + } + + // RoCE Clock enable/disable + OperationRegion(RKCR, SystemMemory, 0xC0000328, 8) + Field(RKCR, DWordAcc, NoLock, Preserve) { + RCLE, 1, + , 31, //RESERVED + RCLD, 1, + , 31, //RESERVED + } + // Hilink access sel cfg reg OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) Field(HSER, DWordAcc, NoLock, Preserve) { @@ -254,6 +281,30 @@ Scope(_SB) } }
+ //reset DSAF channels + //Arg0 : mask + //Arg1 : 0 reset, 1 de-reset + Method(DCRT, 2, Serialized) { + If (LEqual (Arg1, 0)) { + Store(Arg0, DCRE) + } Else { + Store(Arg0, DCRD) + } + } + + //reset RoCE + //Arg0 : 0 reset, 1 de-reset + Method(RRST, 1, Serialized) { + If (LEqual (Arg0, 0)) { + Store(0x1, RKRE) + } Else { + Store(0x1, RCLD) + Store(0x1, RKRD) + sleep(20) + Store(0x1, RCLE) + } + } + // Set Serdes Loopback //Arg0 : port //Arg1 : 0 disable, 1 enable @@ -307,7 +358,7 @@ Scope(_SB) }
//Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) + //Arg0 : reset type (1: dsaf; 2: ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce) //Arg1 : port //Arg2 : 0 disable, 1 enable Method(DRST, 3, Serialized) @@ -363,6 +414,22 @@ Scope(_SB) Store (Arg2, Local1) GRST (Local0, Local1) } + + //Reset DSAF Channels + case (0x6) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + DCRT (Local0, Local1) + } + + //Reset RoCE + case (0x7) + { + // Discarding Arg1 as it is always 0 + Store (Arg2, Local0) + RRST (Local0) + } } }
@@ -373,7 +440,7 @@ Scope(_SB) // Arg2: Integer Function Index // 0 : Return Supported Functions bit mask // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce) // Arg3[1] : port index in dsaf // Arg3[2] : 0 reset, 1 cancle reset // 2 : Set Serdes Loopback @@ -612,5 +679,13 @@ Scope(_SB) 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, } }) + Name (_PRS, ResourceTemplate (){ + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) } }
This patch adds new "node-guid" parameter in ACPI DSDT Table. This is required for RoCE CM(Conenction Mode) feature.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta salil.mehta@huawei.com --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 1 + 1 file changed, 1 insertion(+)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 192e76d..384e27f 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -633,6 +633,7 @@ Scope(_SB) Package () { Package () {"eth-handle", Package () {_SB.ETH0, _SB.ETH1, 0, 0, _SB.ETH4, _SB.ETH5}}, Package () {"dsaf-handle", Package (){_SB.DSF0}}, + Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes Package () {"interrupt-parent", Package() {_SB.MBI7}}, Package () {"interrupt-names", Package() {"hns-roce-comp-0", "hns-roce-comp-1",
Change-Id: I838ab4b8c8e39f31fdb646e6a67e0bd7e986116b Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 4 ++-- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 2 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index db98305..09245b8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -10,8 +10,8 @@ [0004] Table Length : 000002e4 [0001] Revision : 00 [0001] Checksum : BC -[0006] Oem ID : "HISI " -[0008] Oem Table ID : "HISI1610" +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HIP06 " [0004] Oem Revision : 00000000 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20151124 diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl index ca8b2dc..4185f80 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -18,7 +18,7 @@
#include "Hi1610Platform.h"
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI1610", EFI_ACPI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP06 ", EFI_ACPI_ARM_OEM_REVISION) { include ("Lpc.asl") include ("D03Mbig.asl") include ("CPU.asl") diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h index e8a1577..5a95b02 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h @@ -23,8 +23,8 @@ // // ACPI table information used to initialize tables. // -#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','1','6','1','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long #define EFI_ACPI_ARM_OEM_REVISION 0x00000000 #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') #define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
Change-Id: I838ab4b8c8e39f41fda646e6a67e0bd7e986114a Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h | 4 ++-- Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl index f156e1b..c0cc6d2 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl @@ -18,7 +18,7 @@
#include "Pv660Platform.h"
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI0660", EFI_ACPI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP05 ", EFI_ACPI_ARM_OEM_REVISION) { include ("Mbig.asl") include ("CPU.asl") include ("Com.asl") diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index 9ba3d55..bcd31d6 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -11,7 +11,7 @@ [0001] Revision : 00 [0001] Checksum : BC [0006] Oem ID : "HISI " -[0008] Oem Table ID : "HISI0660" +[0008] Oem Table ID : "HIP05 " [0004] Oem Revision : 00000000 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20151124 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h index 3d69d96..5c5b0f1 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h @@ -23,8 +23,8 @@ // // ACPI table information used to initialize tables. // -#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','0','6','6','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','5',' ',' ',' ') // OEM table id 8 bytes long #define EFI_ACPI_ARM_OEM_REVISION 0x00000000 #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') #define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL index 29b3ff4..fa2c2d8 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL @@ -20,7 +20,7 @@ DefinitionBlock ( "SASSSDT.aml", // Output Filename "SSDT", // Signature 0x01, // SSDT Compliance Revision - "HISI", // OEM ID + "HISI ", // OEM ID "SAS0", // Table ID EFI_ACPI_ARM_OEM_REVISION // OEM Revision ) diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL index e82ee4c..f00664c 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL @@ -21,7 +21,7 @@ DefinitionBlock ( "SATASSDT.aml", // Output Filename "SSDT", // Signature 0x01, // DSDT Compliance Revision - "HISI", // OEM ID + "HISI ", // OEM ID "SATA", // Table ID EFI_ACPI_ARM_OEM_REVISION // OEM Revision )
The length field of GTDT table should be the whole length of entire Generic Timer Description Table.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kefeng Wang wangkefeng.wang@huawei.com --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc index 4032382..922f5c3 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -56,7 +56,7 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc index 3caf144..f677feb 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc @@ -56,7 +56,7 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 2228e51..c11fa4e 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -156,7 +156,7 @@ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Estuary v2.2 D02 UEFI" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D02 UEFI 16.08 RC1"
gHisiTokenSpaceGuid.PcdSystemProductName|L"D02" gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 29cc043..b144c57 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -183,7 +183,7 @@ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Estuary v2.2 D03 UEFI" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.08 RC1"
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
On Thu, Oct 27, 2016 at 11:15:19AM +0800, Heyi Guo wrote:
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 2228e51..c11fa4e 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -156,7 +156,7 @@ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Estuary v2.2 D02 UEFI"
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D02 UEFI 16.08 RC1"
gHisiTokenSpaceGuid.PcdSystemProductName|L"D02" gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 29cc043..b144c57 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -183,7 +183,7 @@ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Estuary v2.2 D03 UEFI"
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.08 RC1"
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" -- 1.9.1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com --- .../Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 07dae5f..61473e8 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -226,7 +226,7 @@ GetCacheSocketStr ( OUT CHAR16 *CacheSocketStr ) { - UINTN CacheSocketStrLen = 0; + UINTN CacheSocketStrLen;
if(CacheLevel == CPU_CACHE_L1_Instruction) { @@ -258,7 +258,6 @@ UpdateSmbiosCacheTable ( CACHE_SRAM_TYPE_DATA CacheSramType = {0};
CoreCount = 16; // Default value is 16 Core - CacheSize = 0;
// // Set Cache Configuration @@ -490,6 +489,7 @@ AddSmbiosProcessorTypeTable ( CHAR16 *CpuVersion; STRING_REF TokenToUpdate;
+ UINT64 *ProcessorId; Type4Record = NULL; ProcessorManuStr = NULL; ProcessorVersionStr = NULL; @@ -614,6 +614,8 @@ AddSmbiosProcessorTypeTable ( Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data;
Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000); + ProcessorId = (UINT64 *)&(Type4Record->ProcessorId); + *ProcessorId = ArmReadMidr();
OptionalStrStart = (CHAR8 *) (Type4Record + 1); UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart);
Some kind of commit message body, please.
On Thu, Oct 27, 2016 at 11:15:20AM +0800, Heyi Guo wrote:
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com
.../Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 07dae5f..61473e8 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -226,7 +226,7 @@ GetCacheSocketStr ( OUT CHAR16 *CacheSocketStr ) {
- UINTN CacheSocketStrLen = 0;
- UINTN CacheSocketStrLen;
This does not look functionally related to the described changeset. Should is be a separate bugfix?
if(CacheLevel == CPU_CACHE_L1_Instruction) { @@ -258,7 +258,6 @@ UpdateSmbiosCacheTable ( CACHE_SRAM_TYPE_DATA CacheSramType = {0}; CoreCount = 16; // Default value is 16 Core
- CacheSize = 0;
This too looks unrelated.
// // Set Cache Configuration @@ -490,6 +489,7 @@ AddSmbiosProcessorTypeTable ( CHAR16 *CpuVersion; STRING_REF TokenToUpdate;
- UINT64 *ProcessorId; Type4Record = NULL; ProcessorManuStr = NULL; ProcessorVersionStr = NULL;
@@ -614,6 +614,8 @@ AddSmbiosProcessorTypeTable ( Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data; Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000);
- ProcessorId = (UINT64 *)&(Type4Record->ProcessorId);
- *ProcessorId = ArmReadMidr();
OptionalStrStart = (CHAR8 *) (Type4Record + 1); UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart); -- 1.9.1
Add OemIsNeedDisableExpanderBuffer() interface for SAS driver.
Change-Id: I85262a7800cb0a22e6ddc072d566b9df4405a126 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com --- Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index 75b23d5..c673c42 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -143,3 +143,8 @@ VOID OemBiosSwitch(UINT32 Master) (VOID)Master; return; } + +BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{ + return TRUE; +}
On Thu, Oct 27, 2016 at 11:15:21AM +0800, Heyi Guo wrote:
Add OemIsNeedDisableExpanderBuffer() interface for SAS driver.
If not added with a patch making use of it, please add a commit message explaining when and how it will be used by something.
Change-Id: I85262a7800cb0a22e6ddc072d566b9df4405a126 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com
Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index 75b23d5..c673c42 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -143,3 +143,8 @@ VOID OemBiosSwitch(UINT32 Master) (VOID)Master; return; }
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{
- return TRUE;
+}
1.9.1
Set the PCD to 0 so that the code will read frequency from register and be adapted to 66M and 50M boards.
Change-Id: I5ca7e766a592de27c8151752e749e480af896671 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com --- Platforms/Hisilicon/D03/D03.dsc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index b144c57..7167f4d 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -219,7 +219,9 @@ # # ARM Architectual Timer Frequency # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|66000000 + # Set it to 0 so that the code will read frequence from register and be + # adapted to 66M and 50M boards + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
On Thu, Oct 27, 2016 at 11:15:22AM +0800, Heyi Guo wrote:
Set the PCD to 0 so that the code will read frequency from register and be adapted to 66M and 50M boards.
Does 66M and 50M refer to different kinds of reference clocks?
Change-Id: I5ca7e766a592de27c8151752e749e480af896671 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com
Platforms/Hisilicon/D03/D03.dsc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index b144c57..7167f4d 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -219,7 +219,9 @@ # # ARM Architectual Timer Frequency #
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|66000000
- # Set it to 0 so that the code will read frequence from register and be
- # adapted to 66M and 50M boards
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE -- 1.9.1
Read reference clock from ARCH timer frequency and set it into DT.
Change-Id: I7a305b78512bcbaaab4ed3adc2675800c2462f46 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com --- .../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 64 ++++++++++++++++++++++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 8 ++- 2 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c index b8b9503..f9db938 100755 --- a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c +++ b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c @@ -19,6 +19,7 @@ #include <Library/IoLib.h> #include <Library/DebugLib.h> #include <Library/UefiBootServicesTableLib.h> +#include <Library/ArmArchTimer.h> #include <Library/FdtUpdateLib.h> #include <PlatformArch.h> #include <Library/PcdLib.h> @@ -183,6 +184,67 @@ DelPhyhandleUpdateMacAddress(IN VOID* Fdt) return Status; }
+STATIC +EFI_STATUS +UpdateRefClk (IN VOID* Fdt) +{ + INTN node; + INTN Error; + struct fdt_property *m_prop; + int m_oldlen; + UINTN ArchTimerFreq = 0; + UINT32 Data; + CONST CHAR8 *Property = "clock-frequency"; + + ArmArchTimerReadReg (CntFrq, &ArchTimerFreq); + if (!ArchTimerFreq) + { + DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Get timer frequency failed!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + node = fdt_subnode_offset(Fdt, 0, "soc"); + if (node < 0) + { + DEBUG ((EFI_D_ERROR, "can not find soc root node\n")); + return EFI_INVALID_PARAMETER; + } + + node = fdt_subnode_offset(Fdt, node, "refclk"); + if (node < 0) + { + DEBUG ((EFI_D_ERROR, "can not find refclk node\n")); + return EFI_INVALID_PARAMETER; + } + + m_prop = fdt_get_property_w(Fdt, node, Property, &m_oldlen); + if(!m_prop) + { + DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Can't find property %a\n", __FUNCTION__, __LINE__, Property)); + return EFI_INVALID_PARAMETER; + } + + Error = fdt_delprop(Fdt, node, Property); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR: fdt_delprop() %a: %a\n", Property, fdt_strerror (Error))); + return EFI_INVALID_PARAMETER; + } + + // UINT32 is enough for refclk data length + Data = (UINT32) ArchTimerFreq; + Data = cpu_to_fdt32 (Data); + Error = fdt_setprop(Fdt, node, Property, &Data, sizeof(Data)); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop() %a: %a\n", Property, fdt_strerror (Error))); + return EFI_INVALID_PARAMETER; + } + + DEBUG ((EFI_D_INFO, "Update refclk successfully.\n")); + return EFI_SUCCESS; +} + INTN GetMemoryNode(VOID* Fdt) { @@ -401,6 +463,8 @@ EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr) Status = EFI_SUCCESS; }
+ // Ignore the return status and continue running + (VOID) UpdateRefClk (Fdt);
Status = UpdateMemoryNode(Fdt); if (EFI_ERROR (Status)) diff --git a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf index b885eae..816f6f5 100755 --- a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf +++ b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -29,13 +29,15 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec EmbeddedPkg/EmbeddedPkg.dec OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] - FdtLib - PlatformSysCtrlLib - OemMiscLib + ArmLib + FdtLib + PlatformSysCtrlLib + OemMiscLib
[Protocols] gHisiBoardNicProtocolGuid
On Thu, Oct 27, 2016 at 11:15:23AM +0800, Heyi Guo wrote:
Read reference clock from ARCH timer frequency and set it into DT.
Change-Id: I7a305b78512bcbaaab4ed3adc2675800c2462f46
Please try to get rid of these change ids for v2.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com
.../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 64 ++++++++++++++++++++++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 8 ++- 2 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c index b8b9503..f9db938 100755 --- a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c +++ b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c @@ -19,6 +19,7 @@ #include <Library/IoLib.h> #include <Library/DebugLib.h> #include <Library/UefiBootServicesTableLib.h> +#include <Library/ArmArchTimer.h>
Don't re-sort this whole list as part of this set, but please insert this one as alphabetically sorted as possible.
#include <Library/FdtUpdateLib.h> #include <PlatformArch.h> #include <Library/PcdLib.h> @@ -183,6 +184,67 @@ DelPhyhandleUpdateMacAddress(IN VOID* Fdt) return Status; } +STATIC +EFI_STATUS +UpdateRefClk (IN VOID* Fdt) +{
- INTN node;
This uses 4-space indentation rather than 2-space indentation. Please change for all parts of this patch.
- INTN Error;
- struct fdt_property *m_prop;
- int m_oldlen;
- UINTN ArchTimerFreq = 0;
- UINT32 Data;
- CONST CHAR8 *Property = "clock-frequency";
- ArmArchTimerReadReg (CntFrq, &ArchTimerFreq);
- if (!ArchTimerFreq)
- {
Move that { onto the if line. (And please apply to other instances in patch too.)
DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Get timer frequency failed!\n", __FUNCTION__, __LINE__));return EFI_INVALID_PARAMETER;- }
- node = fdt_subnode_offset(Fdt, 0, "soc");
- if (node < 0)
- {
DEBUG ((EFI_D_ERROR, "can not find soc root node\n"));return EFI_INVALID_PARAMETER;- }
- node = fdt_subnode_offset(Fdt, node, "refclk");
- if (node < 0)
- {
DEBUG ((EFI_D_ERROR, "can not find refclk node\n"));return EFI_INVALID_PARAMETER;- }
- m_prop = fdt_get_property_w(Fdt, node, Property, &m_oldlen);
- if(!m_prop)
- {
DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Can't find property %a\n", __FUNCTION__, __LINE__, Property));return EFI_INVALID_PARAMETER;- }
- Error = fdt_delprop(Fdt, node, Property);
- if (Error)
- {
DEBUG ((EFI_D_ERROR, "ERROR: fdt_delprop() %a: %a\n", Property, fdt_strerror (Error)));return EFI_INVALID_PARAMETER;- }
- // UINT32 is enough for refclk data length
- Data = (UINT32) ArchTimerFreq;
- Data = cpu_to_fdt32 (Data);
- Error = fdt_setprop(Fdt, node, Property, &Data, sizeof(Data));
- if (Error)
- {
DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop() %a: %a\n", Property, fdt_strerror (Error)));return EFI_INVALID_PARAMETER;- }
- DEBUG ((EFI_D_INFO, "Update refclk successfully.\n"));
- return EFI_SUCCESS;
+}
INTN GetMemoryNode(VOID* Fdt) { @@ -401,6 +463,8 @@ EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr) Status = EFI_SUCCESS; }
- // Ignore the return status and continue running
- (VOID) UpdateRefClk (Fdt);
Why add so many error checks in the definition of the function, only to ignore them all where it is actually used?
Status = UpdateMemoryNode(Fdt); if (EFI_ERROR (Status)) diff --git a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf index b885eae..816f6f5 100755 --- a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf +++ b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -29,13 +29,15 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec
- ArmPkg/ArmPkg.dec
Please insert first in this block.
EmbeddedPkg/EmbeddedPkg.dec OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec [LibraryClasses]
- FdtLib
- PlatformSysCtrlLib
- OemMiscLib
- ArmLib
- FdtLib
- PlatformSysCtrlLib
- OemMiscLib
No unrelated indentation changes, please.
[Protocols] gHisiBoardNicProtocolGuid -- 1.9.1
Memory test may take long time when there is a lot of memory in system, so we disable memory test in BDS to accelerate boot speed.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index c11fa4e..d6fbcb9 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -429,7 +429,7 @@ # # Memory test # - MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf diff --git a/Platforms/Hisilicon/D02/Pv660D02.fdf b/Platforms/Hisilicon/D02/Pv660D02.fdf index ec4d749..c941e4e 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.fdf +++ b/Platforms/Hisilicon/D02/Pv660D02.fdf @@ -278,7 +278,7 @@ READ_LOCK_STATUS = TRUE # INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
On Thu, Oct 27, 2016 at 11:15:24AM +0800, Heyi Guo wrote:
Memory test may take long time when there is a lot of memory in system, so we disable memory test in BDS to accelerate boot speed.
It would be very much preferable if you could make use of the provided facilities and set your BootMode to BOOT_WITH_DEFAULT_SETTINGS or BOOT_WITH_FULL_CONFIGURATION, which would cut the memory test time to 1/16.
Have a look at GenericMemoryTestEntryPoint() and let me know what you think.
/ Leif
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index c11fa4e..d6fbcb9 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -429,7 +429,7 @@ # # Memory test #
- MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf diff --git a/Platforms/Hisilicon/D02/Pv660D02.fdf b/Platforms/Hisilicon/D02/Pv660D02.fdf index ec4d749..c941e4e 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.fdf +++ b/Platforms/Hisilicon/D02/Pv660D02.fdf @@ -278,7 +278,7 @@ READ_LOCK_STATUS = TRUE # INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
-- 1.9.1
Memory test may take long time when there is a lot of memory in system, so we disable memory test in BDS to accelerate boot speed.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 7167f4d..d6c8b7c 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -504,7 +504,7 @@ # # Memory test # - MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index b57a74b..9f8c6f3 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -290,7 +290,7 @@ READ_LOCK_STATUS = TRUE # INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
Refine SAS ASL code indention to EDK2 style.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 276 ++++++++++----------- 1 file changed, 138 insertions(+), 138 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index de21b2d..e19ea18 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -16,56 +16,56 @@
Scope(_SB) { - Device(SAS0) { - Name(_HID, "HISI0162") + Device(SAS0) { + Name(_HID, "HISI0162") Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI6") - { - 64,65,66,67,68, - 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI6") + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI6" ) - { - 601,602,603,604, - 605,606,607,608,609, - 610,611,612,613,614, - 615,616,617,618,619, - 620,621,622,623,624, - 625,626,627,628,629, - 630,631,632, + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI6}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI6}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) + })
OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -89,60 +89,60 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } - } + }
- Device(SAS1) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) + Device(SAS1) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI1") { - 64,65,66,67,68, - 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") - { - 576,577,578,579,580, - 581,582,583,584,585, - 586,587,588,589,590, - 591,592,593,594,595, - 596,597,598,599,600, - 601,602,603,604,605, - 606,607, + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI1}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - Package () {"hip06-sas-v2-quirk-amt", 1}, - } - }) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI1}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + Package () {"hip06-sas-v2-quirk-amt", 1}, + } + })
OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -166,59 +166,59 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } - } + }
- Device(SAS2) { - Name(_HID, "HISI0162") + Device(SAS2) { + Name(_HID, "HISI0162") Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI2") - { - 192,193,194,195,196, - 197,198,199,200,201, - 202,203,204,205,206, - 207,208,209,210,211, - 212,213,214,215,216, - 217,218,219,220,221, - 222,223,224,225,226, - 227,228,229,230,231, - 232,233,234,235,236, - 237,238,239,240,241, - 242,243,244,245,246, - 247,248,249,250,251, - 252,253,254,255,256, - 257,258,259,260,261, - 262,263,264,265,266, - 267,268,269,270,271, - 272,273,274,275,276, - 277,278,279,280,281, - 282,283,284,285,286, - 287, + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI2") - { - 608,609,610,611, - 612,613,614,615,616, - 617,618,619,620,621, - 622,623,624,625,626, - 627,628,629,630,631, - 632,633,634,635,636, - 637,638,639, + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI2") + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI2}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI2}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) + })
OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -242,6 +242,6 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } - } + }
}
On Thu, Oct 27, 2016 at 11:15:26AM +0800, Heyi Guo wrote:
Refine SAS ASL code indention to EDK2 style.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
No functional changes, and looks good to me.
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 276 ++++++++++----------- 1 file changed, 138 insertions(+), 138 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index de21b2d..e19ea18 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -16,56 +16,56 @@ Scope(_SB) {
- Device(SAS0) {
Name(_HID, "HISI0162")
- Device(SAS0) {
- Name(_HID, "HISI0162") Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6"){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6"){64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160, }Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI6" )
{601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,
{601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,}- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI6}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},Package () {"queue-count", 16},Package () {"phy-count", 8}, }
})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI6}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},Package () {"queue-count", 16},Package () {"phy-count", 8},}})
- })
OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -89,60 +89,60 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) }
- }
- }
- Device(SAS1) {
Name(_HID, "HISI0162")Name(_CCA, 1)Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
- Device(SAS1) {
- Name(_HID, "HISI0162")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI1") {
64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
64,65,66,67,68,69,70,71,72,73,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160, }Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1")
{576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,
{576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607, }
})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI1}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 16},Package () {"phy-count", 8},Package () {"hip06-sas-v2-quirk-amt", 1},}})
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI1}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 16},Package () {"phy-count", 8},Package () {"hip06-sas-v2-quirk-amt", 1},}- })
OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -166,59 +166,59 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) }
- }
- }
- Device(SAS2) {
Name(_HID, "HISI0162")
- Device(SAS2) {
- Name(_HID, "HISI0162") Name(_CCA, 1)
Name(_CRS, ResourceTemplate() {Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI2")
{192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,
{192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2"){608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2"){608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,}- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI2}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 16},Package () {"phy-count", 8}, }
})Name (_DSD, Package () {ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package () {Package () {"interrupt-parent",Package() {\_SB.MBI2}},Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},Package () {"queue-count", 16},Package () {"phy-count", 8},}})
- })
OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -242,6 +242,6 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) }
- }
- }
} -- 1.9.1
Check the value of register(0xD000E014) to decide whether this is 50MHZ or 66MHZ board attached. Configure register PHY_CTRL to support 50MHZ or 66MHZ. Default Configure of PHY_CTRL is the configure of 50MHZ, if 66MHZ board attached, change the value of PHY_CTRL.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiang Chen chenxiang66@Hisilicon.com --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 122 ++++++++++++++++++++- 1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index e19ea18..ea4dc76 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -80,6 +80,32 @@ Scope(_SB) STS, 32, }
+ OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -88,6 +114,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + } } }
@@ -157,6 +196,32 @@ Scope(_SB) STS, 32, }
+ OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -165,6 +230,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + } } }
@@ -216,7 +294,7 @@ Scope(_SB) Package () {"interrupt-parent",Package() {_SB.MBI2}}, Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, Package () {"queue-count", 16}, - Package () {"phy-count", 8}, + Package () {"phy-count",9}, } })
@@ -233,6 +311,34 @@ Scope(_SB) STS, 32, }
+ OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + offset (0x2014), + PHY8, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -241,6 +347,20 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + Store(Local1, PHY8) + } } }
Graeme?
Also, minor style comment inline.
On Thu, Oct 27, 2016 at 11:15:27AM +0800, Heyi Guo wrote:
Check the value of register(0xD000E014) to decide whether this is 50MHZ or 66MHZ board attached. Configure register PHY_CTRL to support 50MHZ or 66MHZ. Default Configure of PHY_CTRL is the configure of 50MHZ, if 66MHZ board attached, change the value of PHY_CTRL.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiang Chen chenxiang66@Hisilicon.com
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 122 ++++++++++++++++++++- 1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index e19ea18..ea4dc76 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -80,6 +80,32 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -88,6 +114,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)}@@ -157,6 +196,32 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -165,6 +230,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)}@@ -216,7 +294,7 @@ Scope(_SB) Package () {"interrupt-parent",Package() {_SB.MBI2}}, Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, Package () {"queue-count", 16},
Package () {"phy-count", 8},
Package () {"phy-count",9},
Space before 9.
} })@@ -233,6 +311,34 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,offset (0x2014),PHY8, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -241,6 +347,20 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)Store(Local1, PHY8)}1.9.1
On Sat, Nov 05, 2016 at 11:39:07PM +0000, Leif Lindholm wrote:
Graeme?
Can't see anything I dislike, nice to see some actual _RST code on ARM64!
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
Also, minor style comment inline.
On Thu, Oct 27, 2016 at 11:15:27AM +0800, Heyi Guo wrote:
Check the value of register(0xD000E014) to decide whether this is 50MHZ or 66MHZ board attached. Configure register PHY_CTRL to support 50MHZ or 66MHZ. Default Configure of PHY_CTRL is the configure of 50MHZ, if 66MHZ board attached, change the value of PHY_CTRL.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiang Chen chenxiang66@Hisilicon.com
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 122 ++++++++++++++++++++- 1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index e19ea18..ea4dc76 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -80,6 +80,32 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -88,6 +114,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)}@@ -157,6 +196,32 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -165,6 +230,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)}@@ -216,7 +294,7 @@ Scope(_SB) Package () {"interrupt-parent",Package() {_SB.MBI2}}, Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, Package () {"queue-count", 16},
Package () {"phy-count", 8},
Package () {"phy-count",9},Space before 9.
} })@@ -233,6 +311,34 @@ Scope(_SB) STS, 32, }
- OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400)
- Field (PHYS, DWordAcc, NoLock, Preserve) {
Offset (0x0014),PHY0, 32,Offset (0x0414),PHY1, 32,Offset (0x0814),PHY2, 32,Offset (0x0c14),PHY3, 32,Offset (0x1014),PHY4, 32,Offset (0x1414),PHY5, 32,Offset (0x1814),PHY6, 32,Offset (0x1c14),PHY7, 32,offset (0x2014),PHY8, 32,- }
- OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
- Field (SYSR, DWordAcc, NoLock, Preserve) {
Offset (0xe014),DIE4, 32,- }
- Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST)
@@ -241,6 +347,20 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1)
Store(DIE4, local0)If (LEqual (local0, 0)) {/* 66MHZ */Store(0x0199B694, Local1)Store(Local1, PHY0)Store(Local1, PHY1)Store(Local1, PHY2)Store(Local1, PHY3)Store(Local1, PHY4)Store(Local1, PHY5)Store(Local1, PHY6)Store(Local1, PHY7)Store(Local1, PHY8)}1.9.1
The ehci hardware pin number should be 641, correct it.i
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kefeng Wang wangkefeng@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 2 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index afd6b47..36a9c0c 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -23,7 +23,7 @@ Scope(_SB) })
Name(_PRS, ResourceTemplate() { - Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42} + Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {640, 641} })
Name(_DSD, Package () { diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 8429a4b..5bb03eb 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -34,7 +34,7 @@ Scope(_SB) ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI0") { - 0x00000041, + 641, } }) Return (RBUF) /* _SB_.USB0._CRS.RBUF */
On Thu, Oct 27, 2016 at 11:15:28AM +0800, Heyi Guo wrote:
The ehci hardware pin number should be 641, correct it.i
Drop the trailing 'i'.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kefeng Wang wangkefeng@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 2 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index afd6b47..36a9c0c 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -23,7 +23,7 @@ Scope(_SB) }) Name(_PRS, ResourceTemplate() {
Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42}
Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {640, 641}
This gets confusing though - this is changing 0x41 to 640 (which is not mentioned in commit message) and 0x42 to 641...
})Name(_DSD, Package () { diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 8429a4b..5bb03eb 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -34,7 +34,7 @@ Scope(_SB) ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI0") {
0x00000041,
641,
Whereas this is changing a 0x41 to 641.
} }) Return (RBUF) /* \_SB_.USB0._CRS.RBUF */-- 1.9.1
Change the single mapping flags of mbigen node to 1i
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: MaJun majun258@huawei.com --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index 09245b8..9a045b7 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -60,7 +60,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040080 // device id [0004] Output Reference : 00000034 // point to its dsa -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi1 - sas1, named component */ @@ -91,7 +91,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040000 [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi2 - sas2, named component */ @@ -122,7 +122,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040040 [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi3 - dsa0, srv named component */ @@ -153,7 +153,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040800 [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ @@ -184,7 +184,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040b1c [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ @@ -215,7 +215,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040b1d [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi6 - dsa sas0 named component */ @@ -246,7 +246,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040900 [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen mbi7 - RoCE named component */ @@ -277,7 +277,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040b1e [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* RC 0 */
On Thu, Oct 27, 2016 at 11:15:05AM +0800, Heyi Guo wrote:
Code can also be found in my linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-16.12-07-d02-d03
Patch 1 and 2 are for binary and too large to be sent to mailing list; please find it in the above git repo.
As for D05 series - please send a with --no-binary for v2.
Regards,
Leif
Changelog v1:
*Update D02/D03 platform binaries and bug fixed
- Update Memory init code
- Change ACPI OEM header
- Support RoCE Reset through ACPI method
Chenhui Sun (6): D02/ACPI: Use HISI0031 HID for uart on Hip05 soc Platform/D02: Update ACPI table header Plarform/D03: Update ACPI table header D03: Update ACPI Oem table header id D02: Update ACPI table header id D02/D03: Update version to 16.08 RC1
Hanjun Guo (1): D03/DSDT: use irq producer/consumer to support mbi-gen
Heyi Guo (11): Platforms/D02: Update binaries Platforms/D03: Update binaries D02/D03/D05: Support Spd mirror mode Hisilicon/SMBIOS: Update ProcessorID from MIDR D03/OemMiscLib: Add interface for SAS driver D03: Set PcdArmArchTimerFreqInHz to 0 D03/FdtUpdateLib: Update refclk in DT D02: Disable memory test in BDS D03: Disable memory test in BDS D03/ACPI: Refine SAS ASL code indention D03/USB: fix ehci interrupt pin number
Kefeng Wang (1): D02/D03/ACPI: Fix wrong GTDT length
Kejian Yan (2): D02/D03/Dsdt: add media-type property for hns D02/D03/Dsdt/hns: fix the bug of serdes loopback
MaJun (1): D03/IORT:Change the single mapping flags of mbigen node to 1
Salil Mehta (3): D03/ACPI: Add RoCE device to ACPI & IORT Tables D03/ACPI: Add support of RoCE Reset in DSDT D03/ACPI/ROCE: Add node-guid parameter to DSDT
flyingnosky (1): D03/ACPI: support 50MHZ and 66MHZ boards in acpi mode
.../Library/Hi1610Serdes/Hi1610SerdesLib.lib | Bin 601828 -> 603524 bytes .../Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib | Bin 253328 -> 247176 bytes .../Binary/Hi1610/Library/LpcLib/LpcLib.lib | Bin 13870 -> 13998 bytes .../PlatformSysCtrlLibHi1610.lib | Bin 273980 -> 305230 bytes .../Uart/LpcSerialPortLib/LpcSerialPortLib.lib | Bin 17086 -> 17022 bytes .../Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib | Bin 439708 -> 431524 bytes .../ProcessorSubClassDxe/ProcessorSubClass.c | 6 +- .../Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf | 56 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 368 +++++++++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 85 +++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl | 88 +++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 36 ++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 692 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 305 +++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 261 ++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 367 +++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 136 ++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 29 + .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 91 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 96 +++ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 48 ++ .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 128 ++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc | 81 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc | 115 ++++ Chips/Hisilicon/Include/Library/HwMemInitLib.h | 5 +- .../Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf | 56 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl | 337 ---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc | 85 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 5 +- .../Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 558 ----------------- .../Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl | 125 ---- .../Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl | 261 -------- .../Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl | 247 -------- .../Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl | 136 ---- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- .../Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl | 29 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 16 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl | 25 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl | 152 ----- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl | 39 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 6 +- .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 128 ---- .../Pv660/Pv660AcpiTables/Pv660Platform.h | 10 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc | 81 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc | 115 ---- Platforms/Hisilicon/Binary/D02/Ebl/Ebl.efi | Bin 159744 -> 137056 bytes .../Binary/D02/MemoryInitPei/MemoryInit.efi | Bin 159136 -> 160672 bytes Platforms/Hisilicon/Binary/D02/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/Binary/D02/bl1.bin | Bin 14344 -> 12296 bytes Platforms/Hisilicon/Binary/D02/fip.bin | Bin 45621 -> 45621 bytes .../D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 22304 -> 21696 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 22240 -> 22208 bytes .../Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 26720 -> 25440 bytes .../D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 24704 -> 23712 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 18368 -> 18080 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 63648 -> 56832 bytes .../Binary/D03/Drivers/OhciDxe/NativeOhci.efi | Bin 55488 -> 48352 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 22752 -> 22112 bytes .../Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi | Bin 262144 -> 262144 bytes .../Binary/D03/Drivers/Sas/SasDriverDxe.efi | Bin 233408 -> 210752 bytes .../D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 38624 -> 36480 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 22112 -> 21408 bytes Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi | Bin 159744 -> 134240 bytes .../Library/OemAddressMap2P/OemAddressMap2P.lib | Bin 19568 -> 19486 bytes .../Binary/D03/MemoryInitPei/MemoryInit.efi | Bin 158944 -> 161344 bytes Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/Binary/D03/bl1.bin | Bin 14336 -> 14336 bytes Platforms/Hisilicon/Binary/D03/fip.bin | Bin 45601 -> 45601 bytes Platforms/Hisilicon/D02/Pv660D02.dsc | 4 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 24 +- Platforms/Hisilicon/D03/D03.dsc | 10 +- Platforms/Hisilicon/D03/D03.fdf | 10 +- .../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 64 ++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 8 +- .../D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 + 83 files changed, 3205 insertions(+), 2424 deletions(-) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Sata.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Slit.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc
-- 1.9.1
-
Graeme Gregory -
Hanjun Guo -
Heyi Guo -
Leif Lindholm