The patch that follows would be good to add to our tree.
It isn't critical, but it fixes an issue that Roy was seeing with single core models.
The patch is taken directly from upstream and I tested it here locally, although only on the newer FVP models.
It applied cleanly to our tree, so I don't see any problems taking it and adding it to linaro-topic-misc or somewhere suitable like that. You could even create a new topic for upstream fixes that will be removed next cycle if you wanted to be ultra-organised.
From: Olivier Martin olivier.martin@arm.com
When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero). So the previous assertion was not correct.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin olivier.martin@arm.com
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Drivers/PL390Gic/PL390GicDxe.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c index ce96831..111ce14 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c @@ -378,12 +378,12 @@ InterruptDxeInitialize ( CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value - // cannot be 0. - ASSERT (CpuTarget != 0); - - // The 8 first Interrupt Processor Targets Registers are read-only - for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) { - MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget); + // is 0 when we run on a uniprocessor platform. + if (CpuTarget != 0) { + // The 8 first Interrupt Processor Targets Registers are read-only + for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) { + MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget); + } }
// Set binary point reg to 0x7 (no preemption)
-
Ryan Harkin