From: Yehuda Yitschak yehuday@marvell.com

This patch adds initial support for Armada70x0 SoC's initialization. It implements empty mandatory hooks which are currently mostly empty except for Memory mapping information.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yehuda Yitschak yehuday@marvell.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- .../Armada70x0Lib/AArch64/ArmPlatformHelper.S | 66 +++++++++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 153 +++++++++++++++++++++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 67 +++++++++ .../Library/Armada70x0Lib/Armada70x0LibMem.c | 93 +++++++++++++ 4 files changed, 379 insertions(+) create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c

diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S new file mode 100644 index 0000000..4ad435c --- /dev/null +++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S @@ -0,0 +1,66 @@ +//Based on ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHelper.S +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// Copyright (c) 2016, Marvell. All rights reserved. +// +// This program and the accompanying materials are licensed and made available +// under the terms and conditions of the BSD License which accompanies this +// distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +// + +#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h> + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore) +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask) + +ASM_PFX(ArmPlatformPeiBootAction): + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 4) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0) + ldrh w0, [x0] + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1) + ldrh w1, [x1] + and x0, x0, x1 + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x1) + ldrh w1, [x1] + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq + ret diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c new file mode 100644 index 0000000..8609700 --- /dev/null +++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c @@ -0,0 +1,153 @@ +/**Based on ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Marvell International Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmLib.h> +#include <Library/ArmPlatformLib.h> +#include <Ppi/ArmMpCoreInfo.h> + + +ARM_CORE_INFO mArmada7040MpCoreInfoTable[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 2 + 0x0, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 3 + 0x0, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + } +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + //TODO: Add basic platfrom initialization + + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + //TODO: Initialize DRAM controller here +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + if (ArmIsMpCore()) { + *CoreCount = sizeof(mArmada7040MpCoreInfoTable) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mArmada7040MpCoreInfoTable; + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + if (ArmIsMpCore()) { + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; + } else { + *PpiListSize = 0; + *PpiList = NULL; + } +} + + diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf new file mode 100644 index 0000000..2e2120e --- /dev/null +++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -0,0 +1,67 @@ +# Copyright (C) 2016 Marvell International Ltd. +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Armada7040Lib + FILE_GUID = 3f29b642-4a49-4dfd-8f4a-205dd38432bb + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + ArmLib + DebugLib + MemoryAllocationLib + +[Sources.common] + Armada70x0Lib.c + Armada70x0LibMem.c + +[Sources.AArch64] + AArch64/ArmPlatformHelper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c new file mode 100644 index 0000000..74c9956 --- /dev/null +++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -0,0 +1,93 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include <Base.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + UINTN Index = 0; + + ASSERT (VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + // DDR + VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + + // Configuration space 0xF000_0000 - 0xFFFF_FFFF + VirtualMemoryTable[++Index].PhysicalBase = 0xF0000000; + VirtualMemoryTable[Index].VirtualBase = 0xF0000000; + VirtualMemoryTable[Index].Length = 0x10000000; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = 0; + + ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap = VirtualMemoryTable; +}

From: Yehuda Yitschak yehuday@marvell.com

This patch add initial support for Armada70x0 platform. It includes Armada.dsc.inc and uses Armada70x0.fdf files, which are created with the aim of support for new boards. Code currently supports: - GICv2 - ARM architected timer - ARM watchdog timer - UART port

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yehuda Yitschak yehuday@marvell.com Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Platforms/Marvell/Armada/Armada.dsc.inc | 436 ++++++++++++++++++++++++++++++++ Platforms/Marvell/Armada/Armada70x0.dsc | 48 ++++ Platforms/Marvell/Armada/Armada70x0.fdf | 264 +++++++++++++++++++ 3 files changed, 748 insertions(+) create mode 100644 Platforms/Marvell/Armada/Armada.dsc.inc create mode 100644 Platforms/Marvell/Armada/Armada70x0.dsc create mode 100644 Platforms/Marvell/Armada/Armada70x0.fdf

diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc new file mode 100644 index 0000000..0c81bf0 --- /dev/null +++ b/Platforms/Marvell/Armada/Armada.dsc.inc @@ -0,0 +1,436 @@ +#Copyright (C) 2016 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modification, +#are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +[LibraryClasses.common] + ArmPlatformLib|OpenPlatformPkg/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf + + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + +# Basic utility libraries + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + +# Basic UEFI services libraries + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + # Assume everything is fixed at build. do not use runtime PCD feature + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + # 1/123 faster than Stm or Vstm version + BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # Serial port libraries + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + + # Reset and Time libraries + EfiResetSystemLib|EmbeddedPkg/Library/TemplateResetSystemLib/TemplateResetSystemLib.inf + RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf + + # Networking Requirements for ArmPlatformPkg/Bds + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + + # These libraries are used by the dynamic EFI Shell commands + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + # EBL Related Libraries + EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf + EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf + EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf + EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scripts accessing system memory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf + # SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + + # BDS Libraries + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf + PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + +[LibraryClasses.AARCH64] + ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + +[LibraryClasses.common.SEC] + ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf + + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf + + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM] + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + # + # It is not possible to prevent the ARM compiler for generic intrinsic functions. + # This library provides the instrinsic functions generate by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +[BuildOptions] + *_*_*_PLATFORM_FLAGS = -fno-unwind-tables + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # + # Control what commands are supported from the UI + # Turn these on and off to add features or save size + # + gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE + gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE + + gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE + + # Use the Vector Table location in CpuDxe. + # We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + # If TRUE, Graphics Output Protocol will be installed on virtual + # handle created by ConsplitterDxe. It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + + # USB support + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Marvell" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"MARVELL_EFI" + gArmPlatformTokenSpaceGuid.PcdCoreCount|4 + # gArmPlatformTokenSpaceGuid.PcdClusterCount|1 + + ## Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"Marvell>> " + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1 + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 + + # Required for Intel BDS + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + + # ARM Generic Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000 + + # ARM Architectural Timer Support + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + + # ARM SBSA Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0xF0620000 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0xF0600000 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|34 + + # Serial + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xF0512000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|115200 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|200000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error + +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F +!endif + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" + gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 + gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # We want to use the Shell Libraries but don't want it to initialise + # automatically. We initialise the libraries when the command is called by the + # Shell. + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + # ARM Pcds + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000 + gArmTokenSpaceGuid.PcdSystemMemoryBase|0 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 + gArmTokenSpaceGuid.PcdArmScr|0x531 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # PEI Phase modules + ArmPlatformPkg/PrePi/PeiMPCore.inf + + # DXE + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # Architectural Protocols DXE + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # Console packages + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Human interface: + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # FAT filesystem + GPT/MBR partitioning + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # Application + EmbeddedPkg/Ebl/Ebl.inf + + # Bds - Use Intel BDS + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + + # UEFI application (Shell Embedded Boot Loader) + ShellPkg/Application/Shell/Shell.inf { + <LibraryClasses> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc new file mode 100644 index 0000000..8c7751a --- /dev/null +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -0,0 +1,48 @@ +#Copyright (C) 2016 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modification, +#are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Armada70x0 + PLATFORM_GUID = f837e231-cfc7-4f56-9a0f-5b218d746ae3 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = OpenPlatformPkg/Platforms/Marvell/Armada/Armada70x0.fdf + +!include Armada.dsc.inc diff --git a/Platforms/Marvell/Armada/Armada70x0.fdf b/Platforms/Marvell/Armada/Armada70x0.fdf new file mode 100644 index 0000000..7fb7a5e --- /dev/null +++ b/Platforms/Marvell/Armada/Armada70x0.fdf @@ -0,0 +1,264 @@ +# +# Copyright (C) Marvell International Ltd. and its affiliates +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.Armada70x0_EFI] +BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x400 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x000E0000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +# DXE phase firmware volume +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # PI DXE Drivers producing Architectural Protocols (EFI Services) + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # Multiple Console IO support + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Human interface + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # FAT filesystem + GPT/MBR partitioning + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # UEFI application (Shell Embedded Boot Loader) + INF EmbeddedPkg/Ebl/Ebl.inf + + # UEFI application (Shell Embedded Boot Loader) + INF ShellPkg/Application/Shell/Shell.inf + + # Bds + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + + +# PEI phase firmware volume +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +FvForceRebase = TRUE +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiMPCore.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.ARM.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification. +# It is the reason 4K is used instead of 2K for the module alignment. +[Rule.AARCH64.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + }

From: Jan Dąbroś jsd@semihalf.com

- Create Mpp Library, which allows to set MPP on board. - Create Platforms/Marvell/Marvell.dec file, which holds PCDs' declaration. - Export configuration capabilities via PCDs. - Prepare porting guide document

Because GetMppPcd has to be adjusted to possible 8 MPP registers, although unused, additional PcdChip<X>MppSel are added in order to satisfy preprocessor demands. For the same reason there are MPP PCDs for all of 4 possible chips.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Documentation/Marvell/PortingGuide/Mpp.txt | 48 ++++++++ Platforms/Marvell/Include/Library/MppLib.h | 42 +++++++ Platforms/Marvell/Library/MppLib/MppLib.c | 163 ++++++++++++++++++++++++++++ Platforms/Marvell/Library/MppLib/MppLib.inf | 107 ++++++++++++++++++ Platforms/Marvell/Marvell.dec | 106 ++++++++++++++++++ 5 files changed, 466 insertions(+) create mode 100644 Documentation/Marvell/PortingGuide/Mpp.txt create mode 100644 Platforms/Marvell/Include/Library/MppLib.h create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.c create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.inf create mode 100644 Platforms/Marvell/Marvell.dec

diff --git a/Documentation/Marvell/PortingGuide/Mpp.txt b/Documentation/Marvell/PortingGuide/Mpp.txt new file mode 100644 index 0000000..3e36b5f --- /dev/null +++ b/Documentation/Marvell/PortingGuide/Mpp.txt @@ -0,0 +1,48 @@ +MPP configuration +----------------- +Multi-Purpose Ports (MPP) are configurable through platform PCDs. +In order to set desired pin multiplexing, .dsc file needs to be modified. +(OpenPlatformPkg/Platforms/Marvell/Armada/{platform_name}.dsc - please refer to +Documentation/Build.txt for currently supported {platftorm_name} ) +Following PCDs are available: + + gMarvellTokenSpaceGuid.PcdMppChipCount + +Indicates how many different chips are placed on board. So far up to 4 chips +are supported. + +Every MPP PCD has <Num> part where + <Num> stands for chip ID (order is not important, but configuration will be + set for first PcdMppChipCount chips). + +Below is example for the first chip (Chip0). + + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag + +Indicates that register order is reversed. (Needs to be used only for AP806-Z1) + + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress + +This is base address for MPP configuration register. + + gMarvellTokenSpaceGuid.PcdChip0MppPinCount + +Defines how many MPP pins are available. + + gMarvellTokenSpaceGuid.PcdChip0MppSel0 + gMarvellTokenSpaceGuid.PcdChip0MppSel1 + gMarvellTokenSpaceGuid.PcdChip0MppSel2 + +This registers defines functions of 10 pins in ascending order. + +Examples +-------- +#APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + +Set pin 6 and 7 to 0xa function: + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } diff --git a/Platforms/Marvell/Include/Library/MppLib.h b/Platforms/Marvell/Include/Library/MppLib.h new file mode 100644 index 0000000..77c6cdb --- /dev/null +++ b/Platforms/Marvell/Include/Library/MppLib.h @@ -0,0 +1,42 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MPPLIB_H__ +#define __MPPLIB_H__ + +EFI_STATUS +MppInitialize ( + ); + +#endif diff --git a/Platforms/Marvell/Library/MppLib/MppLib.c b/Platforms/Marvell/Library/MppLib/MppLib.c new file mode 100644 index 0000000..b24743c --- /dev/null +++ b/Platforms/Marvell/Library/MppLib/MppLib.c @@ -0,0 +1,163 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include <Library/ArmLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> + +#define MPP_PIN_VAL(pin,func) (((func) & 0xf) << ((pin) * 4)) +#define MPP_MAX_REGS 8 +#define MPP_PINS_PER_REG 8 +#define PCD_PINS_PER_GROUP 10 + +#define MAX_CHIPS 4 + +#define GET_PCD_PTR(id,num) PcdGetPtr(PcdChip##id##MppSel##num) +#define GET_PIN_COUNT(id) PcdGet32(PcdChip##id##MppPinCount) +#define GET_BASE(id) PcdGet64(PcdChip##id##MppBaseAddress) +#define GET_REV_FLAG(id) PcdGetBool(PcdChip##id##MppReverseFlag) + +/* We get chip number */ +#define GetMppPcd(id) { \ + PinCount[id] = GET_PIN_COUNT(id); \ + MppRegPcd[id][7] = GET_PCD_PTR(id,7); \ + MppRegPcd[id][6] = GET_PCD_PTR(id,6); \ + MppRegPcd[id][5] = GET_PCD_PTR(id,5); \ + MppRegPcd[id][4] = GET_PCD_PTR(id,4); \ + MppRegPcd[id][3] = GET_PCD_PTR(id,3); \ + MppRegPcd[id][2] = GET_PCD_PTR(id,2); \ + MppRegPcd[id][1] = GET_PCD_PTR(id,1); \ + MppRegPcd[id][0] = GET_PCD_PTR(id,0); \ + BaseAddr[id] = GET_BASE(id); \ + ReverseFlag[id] = GET_REV_FLAG(id); \ +} + +STATIC +VOID +SetRegisterValue ( + UINT8 RegCount, + UINT8 **MppRegPcd, + UINTN BaseAddr, + BOOLEAN ReverseFlag + ) +{ + UINT32 i, j, CtrlVal; + INTN Sign; + + Sign = ReverseFlag ? -1 : 1; + + for (i = 0; i < RegCount; i++) { + CtrlVal = 0; + for (j = 0; j < MPP_PINS_PER_REG; j++) { + CtrlVal |= MPP_PIN_VAL(7 * (UINTN) ReverseFlag + j * Sign, + MppRegPcd[i][7 * (UINTN) ReverseFlag + j * Sign]); + } + MmioWrite32 (BaseAddr + 4 * i * Sign, CtrlVal); + } +} + +STATIC +/* Transform PCD MPP group format into hardware register format */ +UINT8 +PcdToMppRegs ( + UINTN PinCount, + UINT8 **MppRegPcd + ) +{ + UINT8 MppRegPcdTmp[MPP_MAX_REGS][MPP_PINS_PER_REG]; + UINT8 PcdGroupCount, MppRegCount; + UINTN i, j, k, l; + + if (PinCount == 0) { + return 0; + } + + PcdGroupCount = PinCount / PCD_PINS_PER_GROUP; + if ((PinCount % PCD_PINS_PER_GROUP) != 0) { + PcdGroupCount += 1; + } + + MppRegCount = PinCount / MPP_PINS_PER_REG; + if ((PinCount % MPP_PINS_PER_REG) != 0) { + MppRegCount += 1; + } + + /* Fill temporary table with data from PCD groups in HW format */ + for (i = 0; i < PcdGroupCount; i++) { + for (j = 0; j < PCD_PINS_PER_GROUP; j++) { + k = (PCD_PINS_PER_GROUP * i + j) / MPP_PINS_PER_REG; + l = (PCD_PINS_PER_GROUP * i + j) % MPP_PINS_PER_REG; + MppRegPcdTmp[k][l] = MppRegPcd[i][j]; + } + } + + /* Update input table */ + for (i = 0; i < MppRegCount; i++) { + for (j = 0; j < MPP_PINS_PER_REG; j++) { + MppRegPcd[i][j] = MppRegPcdTmp[i][j]; + } + } + + return MppRegCount; +} + +EFI_STATUS +MppInitialize ( + ) +{ + UINTN BaseAddr[MAX_CHIPS], PinCount[MAX_CHIPS], RegCount; + BOOLEAN ReverseFlag[MAX_CHIPS]; + UINT8 *MppRegPcd[MAX_CHIPS][MPP_MAX_REGS]; + UINT32 i, ChipCount; + + ChipCount = PcdGet32 (PcdMppChipCount); + + /* Read all needed PCD for MPP configuration */ + GetMppPcd(0); + GetMppPcd(1); + GetMppPcd(2); + GetMppPcd(3); + + for (i = 0; i < MAX_CHIPS; i++) { + if (i == ChipCount) + break; + RegCount = PcdToMppRegs (PinCount[i], MppRegPcd[i]); + SetRegisterValue (RegCount, MppRegPcd[i], BaseAddr[i], ReverseFlag[i]); + } + + return EFI_SUCCESS; +} diff --git a/Platforms/Marvell/Library/MppLib/MppLib.inf b/Platforms/Marvell/Library/MppLib/MppLib.inf new file mode 100644 index 0000000..510064f --- /dev/null +++ b/Platforms/Marvell/Library/MppLib/MppLib.inf @@ -0,0 +1,107 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MarvellMppLib + FILE_GUID = 3f19b642-4a49-4dfd-8f4a-205dd38432bb + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MppLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec + +[LibraryClasses] + ArmLib + DebugLib + MemoryAllocationLib + PcdLib + IoLib + +[Sources.common] + MppLib.c + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdMppChipCount + + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress + gMarvellTokenSpaceGuid.PcdChip0MppPinCount + gMarvellTokenSpaceGuid.PcdChip0MppSel0 + gMarvellTokenSpaceGuid.PcdChip0MppSel1 + gMarvellTokenSpaceGuid.PcdChip0MppSel2 + gMarvellTokenSpaceGuid.PcdChip0MppSel3 + gMarvellTokenSpaceGuid.PcdChip0MppSel4 + gMarvellTokenSpaceGuid.PcdChip0MppSel5 + gMarvellTokenSpaceGuid.PcdChip0MppSel6 + gMarvellTokenSpaceGuid.PcdChip0MppSel7 + + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress + gMarvellTokenSpaceGuid.PcdChip1MppPinCount + gMarvellTokenSpaceGuid.PcdChip1MppSel0 + gMarvellTokenSpaceGuid.PcdChip1MppSel1 + gMarvellTokenSpaceGuid.PcdChip1MppSel2 + gMarvellTokenSpaceGuid.PcdChip1MppSel3 + gMarvellTokenSpaceGuid.PcdChip1MppSel4 + gMarvellTokenSpaceGuid.PcdChip1MppSel5 + gMarvellTokenSpaceGuid.PcdChip1MppSel6 + gMarvellTokenSpaceGuid.PcdChip1MppSel7 + + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress + gMarvellTokenSpaceGuid.PcdChip2MppPinCount + gMarvellTokenSpaceGuid.PcdChip2MppSel0 + gMarvellTokenSpaceGuid.PcdChip2MppSel1 + gMarvellTokenSpaceGuid.PcdChip2MppSel2 + gMarvellTokenSpaceGuid.PcdChip2MppSel3 + gMarvellTokenSpaceGuid.PcdChip2MppSel4 + gMarvellTokenSpaceGuid.PcdChip2MppSel5 + gMarvellTokenSpaceGuid.PcdChip2MppSel6 + gMarvellTokenSpaceGuid.PcdChip2MppSel7 + + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress + gMarvellTokenSpaceGuid.PcdChip3MppPinCount + gMarvellTokenSpaceGuid.PcdChip3MppSel0 + gMarvellTokenSpaceGuid.PcdChip3MppSel1 + gMarvellTokenSpaceGuid.PcdChip3MppSel2 + gMarvellTokenSpaceGuid.PcdChip3MppSel3 + gMarvellTokenSpaceGuid.PcdChip3MppSel4 + gMarvellTokenSpaceGuid.PcdChip3MppSel5 + gMarvellTokenSpaceGuid.PcdChip3MppSel6 + gMarvellTokenSpaceGuid.PcdChip3MppSel7 + diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec new file mode 100644 index 0000000..fee8025 --- /dev/null +++ b/Platforms/Marvell/Marvell.dec @@ -0,0 +1,106 @@ +# Copyright (C) 2016 Marvell International Ltd. +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute and/or +# modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +#* Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +#* Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +#* Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = OpenPlatformMarvellPkg + PACKAGE_GUID = c372916e-83ad-4b2a-8410-bbc31bd9e68f + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ + +[Includes] + Include + +[Guids.common] + gMarvellTokenSpaceGuid = { 0xf995c6c8, 0xbc9b, 0x4e93, { 0xbd, 0xcf, 0x49, 0x90, 0xc6, 0xe7, 0x8c, 0x7f } } + +[PcdsFixedAtBuild.common] +#MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001 + + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE|BOOLEAN|0x30000002 + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0|UINT64|0x30000003 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|0|UINT32|0x30000004 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0 }|VOID*|0x30000005 + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0 }|VOID*|0x30000006 + gMarvellTokenSpaceGuid.PcdChip0MppSel2|{ 0 }|VOID*|0x30000007 + gMarvellTokenSpaceGuid.PcdChip0MppSel3|{ 0 }|VOID*|0x30000008 + gMarvellTokenSpaceGuid.PcdChip0MppSel4|{ 0 }|VOID*|0x30000009 + gMarvellTokenSpaceGuid.PcdChip0MppSel5|{ 0 }|VOID*|0x30000010 + gMarvellTokenSpaceGuid.PcdChip0MppSel6|{ 0 }|VOID*|0x30000011 + gMarvellTokenSpaceGuid.PcdChip0MppSel7|{ 0 }|VOID*|0x30000012 + + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE|BOOLEAN|0x30000013 + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0|UINT64|0x30000014 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|0|UINT32|0x30000015 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0 }|VOID*|0x30000016 + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0 }|VOID*|0x30000017 + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0 }|VOID*|0x30000018 + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0 }|VOID*|0x30000019 + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0 }|VOID*|0x30000020 + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0 }|VOID*|0x30000021 + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0 }|VOID*|0x30000022 + gMarvellTokenSpaceGuid.PcdChip1MppSel7|{ 0 }|VOID*|0x30000023 + + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE|BOOLEAN|0x30000024 + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0|UINT64|0x30000025 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|0|UINT32|0x30000026 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0 }|VOID*|0x30000027 + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0 }|VOID*|0x30000028 + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0 }|VOID*|0x30000029 + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0 }|VOID*|0x30000030 + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0 }|VOID*|0x30000031 + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0 }|VOID*|0x30000032 + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0 }|VOID*|0x30000033 + gMarvellTokenSpaceGuid.PcdChip2MppSel7|{ 0 }|VOID*|0x30000034 + + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE|BOOLEAN|0x30000035 + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0|UINT64|0x30000036 + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|0|UINT32|0x30000037 + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0 }|VOID*|0x30000038 + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0 }|VOID*|0x30000039 + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0 }|VOID*|0x30000040 + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0 }|VOID*|0x30000041 + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0 }|VOID*|0x30000042 + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0 }|VOID*|0x30000043 + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0 }|VOID*|0x30000044 + gMarvellTokenSpaceGuid.PcdChip3MppSel7|{ 0 }|VOID*|0x30000045 +

From: Jan Dąbroś jsd@semihalf.com

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/Marvell/Armada/Armada.dsc.inc | 1 + Platforms/Marvell/Armada/Armada70x0.dsc | 28 ++++++++++++++++++++++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 2 ++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 2 ++ 4 files changed, 33 insertions(+)

diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc index 0c81bf0..3779e82 100644 --- a/Platforms/Marvell/Armada/Armada.dsc.inc +++ b/Platforms/Marvell/Armada/Armada.dsc.inc @@ -31,6 +31,7 @@ # [LibraryClasses.common] ArmPlatformLib|OpenPlatformPkg/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf + MppLib|OpenPlatformPkg/Platforms/Marvell/Library/MppLib/MppLib.inf

DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 8c7751a..9bd66e0 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -46,3 +46,31 @@ FLASH_DEFINITION = OpenPlatformPkg/Platforms/Marvell/Armada/Armada70x0.fdf

!include Armada.dsc.inc + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ +[PcdsFixedAtBuild.common] + #MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|2 + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 } + + # CP110 MPP SET - Router configuration + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c index 8609700..a2b25e1 100644 --- a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c +++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c @@ -15,6 +15,7 @@

#include <Library/ArmLib.h> #include <Library/ArmPlatformLib.h> +#include <Library/MppLib.h> #include <Ppi/ArmMpCoreInfo.h>

@@ -93,6 +94,7 @@ ArmPlatformInitialize (

//TODO: Add basic platfrom initialization

+ MppInitialize (); return RETURN_SUCCESS; }

diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2e2120e..bd78406 100644 --- a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -43,11 +43,13 @@ MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec

[LibraryClasses] ArmLib DebugLib MemoryAllocationLib + MppLib

[Sources.common] Armada70x0Lib.c

From: Bartosz Szczepanek bsz@semihalf.com

MvEeprom driver produces MARVELL_EEPROM_PROTOCOL, which can be used by other drivers or applications. Working EFI_I2C_IO_PROTOCOL is required by driver to operate.

EEPROM devices' addresses need to be fed via 'PcdEepromI2cAddresses'.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bartosz Szczepanek bsz@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Documentation/Marvell/Drivers/EepromDriver.txt | 96 ++++++++ Drivers/I2c/Devices/MvEeprom/MvEeprom.c | 297 +++++++++++++++++++++++++ Drivers/I2c/Devices/MvEeprom/MvEeprom.h | 97 ++++++++ Drivers/I2c/Devices/MvEeprom/MvEeprom.inf | 70 ++++++ Platforms/Marvell/Include/Protocol/Eeprom.h | 60 +++++ Platforms/Marvell/Marvell.dec | 5 + 6 files changed, 625 insertions(+) create mode 100644 Documentation/Marvell/Drivers/EepromDriver.txt create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.c create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.h create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.inf create mode 100644 Platforms/Marvell/Include/Protocol/Eeprom.h

diff --git a/Documentation/Marvell/Drivers/EepromDriver.txt b/Documentation/Marvell/Drivers/EepromDriver.txt new file mode 100644 index 0000000..e2da35f --- /dev/null +++ b/Documentation/Marvell/Drivers/EepromDriver.txt @@ -0,0 +1,96 @@ +1. Introduction +--------------- +**MvEeprom** driver creates MARVELL_EEPROM_PROTOCOL, which ++is used for managing eeprom. + +2. MvEeprom driver design +------------------------- +Every I2C device driver should implement EFI_DRIVER_BINDING_PROTOCOL and +consume EFI_I2C_IO_PROTOCOL for transactions on I2C bus. MvEeprom driver +additionally implements MARVELL_EEPROM_PROTOCOL. + + 2.1 EFI_DRIVER_BINDING_PROTOCOL + ------------------------------- + Driver Binding protocol is extensively covered in UEFI documentation, as + it is not specific to I2C stack. The only difference is that Supported() + function should check if EFI_I2C_IO_PROTOCOL provides valid EFI_GUID and + DeviceIndex values. + Excerpt from MvEepromSupported(): + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &TmpI2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + + /* get EEPROM devices' addresses from PCD */ + EepromAddresses = PcdGetPtr (PcdEepromI2cAddresses); + if (EepromAddresses == 0) { + Status = EFI_UNSUPPORTED; + goto out; + } + + Status = EFI_UNSUPPORTED; + for (i = 0; EepromAddresses[i] != '\0'; i++) { + /* I2C guid must fit and valid DeviceIndex must be provided */ + if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) && + TmpI2cIo->DeviceIndex == EepromAddresses[i]) { + DEBUG((DEBUG_INFO, "A8kEepromSupported: attached to EEPROM device\n")); + Status = EFI_SUCCESS; + break; + } + } + + 2.2 EFI_I2C_IO_PROTOCOL + ----------------------- + This protocol is provided by generic I2C stack. Multiple drivers can use IO + protocol at once, as queueing is implemented. + + QueueRequest is a routine that queues an I2C transaction to the I2C + controller for execution on the I2C bus. + + 2.3 MARVELL_EEPROM_PROTOCOL + ----------------------- + typedef struct _MARVELL_EEPROM_PROTOCOL MARVELL_EEPROM_PROTOCOL; + + #define EEPROM_READ 0x1 + #define EEPROM_WRITE 0x0 + typedef + EFI_STATUS + (EFIAPI *EFI_EEPROM_TRANSFER) ( + IN CONST MARVELL_EEPROM_PROTOCOL *This, + IN UINT16 Address, + IN UINT32 Length, + IN UINT8 *Buffer, + IN UINT8 Operation + ); + + struct _MARVELL_EEPROM_PROTOCOL { + EFI_EEPROM_TRANSFER Transfer; + UINT8 Identifier; + }; + +3. Adding new I2C slave device drivers +-------------------------------------- +In order to support I2C slave device other than EEPROM, new driver should +be created. Required steps follow. + + 1. Create driver directory (OpenPlatformPkg/Drivers/I2c/Devices/...). + 2. Create stubs of .inf and .c files (MvEeprom files are a reference), + include .inf file in platform .dsc and .fdf files. + 3. Implement EFI_DRIVER_BINDING_PROTOCOL - Start(), Stop(), Supported() + functions' implementation is a must. EFI_DRIVER_BINDING_PROTOCOL + should be installed at driver's entry point. + 4. Add I2C address of device to PcdI2cSlaveAddresses in .dsc file. + 5. Test available EFI_I2C_IO_PROTOCOLs in Supported() - find instance + with valid GUID and DeviceIndex (I2C slave address). + 6. Open EFI_I2C_IO_PROTOCOL for usage in Start(). After that, QueueRequest + function should be available. + 7. Implement core functionality of driver (using QueueRequest to access I2C). + 8. (not mandatory) Produce/consume additional protocols. diff --git a/Drivers/I2c/Devices/MvEeprom/MvEeprom.c b/Drivers/I2c/Devices/MvEeprom/MvEeprom.c new file mode 100644 index 0000000..f29528d --- /dev/null +++ b/Drivers/I2c/Devices/MvEeprom/MvEeprom.c @@ -0,0 +1,297 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include <Protocol/DriverBinding.h> +#include <Protocol/I2cIo.h> +#include <Protocol/Eeprom.h> + +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Pi/PiI2c.h> + +#include "MvEeprom.h" + +#define I2C_GUID \ + { \ + 0x391fc679, 0x6cb0, 0x4f01, { 0x9a, 0xc7, 0x8e, 0x1b, 0x78, 0x6b, 0x7a, 0x00 } \ + } + +#define I2C_DEVICE_INDEX(bus, address) (((address) & 0xffff) | (bus) << 16) + +STATIC CONST EFI_GUID I2cGuid = I2C_GUID; + +EFI_DRIVER_BINDING_PROTOCOL gDriverBindingProtocol = { + MvEepromSupported, + MvEepromStart, + MvEepromStop +}; + +EFI_STATUS +EFIAPI +MvEepromSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + EFI_I2C_IO_PROTOCOL *TmpI2cIo; + UINT8 *EepromAddresses; + UINT8 *EepromBuses; + UINTN i; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &TmpI2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + + /* get EEPROM devices' addresses from PCD */ + EepromAddresses = PcdGetPtr (PcdEepromI2cAddresses); + EepromBuses = PcdGetPtr (PcdEepromI2cBuses); + if (EepromAddresses == 0) { + Status = EFI_UNSUPPORTED; + DEBUG((DEBUG_INFO, "MvEepromSupported: I2C device found, but it's not EEPROM\n")); + goto out; + } + + Status = EFI_UNSUPPORTED; + for (i = 0; EepromAddresses[i] != '\0'; i++) { + /* I2C guid must fit and valid DeviceIndex must be provided */ + if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) && + TmpI2cIo->DeviceIndex == I2C_DEVICE_INDEX(EepromBuses[i], + EepromAddresses[i])) { + DEBUG((DEBUG_INFO, "MvEepromSupported: attached to EEPROM device\n")); + Status = EFI_SUCCESS; + break; + } + } + +out: + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + return Status; +} + +EFI_STATUS +EFIAPI +MvEepromTransfer ( + IN CONST MARVELL_EEPROM_PROTOCOL *This, + IN UINT16 Address, + IN UINT32 Length, + IN UINT8 *Buffer, + IN UINT8 Operation + ) +{ + EFI_I2C_REQUEST_PACKET *RequestPacket; + UINTN RequestPacketSize; + EFI_STATUS Status = EFI_SUCCESS; + EEPROM_CONTEXT *EepromContext = EEPROM_SC_FROM_EEPROM(This); + UINT32 BufferLength; + UINT32 Transmitted = 0; + UINT32 CurrentAddress = Address; + + ASSERT(EepromContext != NULL); + ASSERT(EepromContext->I2cIo != NULL); + + RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION) * 2; + RequestPacket = AllocateZeroPool (RequestPacketSize); + if (RequestPacket == NULL) + return EFI_OUT_OF_RESOURCES; + /* First operation contains address, the second is buffer */ + RequestPacket->OperationCount = 2; + RequestPacket->Operation[0].LengthInBytes = 2; + RequestPacket->Operation[0].Buffer = AllocateZeroPool ( RequestPacket->Operation[0].LengthInBytes ); + if (RequestPacket->Operation[0].Buffer == NULL) { + FreePool(RequestPacket); + return EFI_OUT_OF_RESOURCES; + } + RequestPacket->Operation[1].Flags = (Operation == EEPROM_READ ? I2C_FLAG_READ : I2C_FLAG_NORESTART); + + while (Length > 0) { + CurrentAddress = Address + Transmitted; + BufferLength = (Length <= MAX_BUFFER_LENGTH ? Length : MAX_BUFFER_LENGTH); + RequestPacket->Operation[0].Buffer[0] = (CurrentAddress >> 8) & 0xff; + RequestPacket->Operation[0].Buffer[1] = CurrentAddress & 0xff; + RequestPacket->Operation[1].LengthInBytes = BufferLength; + RequestPacket->Operation[1].Buffer = Buffer + Transmitted; + Status = EepromContext->I2cIo->QueueRequest(EepromContext->I2cIo, 0, NULL, RequestPacket, NULL); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "MvEepromTransfer: error %d during transmission\n", Status)); + break; + } + Length -= BufferLength; + Transmitted += BufferLength; + } + + FreePool(RequestPacket->Operation[0].Buffer); + FreePool(RequestPacket); + return Status; +} + +EFI_STATUS +EFIAPI +MvEepromStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EEPROM_CONTEXT *EepromContext; + + EepromContext = AllocateZeroPool (sizeof(EEPROM_CONTEXT)); + if (EepromContext == NULL) { + DEBUG((DEBUG_ERROR, "MvEeprom: allocation fail\n")); + return EFI_OUT_OF_RESOURCES; + } + + EepromContext->ControllerHandle = ControllerHandle; + EepromContext->Signature = EEPROM_SIGNATURE; + EepromContext->EepromProtocol.Transfer = MvEepromTransfer; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &EepromContext->I2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "MvEeprom: failed to open I2cIo\n")); + FreePool(EepromContext); + return EFI_UNSUPPORTED; + } + + EepromContext->EepromProtocol.Identifier = EepromContext->I2cIo->DeviceIndex; + Status = gBS->InstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gMarvellEepromProtocolGuid, &EepromContext->EepromProtocol, + NULL + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "MvEeprom: failed to install EEPROM protocol\n")); + goto fail; + } + + return Status; + +fail: + FreePool(EepromContext); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +MvEepromStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ) +{ + MARVELL_EEPROM_PROTOCOL *EepromProtocol; + EFI_STATUS Status; + EEPROM_CONTEXT *EepromContext; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gMarvellEepromProtocolGuid, + (VOID **) &EepromProtocol, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + EepromContext = EEPROM_SC_FROM_EEPROM(EepromProtocol); + + gBS->UninstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gMarvellEepromProtocolGuid, &EepromContext->EepromProtocol, + &gEfiDriverBindingProtocolGuid, &gDriverBindingProtocol, + NULL + ); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + FreePool(EepromContext); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvEepromInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiDriverBindingProtocolGuid, &gDriverBindingProtocol, + NULL + ); + return Status; +} diff --git a/Drivers/I2c/Devices/MvEeprom/MvEeprom.h b/Drivers/I2c/Devices/MvEeprom/MvEeprom.h new file mode 100644 index 0000000..3feef1e --- /dev/null +++ b/Drivers/I2c/Devices/MvEeprom/MvEeprom.h @@ -0,0 +1,97 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MV_EEPROM_H__ +#define __MV_EEPROM_H__ + +#include <Uefi.h> + +#define EEPROM_SIGNATURE SIGNATURE_32 ('E', 'E', 'P', 'R') + +#define MAX_BUFFER_LENGTH 64 + +/* + * I2C_FLAG_NORESTART is not part of PI spec, it allows to continue + * transmission without repeated start operation. + * FIXME: This flag is also defined in Drivers/I2c/MvI2cDxe/MvI2cDxe.h + * and it's important to have both version synced. This solution is + * temporary and shared flag should be used by both files. + */ +#define I2C_FLAG_NORESTART 0x00000002 + +typedef struct { + UINT32 Signature; + EFI_HANDLE ControllerHandle; + EFI_I2C_IO_PROTOCOL *I2cIo; + MARVELL_EEPROM_PROTOCOL EepromProtocol; +} EEPROM_CONTEXT; + +#define EEPROM_SC_FROM_IO(a) CR (a, EEPROM_CONTEXT, I2cIo, EEPROM_SIGNATURE) +#define EEPROM_SC_FROM_EEPROM(a) CR (a, EEPROM_CONTEXT, EepromProtocol, EEPROM_SIGNATURE) + +EFI_STATUS +EFIAPI +MvEepromSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +MvEepromStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +MvEepromStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ); + +EFI_STATUS +EFIAPI +MvEepromTransfer ( + IN CONST MARVELL_EEPROM_PROTOCOL *This, + IN UINT16 Address, + IN UINT32 Length, + IN UINT8 *Buffer, + IN UINT8 Operation + ); +#endif // __MV_EEPROM_H__ diff --git a/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf b/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf new file mode 100644 index 0000000..219041b --- /dev/null +++ b/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf @@ -0,0 +1,70 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MvEeprom + FILE_GUID = 59fc3843-d8d4-40aa-ae07-38967138509c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MvEepromInitialise + +[Sources.common] + MvEeprom.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec + +[LibraryClasses] + IoLib + PcdLib + BaseLib + BaseMemoryLib + DebugLib + UefiLib + UefiDriverEntryPoint + UefiBootServicesTableLib + +[Protocols] + gEfiI2cIoProtocolGuid + gEfiDriverBindingProtocolGuid + gMarvellEepromProtocolGuid + +[Pcd] + gMarvellTokenSpaceGuid.PcdEepromI2cAddresses + gMarvellTokenSpaceGuid.PcdEepromI2cBuses + +[Depex] + TRUE diff --git a/Platforms/Marvell/Include/Protocol/Eeprom.h b/Platforms/Marvell/Include/Protocol/Eeprom.h new file mode 100644 index 0000000..2708f7d --- /dev/null +++ b/Platforms/Marvell/Include/Protocol/Eeprom.h @@ -0,0 +1,60 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MARVELL_EEPROM_H__ +#define __MARVELL_EEPROM_H__ + +#define MARVELL_EEPROM_PROTOCOL_GUID { 0xcd728a1f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} + +typedef struct _MARVELL_EEPROM_PROTOCOL MARVELL_EEPROM_PROTOCOL; + +#define EEPROM_READ 0x1 +#define EEPROM_WRITE 0x0 +typedef +EFI_STATUS +(EFIAPI *EFI_EEPROM_TRANSFER) ( + IN CONST MARVELL_EEPROM_PROTOCOL *This, + IN UINT16 Address, + IN UINT32 Length, + IN UINT8 *Buffer, + IN UINT8 Operation + ); + +struct _MARVELL_EEPROM_PROTOCOL { + EFI_EEPROM_TRANSFER Transfer; + UINT32 Identifier; +}; + +extern EFI_GUID gMarvellEepromProtocolGuid; +#endif diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 6738116..bc4ac7a 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -107,8 +107,13 @@ #I2C gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0 }|VOID*|0x3000046 gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0 }|VOID*|0x3000184 + gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0 }|VOID*|0x3000050 + gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0 }|VOID*|0x3000185 gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|{ 0 }|VOID*|0x3000047 gMarvellTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048 gMarvellTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049 gMarvellTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183

+[Protocols] + gMarvellEepromProtocolGuid = { 0xcd728a1f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} +

From: Jan Dąbroś jsd@semihalf.com

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bartosz Szczepanek bsz@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/Marvell/Armada/Armada.dsc.inc | 1 + Platforms/Marvell/Armada/Armada70x0.dsc | 2 ++ Platforms/Marvell/Armada/Armada70x0.fdf | 1 + 3 files changed, 4 insertions(+)

diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc index 0a63af5..af95089 100644 --- a/Platforms/Marvell/Armada/Armada.dsc.inc +++ b/Platforms/Marvell/Armada/Armada.dsc.inc @@ -384,6 +384,7 @@ # Platform drivers OpenPlatformPkg/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf + OpenPlatformPkg/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf

MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 378ad20..76b06e0 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -79,6 +79,8 @@ gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60 } gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" + gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } + gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 gMarvellTokenSpaceGuid.PcdI2cBusCount|2 diff --git a/Platforms/Marvell/Armada/Armada70x0.fdf b/Platforms/Marvell/Armada/Armada70x0.fdf index 110af72..8f4f425 100644 --- a/Platforms/Marvell/Armada/Armada70x0.fdf +++ b/Platforms/Marvell/Armada/Armada70x0.fdf @@ -104,6 +104,7 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf INF OpenPlatformPkg/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf + INF OpenPlatformPkg/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf

# Multiple Console IO support INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf

From: Jan Dąbroś jsd@semihalf.com

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bartosz Szczepanek bsz@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/Marvell/Armada/Armada.dsc.inc | 1 + 1 file changed, 1 insertion(+)

diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc index af95089..ba81baf 100644 --- a/Platforms/Marvell/Armada/Armada.dsc.inc +++ b/Platforms/Marvell/Armada/Armada.dsc.inc @@ -432,6 +432,7 @@ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf + NULL|OpenPlatformPkg/Applications/EepromCmd/EepromCmd.inf HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf

From: Jan Dąbroś jsd@semihalf.com

Spi master driver implements MARVELL_SPI_MASTER_PROTOCOL. It configures and manages SPI controller.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Documentation/Marvell/Drivers/SpiDriver.txt | 116 +++++++++ Documentation/Marvell/PortingGuide/Spi.txt | 15 ++ Drivers/Spi/MvSpiDxe.c | 379 ++++++++++++++++++++++++++++ Drivers/Spi/MvSpiDxe.h | 145 +++++++++++ Drivers/Spi/MvSpiDxe.inf | 66 +++++ Platforms/Marvell/Marvell.dec | 5 + 6 files changed, 726 insertions(+) create mode 100644 Documentation/Marvell/Drivers/SpiDriver.txt create mode 100644 Documentation/Marvell/PortingGuide/Spi.txt create mode 100755 Drivers/Spi/MvSpiDxe.c create mode 100644 Drivers/Spi/MvSpiDxe.h create mode 100644 Drivers/Spi/MvSpiDxe.inf

diff --git a/Documentation/Marvell/Drivers/SpiDriver.txt b/Documentation/Marvell/Drivers/SpiDriver.txt new file mode 100644 index 0000000..42b5e3c --- /dev/null +++ b/Documentation/Marvell/Drivers/SpiDriver.txt @@ -0,0 +1,116 @@ +1. Introduction +--------------- +**SpiDxe** driver implements MARVELL_SPI_MASTER_PROTOCOL in order to manage SPI +controller on Marvell A8k boards. It exposes below functionalities: + - create and setup SPI slaves + - raw transfer over SPI bus + +2. SpiDxe driver design +----------------------- + + 2.1 MARVELL_SPI_MASTER_PROTOCOL + ----------------------- + First member of SPI_MASTER protocol is Init function, implemented for SPI + master controller initialization. + + ->Init() + + // + //Initializes the host controller to execute SPI commands. + // + + param[IN] This Pointer to the MARVELL_SPI_MASTER_PROTOCOL instance + + return EFI_SUCCESS Opcode initialization on the SPI host + controller completed. + return EFI_ACCESS_DENIED The SPI configuration interface is + locked. + return EFI_OUT_OF_RESOURCES Not enough resource available to + initialize the device. + return EFI_DEVICE_ERROR Device error, operation failed. + + ******** + + SPI devices (slaves) do not support any kind of automatic discovery or + enumaration, so every device needs manual configuration, which may be done + with SetupDevice function. + + ->SetupDevice() + + // + //Allocate and zero all fields in the SPI_DEVICE struct. Set the chip + //select, max frequency and transfer mode supported by slave device. + // + + param[IN] Cs Chip select ID of the slave chip. + param[IN] MaxFreq Maximum SCK rate in Hz. + param[IN] Mode Clock polarity and clock phase. + + return *SPI_DEVICE Pointer to new allocated struct SPI_DEVICE. + return NULL NULL pointer if any eroor occured. + + ******** + + Developers have to destroy all created SPI device structs (with FreeDevice + function) in order to prevent from memory leak. + + ->FreeDevice() + + // + //Free any memory associated with a SPI device. + // + + param[in] SpiDev Pointer to the SPI_DEVICE struct. + + return EFI_SUCCESS Memory fried succesfully. + return EFI_DEVICE_ERROR Device error, operation failed. + + ******** + + Transfer function allows write/read raw bytes over SPI bus. + + ->Transfer() + + // + //Perform transfer over SPI bus + // + param[in] This Pointer to the MARVELL_SPI_MASTER_PROTOCOL + instance. + param[in] Slave Pointer to the SPI_DEVICE struct. + param[in] DataByteCount Number of bytes in the data portion of + the SPI cycle. + param[in] DataOut Pointer to caller-allocated buffer + containing the data to send. + param[out] DataIn Pointer to caller-allocated buffer + where received data will be placed. + param[in] Flag Flags which indicate state of CS line + during/after transfer (see file + Drivers/Spi/Devices/A8kSpiFlash.h) + + return EFI_SUCCESS Memory fried succesfully. + return EFI_DEVICE_ERROR Device error, operation failed. + + ********* + + When working with SPI devices it is often necessary to perform "command and + address" transactions. It may be done via ReadWrite function. + + ->ReadWrite() + + // + //Perform two steps transactions. First write Command, then read/write + //buffer + // + + param[in] This Pointer to the MARVELL_SPI_MASTER_PROTOCOL + instance. + param[in] Slave Pointer to the SPI_DEVICE struct. + param[in] Cmd Pointer to caller-allocated buffer + containing the command to send. + param[in] CmdSize Size of command (in bytes). + param[in] DataOut Pointer to caller-allocated buffer + containing the data to send. + param[out] DataIn Pointer to caller-allocated buffer + where received data will be placed. + param[in] DataSize Number of bytes in the data portion of + the SPI cycle. diff --git a/Documentation/Marvell/PortingGuide/Spi.txt b/Documentation/Marvell/PortingGuide/Spi.txt new file mode 100644 index 0000000..f1f36ad --- /dev/null +++ b/Documentation/Marvell/PortingGuide/Spi.txt @@ -0,0 +1,15 @@ +Spi driver configuration +------------------------ +Following PCDs are available for configuration of spi driver: + + gMarvellTokenSpaceGuid.PcdSpiClockFrequency + +Frequency (in Hz) of SPI clock + + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency + +Max SCLK line frequency (in Hz) (max transfer frequency) + + gMarvellTokenSpaceGuid.PcdSpiDefaultMode + +default SCLK mode (see SPI_MODE enum in file OpenPlatformPkg/Drivers/Spi/MvSpi.h) diff --git a/Drivers/Spi/MvSpiDxe.c b/Drivers/Spi/MvSpiDxe.c new file mode 100755 index 0000000..aab20fc --- /dev/null +++ b/Drivers/Spi/MvSpiDxe.c @@ -0,0 +1,379 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "MvSpiDxe.h" + +SPI_MASTER *mSpiMasterInstance; + +STATIC +EFI_STATUS +SpiSetBaudRate ( + IN UINT32 CpuClock, + IN UINT32 MaxFreq + ) +{ + UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff; + UINTN SpiRegBase = PcdGet32 (PcdSpiRegBase); + + MinBaudDiff = 0xFFFFFFFF; + BestSppr = 0; + + //Spr is in range 1-15 and Sppr in range 0-8 + for (Spr = 1; Spr <= 15; Spr++) { + for (Sppr = 0; Sppr <= 7; Sppr++) { + ClockDivider = Spr * (1 << Sppr); + + if ((CpuClock / ClockDivider) > MaxFreq) { + continue; + } + + if ((CpuClock / ClockDivider) == MaxFreq) { + BestSpr = Spr; + BestSppr = Sppr; + Match = 1; + break; + } + + if ((MaxFreq - (CpuClock / ClockDivider)) < MinBaudDiff) { + MinBaudDiff = (MaxFreq - (CpuClock / ClockDivider)); + BestSpr = Spr; + BestSppr = Sppr; + } + } + + if (Match == 1) { + break; + } + } + + if (BestSpr == 0) { + return (EFI_INVALID_PARAMETER); + } + + Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG); + Reg &= ~(SPI_SPR_MASK | SPI_SPPR_0_MASK | SPI_SPPR_HI_MASK); + Reg |= (BestSpr << SPI_SPR_OFFSET) | + ((BestSppr & 0x1) << SPI_SPPR_0_OFFSET) | + ((BestSppr >> 1) << SPI_SPPR_HI_OFFSET); + MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); + + return EFI_SUCCESS; +} + +STATIC +VOID +SpiSetCs ( + UINT8 CsId + ) +{ + UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase); + + Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG); + Reg &= ~SPI_CS_NUM_MASK; + Reg |= (CsId << SPI_CS_NUM_OFFSET); + MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg); +} + +STATIC +VOID +SpiActivateCs ( + UINT8 IN CsId + ) +{ + UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase); + + SpiSetCs(CsId); + Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG); + Reg |= SPI_CS_EN_MASK; + MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg); +} + +STATIC +VOID +SpiDeactivateCs ( + VOID + ) +{ + UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase); + + Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG); + Reg &= ~SPI_CS_EN_MASK; + MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg); +} + +STATIC +VOID +SpiSetupTransfer ( + IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave + ) +{ + SPI_MASTER *SpiMaster; + UINT32 Reg, SpiRegBase, CoreClock, SpiMaxFreq; + + SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); + + // Initialize values from PCDs + SpiRegBase = PcdGet32 (PcdSpiRegBase); + CoreClock = PcdGet32 (PcdSpiClockFrequency); + SpiMaxFreq = PcdGet32 (PcdSpiMaxFrequency); + + EfiAcquireLock (&SpiMaster->Lock); + + Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG); + Reg |= SPI_BYTE_LENGTH; + MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); + + SpiSetCs(Slave->Cs); + + SpiSetBaudRate (CoreClock, SpiMaxFreq); + + Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG); + Reg &= ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_MASK); + + switch (Slave->Mode) { + case SPI_MODE0: + break; + case SPI_MODE1: + Reg |= SPI_CPHA_MASK; + break; + case SPI_MODE2: + Reg |= SPI_CPOL_MASK; + break; + case SPI_MODE3: + Reg |= SPI_CPOL_MASK; + Reg |= SPI_CPHA_MASK; + break; + } + + MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); + + EfiReleaseLock (&SpiMaster->Lock); +} + +EFI_STATUS +EFIAPI +MvSpiTransfer ( + IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave, + IN UINTN DataByteCount, + IN VOID *DataOut, + IN VOID *DataIn, + IN UINTN Flag + ) +{ + SPI_MASTER *SpiMaster; + UINT64 Length; + UINT32 Iterator, Reg, SpiRegBase; + UINT8 *DataOutPtr = (UINT8 *)DataOut; + UINT8 *DataInPtr = (UINT8 *)DataIn; + UINT8 DataToSend = 0; + + SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); + + SpiRegBase = PcdGet32 (PcdSpiRegBase); + + Length = 8 * DataByteCount; + + EfiAcquireLock (&SpiMaster->Lock); + + if (Flag & SPI_TRANSFER_BEGIN) { + SpiActivateCs (Slave->Cs); + } + + // Set 8-bit mode + Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG); + Reg &= ~SPI_BYTE_LENGTH; + MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); + + while (Length > 0) { + if (DataOut != NULL) { + DataToSend = *DataOutPtr & 0xFF; + } + // Transmit Data + MmioWrite32 (SpiRegBase + SPI_INT_CAUSE_REG, 0x0); + MmioWrite32 (SpiRegBase + SPI_DATA_OUT_REG, DataToSend); + // Wait for memory ready + for (Iterator = 0; Iterator < SPI_TIMEOUT; Iterator++) { + if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) { + *DataInPtr = MmioRead32 (SpiRegBase + SPI_DATA_IN_REG); + + if (DataInPtr != NULL) { + DataInPtr++; + } + if (DataOutPtr != NULL) { + DataOutPtr++; + } + Length -= 8; + break; + } + } + + if (Iterator >= SPI_TIMEOUT) { + DEBUG ((DEBUG_ERROR, "Timeout\n")); + } + } + + if (Flag & SPI_TRANSFER_END) { + SpiDeactivateCs (); + } + + EfiReleaseLock (&SpiMaster->Lock); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvSpiReadWrite ( + IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave, + IN UINT8 *Cmd, + IN UINTN CmdSize, + IN UINT8 *DataOut, + OUT UINT8 *DataIn, + IN UINTN DataSize + ) +{ + EFI_STATUS Status; + + Status = MvSpiTransfer (This, Slave, CmdSize, Cmd, NULL, SPI_TRANSFER_BEGIN); + if (EFI_ERROR (Status)) { + Print (L"Spi Transfer Error\n"); + return EFI_DEVICE_ERROR; + } + + Status = MvSpiTransfer (This, Slave, DataSize, DataOut, DataIn, SPI_TRANSFER_END); + if (EFI_ERROR (Status)) { + Print (L"Spi Transfer Error\n"); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvSpiInit ( + IN MARVELL_SPI_MASTER_PROTOCOL * This + ) +{ + + return EFI_SUCCESS; +} + +SPI_DEVICE * +EFIAPI +MvSpiSetupSlave ( + IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN UINTN Cs, + IN SPI_MODE Mode + ) +{ + SPI_DEVICE *Slave; + + Slave = AllocateZeroPool (sizeof(SPI_DEVICE)); + if (Slave == NULL) { + DEBUG((DEBUG_ERROR, "Cannot allocate memory\n")); + return NULL; + } + + Slave->Cs = Cs; + Slave->Mode = Mode; + + SpiSetupTransfer (This, Slave); + + return Slave; +} + +EFI_STATUS +EFIAPI +MvSpiFreeSlave ( + IN SPI_DEVICE *Slave + ) +{ + FreePool (Slave); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +SpiMasterInitProtocol ( + IN MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol + ) +{ + + SpiMasterProtocol->Init = MvSpiInit; + SpiMasterProtocol->SetupDevice = MvSpiSetupSlave; + SpiMasterProtocol->FreeDevice = MvSpiFreeSlave; + SpiMasterProtocol->Transfer = MvSpiTransfer; + SpiMasterProtocol->ReadWrite = MvSpiReadWrite; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SpiMasterEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mSpiMasterInstance = AllocateZeroPool (sizeof (SPI_MASTER)); + + if (mSpiMasterInstance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + EfiInitializeLock (&mSpiMasterInstance->Lock, TPL_NOTIFY); + + SpiMasterInitProtocol (&mSpiMasterInstance->SpiMasterProtocol); + + mSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &(mSpiMasterInstance->Handle), + &gMarvellSpiMasterProtocolGuid, + &(mSpiMasterInstance->SpiMasterProtocol), + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (mSpiMasterInstance); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} diff --git a/Drivers/Spi/MvSpiDxe.h b/Drivers/Spi/MvSpiDxe.h new file mode 100644 index 0000000..1401f62 --- /dev/null +++ b/Drivers/Spi/MvSpiDxe.h @@ -0,0 +1,145 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __SPI_MASTER_H__ +#define __SPI_MASTER_H__ + +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Uefi/UefiBaseType.h> +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/Spi.h> + +#define SPI_MASTER_SIGNATURE SIGNATURE_32 ('M', 'S', 'P', 'I') +#define SPI_MASTER_FROM_SPI_MASTER_PROTOCOL(a) CR (a, SPI_MASTER, SpiMasterProtocol, SPI_MASTER_SIGNATURE) + +// Marvell Flash Device Controller Registers +#define SPI_CTRL_REG (0x00) +#define SPI_CONF_REG (0x04) +#define SPI_DATA_OUT_REG (0x08) +#define SPI_DATA_IN_REG (0x0c) +#define SPI_INT_CAUSE_REG (0x10) + +// Serial Memory Interface Control Register Masks +#define SPI_CS_NUM_OFFSET 2 +#define SPI_CS_NUM_MASK (0x7 << SPI_CS_NUM_OFFSET) +#define SPI_MEM_READY_MASK (0x1 << 1) +#define SPI_CS_EN_MASK (0x1 << 0) + +// Serial Memory Interface Configuration Register Masks +#define SPI_BYTE_LENGTH_OFFSET 5 +#define SPI_BYTE_LENGTH (0x1 << SPI_BYTE_LENGTH_OFFSET) +#define SPI_CPOL_OFFSET 11 +#define SPI_CPOL_MASK (0x1 << SPI_CPOL_OFFSET) +#define SPI_CPHA_OFFSET 12 +#define SPI_CPHA_MASK (0x1 << SPI_CPHA_OFFSET) +#define SPI_TXLSBF_OFFSET 13 +#define SPI_TXLSBF_MASK (0x1 << SPI_TXLSBF_OFFSET) +#define SPI_RXLSBF_OFFSET 14 +#define SPI_RXLSBF_MASK (0x1 << SPI_RXLSBF_OFFSET) + +#define SPI_SPR_OFFSET 0 +#define SPI_SPR_MASK (0xf << SPI_SPR_OFFSET) +#define SPI_SPPR_0_OFFSET 4 +#define SPI_SPPR_0_MASK (0x1 << SPI_SPPR_0_OFFSET) +#define SPI_SPPR_HI_OFFSET 6 +#define SPI_SPPR_HI_MASK (0x3 << SPI_SPPR_HI_OFFSET) + +#define SPI_TRANSFER_BEGIN 0x01 // Assert CS before transfer +#define SPI_TRANSFER_END 0x02 // Deassert CS after transfers + +#define SPI_TIMEOUT 100000 + +typedef struct { + MARVELL_SPI_MASTER_PROTOCOL SpiMasterProtocol; + UINTN Signature; + EFI_HANDLE Handle; + EFI_LOCK Lock; +} SPI_MASTER; + +EFI_STATUS +EFIAPI +MvSpiTransfer ( + IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave, + IN UINTN DataByteCount, + IN VOID *DataOut, + IN VOID *DataIn, + IN UINTN Flag + ); + +EFI_STATUS +EFIAPI +MvSpiReadWrite ( + IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave, + IN UINT8 *Cmd, + IN UINTN CmdSize, + IN UINT8 *DataOut, + OUT UINT8 *DataIn, + IN UINTN DataSize + ); + +EFI_STATUS +EFIAPI +MvSpiInit ( + IN MARVELL_SPI_MASTER_PROTOCOL * This + ); + +SPI_DEVICE * +EFIAPI +MvSpiSetupSlave ( + IN MARVELL_SPI_MASTER_PROTOCOL * This, + IN UINTN Cs, + IN SPI_MODE Mode + ); + +EFI_STATUS +EFIAPI +MvSpiFreeSlave ( + IN SPI_DEVICE *Slave + ); + +EFI_STATUS +EFIAPI +SpiMasterEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif // __SPI_MASTER_H__ diff --git a/Drivers/Spi/MvSpiDxe.inf b/Drivers/Spi/MvSpiDxe.inf new file mode 100644 index 0000000..1dd3029 --- /dev/null +++ b/Drivers/Spi/MvSpiDxe.inf @@ -0,0 +1,66 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SpiMasterDxe + FILE_GUID = c19dbc8a-f4f9-43b0-aee5-802e3ed03d15 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SpiMasterEntryPoint + +[Sources] + MvSpiDxe.c + MvSpiDxe.h + +[Packages] + MdePkg/MdePkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + TimerLib + UefiLib + DebugLib + MemoryAllocationLib + IoLib + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdSpiRegBase + gMarvellTokenSpaceGuid.PcdSpiClockFrequency + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency + +[Protocols] + gMarvellSpiMasterProtocolGuid + +[Depex] + TRUE diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index dc670e7..e76678e 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -116,6 +116,11 @@ gMarvellTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049 gMarvellTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183

+#SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053 + [Protocols] gMarvellEepromProtocolGuid = { 0xcd728a1f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} gMarvellSpiMasterProtocolGuid = { 0x23de66a3, 0xf666, 0x4b3e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }}

From: Jan Dąbroś jsd@semihalf.com

Add MARVELL_SPI_FLASH_PROTOCOL and register containg folder in Marvell/Marvell.dec in order to make it public. This protocol contains functions used to manage SPI flash.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Platforms/Marvell/Include/Protocol/SpiFlash.h | 113 ++++++++++++++++++++++++++ Platforms/Marvell/Marvell.dec | 1 + 2 files changed, 114 insertions(+) create mode 100644 Platforms/Marvell/Include/Protocol/SpiFlash.h

diff --git a/Platforms/Marvell/Include/Protocol/SpiFlash.h b/Platforms/Marvell/Include/Protocol/SpiFlash.h new file mode 100644 index 0000000..743bb87 --- /dev/null +++ b/Platforms/Marvell/Include/Protocol/SpiFlash.h @@ -0,0 +1,113 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __MV_SPI_FLASH__ +#define __MV_SPI_FLASH__ + +#include <Protocol/Spi.h> + +#define CMD_READ_ID 0x9f +#define READ_STATUS_REG_CMD 0x0b +#define CMD_WRITE_ENABLE 0x06 +#define CMD_FLAG_STATUS 0x70 +#define CMD_WRITE_STATUS_REG 0x01 +#define CMD_READ_ARRAY_FAST 0x0b +#define CMD_PAGE_PROGRAM 0x02 +#define CMD_BANK_WRITE 0xc5 +#define CMD_ERASE_64K 0xd8 +#define CMD_4B_ADDR_ENABLE 0xb7 + +extern EFI_GUID gMarvellSpiFlashProtocolGuid; + +typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *MV_SPI_FLASH_INIT) ( + IN MARVELL_SPI_FLASH_PROTOCOL *This, + IN SPI_DEVICE *SpiDev + ); + +typedef +EFI_STATUS +(EFIAPI *MV_SPI_FLASH_READ_ID) ( + IN SPI_DEVICE *SpiDev, + IN UINT32 DataByteCount, + IN OUT UINT8 *Buffer + ); + +typedef +EFI_STATUS +(EFIAPI *MV_SPI_FLASH_READ) ( + IN SPI_DEVICE *SpiDev, + IN UINT32 Address, + IN UINTN DataByteCount, + IN VOID *Buffer + ); + +typedef +EFI_STATUS +(EFIAPI *MV_SPI_FLASH_WRITE) ( + IN SPI_DEVICE *SpiDev, + IN UINT32 Address, + IN UINTN DataByteCount, + IN VOID *Buffer + ); + +typedef +EFI_STATUS +(EFIAPI *MV_SPI_FLASH_ERASE) ( + IN SPI_DEVICE *SpiDev, + IN UINTN Address, + IN UINTN DataByteCount + ); + +typedef +EFI_STATUS +(EFIAPI *MV_SPI_FLASH_UPDATE) ( + IN SPI_DEVICE *SpiDev, + IN UINT32 Address, + IN UINTN DataByteCount, + IN UINT8 *Buffer + ); + +struct _MARVELL_SPI_FLASH_PROTOCOL { + MV_SPI_FLASH_INIT Init; + MV_SPI_FLASH_READ_ID ReadId; + MV_SPI_FLASH_READ Read; + MV_SPI_FLASH_WRITE Write; + MV_SPI_FLASH_ERASE Erase; + MV_SPI_FLASH_UPDATE Update; +}; + +#endif // __MV_SPI_FLASH__ diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index e76678e..7dd3e07 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -124,4 +124,5 @@ [Protocols] gMarvellEepromProtocolGuid = { 0xcd728a1f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} gMarvellSpiMasterProtocolGuid = { 0x23de66a3, 0xf666, 0x4b3e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }} + gMarvellSpiFlashProtocolGuid = { 0x9accb423, 0x5bd2, 0x4fca, { 0x9b, 0x4c, 0x2e, 0x65, 0xfc, 0x25, 0xdf, 0x21 }}

From: Jan Dąbroś jsd@semihalf.com

This patch add driver for managing Spi flash It consumes MARVELL_SPI_FLASH_PROTOCOL and enables configuration by PCD entries.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Documentation/Marvell/PortingGuide/SpiFlash.txt | 23 + Drivers/Spi/Devices/MvSpiFlash.c | 531 ++++++++++++++++++++++++ Drivers/Spi/Devices/MvSpiFlash.h | 132 ++++++ Drivers/Spi/Devices/MvSpiFlash.inf | 67 +++ Platforms/Marvell/Marvell.dec | 6 + 5 files changed, 759 insertions(+) create mode 100644 Documentation/Marvell/PortingGuide/SpiFlash.txt create mode 100755 Drivers/Spi/Devices/MvSpiFlash.c create mode 100755 Drivers/Spi/Devices/MvSpiFlash.h create mode 100644 Drivers/Spi/Devices/MvSpiFlash.inf

diff --git a/Documentation/Marvell/PortingGuide/SpiFlash.txt b/Documentation/Marvell/PortingGuide/SpiFlash.txt new file mode 100644 index 0000000..226db40 --- /dev/null +++ b/Documentation/Marvell/PortingGuide/SpiFlash.txt @@ -0,0 +1,23 @@ +SpiFlash driver configuration +----------------------------- +Folowing PCDs for spi flash driver configuration must be set properly: + + gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles + +Size of SPI flash address in bytes (3 or 4) + + gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize + +Size of minimal erase block in bytes + + gMarvellTokenSpaceGuid.PcdSpiFlashPageSize + +Size of SPI flash page + + gMarvellTokenSpaceGuid.PcdSpiFlashId + +Id of SPI flash + + gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + +Spi flash polling flag diff --git a/Drivers/Spi/Devices/MvSpiFlash.c b/Drivers/Spi/Devices/MvSpiFlash.c new file mode 100755 index 0000000..9a04493 --- /dev/null +++ b/Drivers/Spi/Devices/MvSpiFlash.c @@ -0,0 +1,531 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "MvSpiFlash.h" + +MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol; +SPI_FLASH_INSTANCE *mSpiFlashInstance; + +STATIC +VOID +SpiFlashFormatAddress ( + IN UINT32 Address, + IN UINT8 AddrSize, + IN OUT UINT8 *Cmd + ) +{ + if (AddrSize == 4) { + Cmd[1] = Address >> 24; + Cmd[2] = Address >> 16; + Cmd[3] = Address >> 8; + Cmd[4] = Address; + } else { + Cmd[1] = Address >> 16; + Cmd[2] = Address >> 8; + Cmd[3] = Address; + } +} + +STATIC +EFI_STATUS +MvSpiFlashReadCmd ( + IN SPI_DEVICE *Slave, + IN UINT8 *Cmd, + IN UINTN CmdSize, + OUT UINT8 *DataIn, + IN UINTN DataSize + ) +{ + EFI_STATUS Status; + + // Send command and gather response + Status = SpiMasterProtocol->ReadWrite (SpiMasterProtocol, Slave, Cmd, + CmdSize, NULL, DataIn, DataSize); + + return Status; +} + +STATIC +EFI_STATUS +MvSpiFlashWriteEnableCmd ( + IN SPI_DEVICE *Slave + ) +{ + EFI_STATUS Status; + UINT8 CmdEn = CMD_WRITE_ENABLE; + + // Send write_enable command + Status = SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, + &CmdEn, NULL, SPI_TRANSFER_BEGIN | SPI_TRANSFER_END); + + return Status; +} + +STATIC +EFI_STATUS +MvSpiFlashWriteCommon ( + IN SPI_DEVICE *Slave, + IN UINT8 *Cmd, + IN UINT32 Length, + IN UINT8* Buffer, + IN UINT32 BufferLength + ) +{ + UINT8 CmdStatus = CMD_READ_STATUS; + UINT8 State; + UINT32 Counter = 0xFFFFF; + UINT8 poll_bit = STATUS_REG_POLL_WIP; + UINT8 check_status = 0x0; + + CmdStatus = (UINT8)PcdGet32 (PcdSpiFlashPollCmd); + if (CmdStatus == CMD_FLAG_STATUS) { + poll_bit = STATUS_REG_POLL_PEC; + check_status = poll_bit; + } + + // Send command + MvSpiFlashWriteEnableCmd (Slave); + + // Write data + SpiMasterProtocol->ReadWrite (SpiMasterProtocol, Slave, Cmd, Length, + Buffer, NULL, BufferLength); + + // Poll status register + SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, &CmdStatus, + NULL, SPI_TRANSFER_BEGIN); + do { + SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, NULL, &State, + 0); + Counter--; + if ((State & poll_bit) == check_status) + break; + } while (Counter > 0); + if (Counter == 0) { + DEBUG((DEBUG_ERROR, "SpiFlash: Timeout while writing to spi flash\n")); + return EFI_DEVICE_ERROR; + } + + // Deactivate CS + SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 0, NULL, NULL, SPI_TRANSFER_END); + + return EFI_SUCCESS; +} + +STATIC +VOID +SpiFlashCmdBankaddrWrite ( + IN SPI_DEVICE *Slave, + IN UINT8 BankSel + ) +{ + UINT8 Cmd = CMD_BANK_WRITE; + + MvSpiFlashWriteCommon (Slave, &Cmd, 1, &BankSel, 1); +} + +STATIC +UINT8 +SpiFlashBank ( + IN SPI_DEVICE *Slave, + IN UINT32 Offset + ) +{ + UINT8 BankSel; + + BankSel = Offset / SPI_FLASH_16MB_BOUN; + + SpiFlashCmdBankaddrWrite (Slave, BankSel); + + return BankSel; +} + +EFI_STATUS +MvSpiFlashErase ( + IN SPI_DEVICE *Slave, + IN UINTN Offset, + IN UINTN Length + ) +{ + EFI_STATUS Status; + UINT32 AddrSize, EraseAddr; + UINTN EraseSize; + UINT8 Cmd[5]; + + AddrSize = PcdGet32 (PcdSpiFlashAddressCycles); + EraseSize = PcdGet64 (PcdSpiFlashEraseSize); + + // Check input parameters + if (Offset % EraseSize || Length % EraseSize) { + DEBUG((DEBUG_ERROR, "SpiFlash: Either erase offset or length " + "is not multiple of erase size\n")); + return EFI_DEVICE_ERROR; + } + + Cmd[0] = CMD_ERASE_64K; + while (Length) { + EraseAddr = Offset; + + SpiFlashBank (Slave, EraseAddr); + + SpiFlashFormatAddress (EraseAddr, AddrSize, Cmd); + + // Programm proper erase address + Status = MvSpiFlashWriteCommon (Slave, Cmd, AddrSize + 1, NULL, 0); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while programming target address\n")); + return Status; + } + + Offset += EraseSize; + Length -= EraseSize; + } + return EFI_SUCCESS; +} + +EFI_STATUS +MvSpiFlashRead ( + IN SPI_DEVICE *Slave, + IN UINT32 Offset, + IN UINTN Length, + IN VOID *Buf + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT8 Cmd[6]; + UINT32 AddrSize, ReadAddr, ReadLength, RemainLength; + UINTN BankSel = 0; + + AddrSize = PcdGet32 (PcdSpiFlashAddressCycles); + + Cmd[0] = CMD_READ_ARRAY_FAST; + + // Sign end of address with 0 byte + Cmd[5] = 0; + + while (Length) { + ReadAddr = Offset; + + BankSel = SpiFlashBank (Slave, ReadAddr); + + RemainLength = (SPI_FLASH_16MB_BOUN * (BankSel + 1)) - Offset; + if (Length < RemainLength) { + ReadLength = Length; + } else { + ReadLength = RemainLength; + } + SpiFlashFormatAddress (ReadAddr, AddrSize, Cmd); + // Program proper read address and read data + Status = MvSpiFlashReadCmd (Slave, Cmd, AddrSize + 2, Buf, Length); + + Offset += ReadLength; + Length -= ReadLength; + Buf += ReadLength; + } + + return Status; +} + +EFI_STATUS +MvSpiFlashWrite ( + IN SPI_DEVICE *Slave, + IN UINT32 Offset, + IN UINTN Length, + IN VOID *Buf + ) +{ + EFI_STATUS Status; + UINTN ByteAddr, ChunkLength, ActualIndex, PageSize; + UINT32 WriteAddr; + UINT8 Cmd[5], AddrSize; + + AddrSize = PcdGet32 (PcdSpiFlashAddressCycles); + PageSize = PcdGet32 (PcdSpiFlashPageSize); + + Cmd[0] = CMD_PAGE_PROGRAM; + + for (ActualIndex = 0; ActualIndex < Length; ActualIndex += ChunkLength) { + WriteAddr = Offset; + + SpiFlashBank (Slave, WriteAddr); + + ByteAddr = Offset % PageSize; + + ChunkLength = MIN(Length - ActualIndex, (UINT64) (PageSize - ByteAddr)); + + SpiFlashFormatAddress (WriteAddr, AddrSize, Cmd); + + // Program proper write address and write data + Status = MvSpiFlashWriteCommon (Slave, Cmd, AddrSize + 1, Buf + ActualIndex, + ChunkLength); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while programming write address\n")); + return Status; + } + + Offset += ChunkLength; + } + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvSpiFlashUpdateBlock ( + IN SPI_DEVICE *Slave, + IN UINT32 Offset, + IN UINTN ToUpdate, + IN UINT8 *Buf, + IN UINT8 *TmpBuf, + IN UINTN EraseSize + ) +{ + EFI_STATUS Status; + + // Read backup + Status = MvSpiFlashRead (Slave, Offset, EraseSize, TmpBuf); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while reading old data\n")); + return Status; + } + + // Erase entire sector + Status = MvSpiFlashErase (Slave, Offset, EraseSize); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while erasing block\n")); + return Status; + } + + // Write new data + MvSpiFlashWrite (Slave, Offset, ToUpdate, Buf); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while writing new data\n")); + return Status; + } + + // Write backup + if (ToUpdate != EraseSize) { + Status = MvSpiFlashWrite (Slave, Offset + ToUpdate, EraseSize - ToUpdate, + &TmpBuf[ToUpdate]); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while writing backup\n")); + return Status; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +MvSpiFlashUpdate ( + IN SPI_DEVICE *Slave, + IN UINT32 Offset, + IN UINTN ByteCount, + IN UINT8 *Buf + ) +{ + EFI_STATUS Status; + UINT64 EraseSize, ToUpdate, Scale = 1; + UINT8 *TmpBuf, *End; + + EraseSize = PcdGet64 (PcdSpiFlashEraseSize); + + End = Buf + ByteCount; + + TmpBuf = (UINT8 *)AllocateZeroPool (EraseSize); + if (TmpBuf == NULL) { + DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); + return EFI_OUT_OF_RESOURCES; + } + + if (End - Buf >= 200) + Scale = (End - Buf) / 100; + + for (; Buf < End; Buf += ToUpdate, Offset += ToUpdate) { + ToUpdate = MIN((UINT64)(End - Buf), EraseSize); + Print (L" \rUpdating, %d%%", 100 - (End - Buf) / Scale); + Status = MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf, EraseSize); + + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while updating\n")); + return Status; + } + } + + Print(L"\n"); + FreePool (TmpBuf); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvSpiFlashReadId ( + IN SPI_DEVICE *SpiDev, + IN UINT32 DataByteCount, + IN OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINT8 *DataOut; + + DataOut = (UINT8 *) AllocateZeroPool (DataByteCount); + if (DataOut == NULL) { + DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); + return EFI_OUT_OF_RESOURCES; + } + Status = SpiMasterProtocol->Transfer (SpiMasterProtocol, SpiDev, + DataByteCount, Buffer, DataOut, SPI_TRANSFER_BEGIN | SPI_TRANSFER_END); + if (EFI_ERROR(Status)) { + FreePool (DataOut); + DEBUG((DEBUG_ERROR, "SpiFlash: Spi transfer error\n")); + return Status; + } + + // Bytes 1,2 and 3 contain SPI flash ID + Buffer[0] = DataOut[1]; + Buffer[1] = DataOut[2]; + Buffer[2] = DataOut[3]; + + FreePool (DataOut); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvSpiFlashInit ( + IN MARVELL_SPI_FLASH_PROTOCOL *This, + IN SPI_DEVICE *Slave + ) +{ + EFI_STATUS Status; + UINT8 Cmd, StatusRegister; + UINT32 AddrSize; + + AddrSize = PcdGet32 (PcdSpiFlashAddressCycles); + + if (AddrSize == 4) { + // Set 4 byte address mode + Status = MvSpiFlashWriteEnableCmd (Slave); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while setting write_enable\n")); + return Status; + } + + Cmd = CMD_4B_ADDR_ENABLE; + Status = SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, &Cmd, NULL, + SPI_TRANSFER_BEGIN | SPI_TRANSFER_END); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while setting 4B address\n")); + return Status; + } + } + + // Write flash status register + Status = MvSpiFlashWriteEnableCmd (Slave); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while setting write_enable\n")); + return Status; + } + + Cmd = CMD_WRITE_STATUS_REG; + StatusRegister = 0x0; + Status = SpiMasterProtocol->ReadWrite (SpiMasterProtocol, Slave, &Cmd, 1, + &StatusRegister, NULL, 1); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error with spi transfer\n")); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +MvSpiFlashInitProtocol ( + IN MARVELL_SPI_FLASH_PROTOCOL *SpiFlashProtocol + ) +{ + + SpiFlashProtocol->Init = MvSpiFlashInit; + SpiFlashProtocol->ReadId = MvSpiFlashReadId; + SpiFlashProtocol->Read = MvSpiFlashRead; + SpiFlashProtocol->Write = MvSpiFlashWrite; + SpiFlashProtocol->Erase = MvSpiFlashErase; + SpiFlashProtocol->Update = MvSpiFlashUpdate; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvSpiFlashEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->LocateProtocol ( + &gMarvellSpiMasterProtocolGuid, + NULL, + (VOID **)&SpiMasterProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Cannot locate SPI Master protocol\n")); + return EFI_DEVICE_ERROR; + } + + mSpiFlashInstance = AllocateZeroPool (sizeof (SPI_FLASH_INSTANCE)); + + if (mSpiFlashInstance == NULL) { + DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); + return EFI_OUT_OF_RESOURCES; + } + + MvSpiFlashInitProtocol (&mSpiFlashInstance->SpiFlashProtocol); + + mSpiFlashInstance->Signature = SPI_FLASH_SIGNATURE; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &(mSpiFlashInstance->Handle), + &gMarvellSpiFlashProtocolGuid, + &(mSpiFlashInstance->SpiFlashProtocol), + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (mSpiFlashInstance); + DEBUG((DEBUG_ERROR, "SpiFlash: Cannot install SPI flash protocol\n")); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} diff --git a/Drivers/Spi/Devices/MvSpiFlash.h b/Drivers/Spi/Devices/MvSpiFlash.h new file mode 100755 index 0000000..3889643 --- /dev/null +++ b/Drivers/Spi/Devices/MvSpiFlash.h @@ -0,0 +1,132 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __MV_SPI_FLASH_H__ +#define __MV_SPI_FLASH_H__ + +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Uefi/UefiBaseType.h> +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/Spi.h> +#include <Protocol/SpiFlash.h> + +#define SPI_FLASH_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'I') + +#define CMD_READ_ID 0x9f +#define READ_STATUS_REG_CMD 0x0b +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_STATUS 0x05 +#define CMD_FLAG_STATUS 0x70 +#define CMD_WRITE_STATUS_REG 0x01 +#define CMD_READ_ARRAY_FAST 0x0b +#define CMD_PAGE_PROGRAM 0x02 +#define CMD_BANK_WRITE 0xc5 +#define CMD_ERASE_64K 0xd8 +#define CMD_4B_ADDR_ENABLE 0xb7 + +#define STATUS_REG_POLL_WIP (1 << 0) +#define STATUS_REG_POLL_PEC (1 << 7) + +#define SPI_TRANSFER_BEGIN 0x01 // Assert CS before transfer +#define SPI_TRANSFER_END 0x02 // Deassert CS after transfers + +#define SPI_FLASH_16MB_BOUN 0x1000000 + +typedef enum { + SPI_FLASH_READ_ID, + SPI_FLASH_READ, // Read from SPI flash with address + SPI_FLASH_WRITE, // Write to SPI flash with address + SPI_FLASH_ERASE, + SPI_FLASH_UPDATE, + SPI_COMMAND_MAX +} SPI_COMMAND; + +typedef struct { + MARVELL_SPI_FLASH_PROTOCOL SpiFlashProtocol; + UINTN Signature; + EFI_HANDLE Handle; +} SPI_FLASH_INSTANCE; + +EFI_STATUS +EFIAPI +SpiFlashReadId ( + IN SPI_DEVICE *SpiDev, + IN UINT32 DataByteCount, + IN OUT UINT8 *Buffer + ); + +EFI_STATUS +SpiFlashRead ( + IN SPI_DEVICE *Slave, + IN UINT32 Offset, + IN UINTN Length, + IN VOID *Buf + ); + +EFI_STATUS +SpiFlashWrite ( + IN SPI_DEVICE *Slave, + IN UINT32 Offset, + IN UINTN Length, + IN VOID *Buf + ); + +EFI_STATUS +SpiFlashUpdate ( + IN SPI_DEVICE *Slave, + IN UINT32 Offset, + IN UINTN ByteCount, + IN UINT8 *Buf + ); + +EFI_STATUS +SpiFlashErase ( + IN SPI_DEVICE *SpiDev, + IN UINTN Offset, + IN UINTN Length + ); + +EFI_STATUS +EFIAPI +EfiSpiFlashInit ( + IN MARVELL_SPI_FLASH_PROTOCOL *This, + IN SPI_DEVICE *Slave + ); + +#endif // __MV_SPI_FLASH_H__ diff --git a/Drivers/Spi/Devices/MvSpiFlash.inf b/Drivers/Spi/Devices/MvSpiFlash.inf new file mode 100644 index 0000000..85b1728 --- /dev/null +++ b/Drivers/Spi/Devices/MvSpiFlash.inf @@ -0,0 +1,67 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SpiFlashDxe + FILE_GUID = 49d7fb74-306d-42bd-94c8-c0c54b181dd7 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MvSpiFlashEntryPoint + +[Sources] + MvSpiFlash.c + MvSpiFlash.h + +[Packages] + MdePkg/MdePkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + TimerLib + UefiLib + DebugLib + MemoryAllocationLib + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles + gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize + gMarvellTokenSpaceGuid.PcdSpiFlashPageSize + gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + +[Protocols] + gMarvellSpiMasterProtocolGuid + gMarvellSpiFlashProtocolGuid + +[Depex] + TRUE diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 7dd3e07..a2d1956 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -121,6 +121,12 @@ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053

+ gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0|UINT32|0x3000052 + gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|0|UINT32|0x3000053 + gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 + gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 + gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 + [Protocols] gMarvellEepromProtocolGuid = { 0xcd728a1f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} gMarvellSpiMasterProtocolGuid = { 0x23de66a3, 0xf666, 0x4b3e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }}

From: Jan Dąbroś jsd@semihalf.com

sf command uses MARVELL_SPI_FLASH_PROTOCOL and MARVELL_SPI_MASTER_PROTOCOL. It allows read/write/erase/update operations on SPI flash.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Applications/SpiTool/SpiFlashCmd.c | 526 +++++++++++++++++++++++++++++++++++ Applications/SpiTool/SpiFlashCmd.inf | 75 +++++ Applications/SpiTool/SpiFlashCmd.uni | Bin 0 -> 7216 bytes Platforms/Marvell/Marvell.dec | 1 + 4 files changed, 602 insertions(+) create mode 100644 Applications/SpiTool/SpiFlashCmd.c create mode 100644 Applications/SpiTool/SpiFlashCmd.inf create mode 100644 Applications/SpiTool/SpiFlashCmd.uni

diff --git a/Applications/SpiTool/SpiFlashCmd.c b/Applications/SpiTool/SpiFlashCmd.c new file mode 100644 index 0000000..184e3d7 --- /dev/null +++ b/Applications/SpiTool/SpiFlashCmd.c @@ -0,0 +1,526 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include <Uefi.h> +#include <ShellBase.h> + +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/ShellCommandLib.h> +#include <Library/ShellLib.h> +#include <Library/UefiLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/PrintLib.h> +#include <Library/ShellCEntryLib.h> +#include <Library/HiiLib.h> +#include <Library/FileHandleLib.h> + +#include <Protocol/Spi.h> +#include <Protocol/SpiFlash.h> + +MARVELL_SPI_FLASH_PROTOCOL *SpiFlashProtocol; +MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol; + +CONST CHAR16 gShellSpiFlashFileName[] = L"ShellCommand"; +EFI_HANDLE gShellSfHiiHandle = NULL; + +BOOLEAN InitFlag = 1; + +STATIC CONST SHELL_PARAM_ITEM ParamList[] = { + {L"read", TypeFlag}, + {L"readfile", TypeFlag}, + {L"write", TypeFlag}, + {L"writefile", TypeFlag}, + {L"erase", TypeFlag}, + {L"update", TypeFlag}, + {L"updatefile", TypeFlag}, + {L"probe", TypeFlag}, + {L"help", TypeFlag}, + {NULL , TypeMax} + }; + +typedef enum { + PROBE = 1, + READ = 2, + READ_FILE = 4, + WRITE = 8, + WRITE_FILE = 16, + ERASE = 32, + UPDATE = 64, + UPDATE_FILE = 128, +} Flags; + +/** + Return the file name of the help text file if not using HII. + + @return The string pointer to the file name. +**/ +CONST CHAR16* +EFIAPI +ShellCommandGetManFileNameSpiFlash ( + VOID + ) +{ + + return gShellSpiFlashFileName; +} + +VOID +SfUsage ( + VOID + ) +{ + Print (L"\nBasic SPI command\n" + "sf [probe | read | readfile | write | writefile | erase |" + "update | updatefile]" + "[<Address> | <FilePath>] <Offset> <Length>\n\n" + "Length - Number of bytes to send\n" + "Address - Address in RAM to store/load data\n" + "FilePath - Path to file to read/write data from/to\n" + "Offset - Offset from beggining of SPI flash to store/load data\n" + "Examples:\n" + "Check if there is response from SPI flash\n" + " sf probe\n" + "Read 32 bytes from 0xe00000 of SPI flash into RAM at address 0x100000\n" + " sf read 0x100000 0xe00000 32\n" + "Read 0x20 bytes from 0x200000 of SPI flash into RAM at address 0x300000\n" + " sf read 0x300000 0x200000 0x20\n" + "Erase 0x10000 bytes from offset 0x100000 of SPI flash\n" + " sf erase 0x100000 0x100000\n" + "Write 16 bytes from 0x200000 at RAM into SPI flash at address 0x4000000\n" + " sf write 0x200000 0x4000000 16\n" + "Update 100 bytes from 0x100000 at RAM in SPI flash at address 0xe00000\n" + " sf update 0x100000 0xe00000 100\n" + "Read 0x3000 bytes from 0x0 of SPI flash into file fs2:file.bin\n" + " sf readfile fs2:file.bin 0x0 0x3000 \n" + "Update data in SPI flash at 0x3000000 from file Linux.efi\n" + " sf updatefile Linux.efi 0x3000000\n" + ); +} + +STATIC +EFI_STATUS +OpenAndPrepareFile ( + IN CHAR16 *FilePath, + SHELL_FILE_HANDLE *FileHandle + ) +{ + EFI_STATUS Status; + UINT64 OpenMode; + + OpenMode = EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE; + + Status = ShellOpenFileByName (FilePath, FileHandle, OpenMode, 0); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot open file\n"); + return Status; + } + + Status = FileHandleSetPosition(*FileHandle, 0); + + if (EFI_ERROR(Status)) { + Print (L"sf: Cannot set file position to first byte\n"); + ShellCloseFile (FileHandle); + return Status; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +FlashProbe ( + IN SPI_DEVICE *Slave + ) +{ + EFI_STATUS Status; + UINT8 IdBuffer[4]; + UINT32 Id, RefId; + + Id = PcdGet32 (PcdSpiFlashId); + + IdBuffer[0] = CMD_READ_ID; + + SpiFlashProtocol->ReadId ( + Slave, + 4, + IdBuffer + ); + + RefId = (IdBuffer[0] << 16) + (IdBuffer[1] << 8) + IdBuffer[2]; + + if (RefId == Id) { + Print (L"sf: Detected supported SPI flash with ID=%3x\n", RefId); + Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave); + if (EFI_ERROR(Status)) { + Print (L"sf: Cannot initialize flash device\n"); + return SHELL_ABORTED; + } + InitFlag = 0; + return EFI_SUCCESS; + } else if (RefId != 0) { + Print (L"sf: Unsupported SPI flash detected with ID=%2x\n", RefId); + return SHELL_ABORTED; + } + + Print (L"sf: No SPI flash detected"); + return SHELL_ABORTED; +} + +SHELL_STATUS +EFIAPI +ShellCommandRunSpiFlash ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ +EFI_STATUS Status; + SPI_DEVICE *Slave; + LIST_ENTRY *CheckPackage; + EFI_PHYSICAL_ADDRESS Address = 0, Offset = 0; + SHELL_FILE_HANDLE FileHandle = NULL; + UINTN ByteCount, FileSize, I; + UINT8 *Buffer = NULL, *FileBuffer = NULL; + CHAR16 *ProblemParam, *FilePath; + CONST CHAR16 *AddressStr = NULL, *OffsetStr = NULL; + CONST CHAR16 *LengthStr = NULL, *FileStr = NULL; + BOOLEAN AddrFlag = FALSE, LengthFlag = TRUE, FileFlag = FALSE; + UINT8 Flag = 0, CheckFlag = 0; + + Status = gBS->LocateProtocol ( + &gMarvellSpiFlashProtocolGuid, + NULL, + (VOID **)&SpiFlashProtocol + ); + if (EFI_ERROR(Status)) { + Print (L"sf: Cannot locate SpiFlash protocol\n"); + return SHELL_ABORTED; + } + + Status = gBS->LocateProtocol ( + &gMarvellSpiMasterProtocolGuid, + NULL, + (VOID **)&SpiMasterProtocol + ); + if (EFI_ERROR(Status)) { + Print (L"sf: Cannot locate SpiMaster protocol\n"); + return SHELL_ABORTED; + } + + // Parse Shell command line + Status = ShellInitialize (); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot initialize Shell\n"); + ASSERT_EFI_ERROR (Status); + return SHELL_ABORTED; + } + + Status = ShellCommandLineParse (ParamList, &CheckPackage, &ProblemParam, TRUE); + if (EFI_ERROR (Status)) { + Print (L"sf: Error while parsing command line\n"); + return SHELL_ABORTED; + } + + if (ShellCommandLineGetFlag (CheckPackage, L"help")) { + SfUsage(); + return EFI_SUCCESS; + } + + // Check flags provided by user + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"probe") << 0); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"read") << 1); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"readfile") << 2); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"write") << 3); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"writefile") << 4); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"erase") << 5); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"update") << 6); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"updatefile") << 7); + + if (InitFlag && !(Flag & PROBE)) { + Print (L"Please run sf probe\n"); + return EFI_SUCCESS; + } + + CheckFlag = Flag; + for (I = 0; CheckFlag; CheckFlag >>= 1) { + I += CheckFlag & 1; + if (I > 1) { + Print (L"sf: Too many flags\n"); + SfUsage(); + return SHELL_ABORTED; + } + } + + // Setup new spi device + Slave = SpiMasterProtocol->SetupDevice (SpiMasterProtocol, 0, 0); + if (Slave == NULL) { + Print(L"sf: Cannot allocate SPI device!\n"); + return SHELL_ABORTED; + } + + switch (Flag) { + case PROBE: + // Probe spi bus + Status = FlashProbe (Slave); + if (EFI_ERROR(Status)) { + // No supported spi flash detected + return SHELL_ABORTED; + } else { + return Status; + } + break; + // Fall through + case READ: + case WRITE: + case UPDATE: + AddressStr = ShellCommandLineGetRawValue (CheckPackage, 1); + OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2); + LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3); + AddrFlag = TRUE; + break; + case ERASE: + OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 1); + LengthStr = ShellCommandLineGetRawValue (CheckPackage, 2); + break; + case READ_FILE: + FileStr = ShellCommandLineGetRawValue (CheckPackage, 1); + OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2); + LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3); + FileFlag = TRUE; + break; + case WRITE_FILE: + case UPDATE_FILE: + FileStr = ShellCommandLineGetRawValue (CheckPackage, 1); + OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2); + LengthFlag = FALSE; + FileFlag = TRUE; + break; + } + + // Read address parameter + if ((AddressStr == NULL) & AddrFlag) { + Print (L"sf: No address parameter!\n"); + return SHELL_ABORTED; + } else if (AddrFlag) { + Address = ShellHexStrToUintn (AddressStr); + if (Address == (UINTN)(-1)) { + Print (L"sf: Wrong address parameter\n"); + return SHELL_ABORTED; + } + } + + // Read offset parameter + if (OffsetStr == NULL) { + Print (L"sf: No offset Parameter!\n"); + return SHELL_ABORTED; + } else { + Offset = ShellHexStrToUintn (OffsetStr); + if (Offset < 0) { + Print (L"sf: Wrong offset parameter: %s", OffsetStr); + return SHELL_ABORTED; + } + } + + // Read length parameter + if ((LengthStr == NULL) & LengthFlag) { + Print (L"sf: No lenght parameter!\n"); + return SHELL_ABORTED; + } else if (LengthFlag) { + ByteCount = ShellStrToUintn (LengthStr); + if (ByteCount < 0) { + Print (L"sf: Wrong length parameter %s!\n", LengthStr); + return SHELL_ABORTED; + } + } + + if (FileFlag) { + // Read FilePath parameter + if (FileStr == NULL) { + Print (L"sf: No FilePath parameter!\n"); + return SHELL_ABORTED; + } else { + FilePath = (CHAR16 *) FileStr; + Status = ShellIsFile (FilePath); + // When read file into flash, file doesn't have to exist + if (EFI_ERROR(Status && !(Flag & READ_FILE))) { + Print (L"sf: Wrong FilePath parameter!\n"); + return SHELL_ABORTED; + } + } + + Status = OpenAndPrepareFile (FilePath, &FileHandle); + if (EFI_ERROR(Status)) { + Print (L"sf: Error while preparing file\n"); + return SHELL_ABORTED; + } + + // Get file size in order to check correctness at the end of transfer + if (Flag & (WRITE_FILE | UPDATE_FILE)) { + Status = FileHandleGetSize (FileHandle, &FileSize); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot get file size\n"); + } + ByteCount = (UINTN) FileSize; + } + + FileBuffer = AllocateZeroPool ((UINTN) ByteCount); + if (FileBuffer == NULL) { + Print (L"sf: Cannot allocate memory\n"); + goto Error_Close_File; + } + + // Read file content and store it in FileBuffer + if (Flag & (WRITE_FILE | UPDATE_FILE)) { + Status = FileHandleRead (FileHandle, &ByteCount, FileBuffer); + if (EFI_ERROR (Status)) { + Print (L"sf: Read from file error\n"); + goto Error_Free_Buffer; + } else if (ByteCount != (UINTN) FileSize) { + Print (L"sf: Not whole file read. Abort\n"); + goto Error_Free_Buffer; + } + } + } + + Buffer = (UINT8 *) Address; + if (FileFlag) { + Buffer = FileBuffer; + } + + switch (Flag) { + case READ: + case READ_FILE: + Status = SpiFlashProtocol->Read (Slave, Offset, ByteCount, Buffer); + break; + case ERASE: + Status = SpiFlashProtocol->Erase (Slave, Offset, ByteCount); + break; + case WRITE: + case WRITE_FILE: + Status = SpiFlashProtocol->Write (Slave, Offset, ByteCount, Buffer); + break; + case UPDATE: + case UPDATE_FILE: + Status = SpiFlashProtocol->Update (Slave, Offset, ByteCount, Buffer); + break; + } + + SpiMasterProtocol->FreeDevice(Slave); + + if (EFI_ERROR (Status)) { + Print (L"sf: Error while performing spi transfer\n"); + return SHELL_ABORTED; + } + + switch (Flag) { + case ERASE: + Print (L"sf: %d bytes succesfully erased at offset 0x%x\n", ByteCount, + Offset); + break; + case WRITE: + case WRITE_FILE: + Print (L"sf: Write %d bytes at offset 0x%x\n", ByteCount, Offset); + break; + case UPDATE: + case UPDATE_FILE: + Print (L"sf: Update %d bytes at offset 0x%x\n", ByteCount, Offset); + break; + case READ: + Print (L"sf: Read %d bytes from offset 0x%x\n", ByteCount, Offset); + break; + case READ_FILE: + Status = FileHandleWrite (FileHandle, &ByteCount, FileBuffer); + if (EFI_ERROR(Status)) { + Print (L"sf: Error while writing into file\n"); + goto Error_Free_Buffer; + } + break; + } + + if (FileFlag) { + FreePool (FileBuffer); + + if (FileHandle != NULL) { + ShellCloseFile (&FileHandle); + } + } + + return EFI_SUCCESS; + +Error_Free_Buffer: + FreePool (FileBuffer); +Error_Close_File: + ShellCloseFile (&FileHandle); + return SHELL_ABORTED; +} + +EFI_STATUS +EFIAPI +ShellSpiFlashLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + gShellSfHiiHandle = NULL; + + gShellSfHiiHandle = HiiAddPackages ( + &gShellSfHiiGuid, gImageHandle, + UefiShellSpiFlashLibStrings, NULL + ); + if (gShellSfHiiHandle == NULL) { + return EFI_DEVICE_ERROR; + } + + ShellCommandRegisterCommandName ( + L"sf", ShellCommandRunSpiFlash, ShellCommandGetManFileNameSpiFlash, 0, + L"sf", TRUE , gShellSfHiiHandle, STRING_TOKEN (STR_GET_HELP_SF) + ); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +ShellSpiFlashLibDestructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + if (gShellSfHiiHandle != NULL) { + HiiRemovePackages (gShellSfHiiHandle); + } + return EFI_SUCCESS; +} diff --git a/Applications/SpiTool/SpiFlashCmd.inf b/Applications/SpiTool/SpiFlashCmd.inf new file mode 100644 index 0000000..d91fdf3 --- /dev/null +++ b/Applications/SpiTool/SpiFlashCmd.inf @@ -0,0 +1,75 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = UefiShellSpiFlashLib + FILE_GUID = 2f2dd8c9-221f-4acf-afe5-5897264c5774 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 0.1 + LIBRARY_CLASS = NULL|UEFI_APPLICATION UEFI_DRIVER + CONSTRUCTOR = ShellSpiFlashLibConstructor + DESTRUCTOR = ShellSpiFlashLibDestructor + +[Sources] + SpiFlashCmd.c + SpiFlashCmd.uni + +[Packages] + MdePkg/MdePkg.dec + ShellPkg/ShellPkg.dec + MdeModulePkg/MdeModulePkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec + +[LibraryClasses] + UefiLib + UefiBootServicesTableLib + MemoryAllocationLib + BaseLib + BaseMemoryLib + DebugLib + ShellCommandLib + ShellLib + UefiLib + UefiRuntimeServicesTableLib + PcdLib + HiiLib + FileHandleLib + +[Pcd] + gMarvellTokenSpaceGuid.PcdSpiFlashId + +[Protocols] + gMarvellSpiFlashProtocolGuid + gMarvellSpiMasterProtocolGuid + +[Guids] + gShellSfHiiGuid diff --git a/Applications/SpiTool/SpiFlashCmd.uni b/Applications/SpiTool/SpiFlashCmd.uni new file mode 100644 index 0000000000000000000000000000000000000000..3f25663ed79f1e7a8f6f7ca3143864e04a506fac GIT binary patch literal 7216 zcmd6s+ix316vpQniT`1hzLcs>(iZVh#Dn8FZ6xP{?KD&rRf$uFh~`4#P%81a1K)3s zPv)|=6%a_(%GuqyocYdoE^}t{*Pm<Q(Pw>q8NLYJa2c+`r*Iw4!fE(9OhXeMs`V?~ zpM~}CG<>6{op7WPzlHbVgRUlQhYO8-ueJ;IOf~m1KGE0L`$<?0Nat72-3Y_58ONQ4 zv1D9?8~ts<o^ZG%pSv9<>iHz;x4K_z95c=$k`uK|h4@VKo3N$(hbU*FahKs-ZRN_3 z)#8%Qh5D1;(H)JadTO)=NEpXTCsFcL&u8ISedyb0-i3PBH2ykjcdjQ!PNKYdcy8ki zxH7y*nP?VFUWSjFdm-i<y(K=p%{V?6F5`1B7niZ`*j$e$N^Ue4_O2syY0Po##j5ZC zo@;S-6SW5un!pdJ{T(^5m2?Jivj5}A2r|*}N`H}wEcC!$S8BPG_0IHWEv$ot<=l)l z3*M1s+G2BG>0Gj=;l-WDHR{W+M|xYv9I`H>r<Gi>Dmc*?-vA}LO|>!>N|=x2A?U?e zX4MgOp*E1?y~a|G&!3a`;0v~%;aa3WoFo+Uyvn?IEbjs{OkHQO=_~vFK1`YB^Zlo0 z%Itk2_Ru^bUCtNL?}+ky$)ZWK=>LED@<_ry@1vLHsQmdvHXch;I3_!$xbUd6tbwnY zBw~w9WKn*mrw_9FyeRPqOboWOlf^~KyN=86*mhUgEVj#hL>33P$3dAn8|h=2z;N?! z<5T1yl{fR$JZmzO9?!YQOE|O)Y(7m!hDmruf}w*m^D45C<>cJU3<Xh3-X<cEmiB}c zW5oJI5<W^7%UI5`<+(*(coQ?*Skfo@jc0gZ-*P4ETE-(oq%3$N9cmkm!Yl2iLya41 z|Jw?qa2PtuRXw#>`@Y`x!fU;4s&!NC8{v)qGLunV_3o=>pb;<CHd5Owwe{opL6qH* z-I>YQU5#MuMmW&Zo}O8KMXPdW%@y5k1`P1TdcE+2)&bctj$|g|chuU~-LM(@L7X*; zt;4vZY)eX4;|_#_=a;e7FyNJY5jS#n^c&5jfsftTbuCu|-MsavB(^kbM^Xk__0<eb zM>=mutfQ!rv$7Re+`ZFmE3yIyjda5rXwnt-ete_#K&|^4H`FXf!V7rNZWuM~=m`Xy z%C_*dtH0<8ldtu|4p<#@eO*b*c^2K1rXYlKV}7wMH#CkaY+I5ybmz@<%IyhKP<Mp` zjzKuDt*ah954<2{>`=NhlNGE5@952Z0XE*maXC_$`d+-5B%9eta!0c|@(271d=Dd% zfA1?6FIWrhuz)dbJ~31~^(Ph`=^0OJwECW|O|?6_pdG}h>*{G3zKz)W8s*-PhaKpx z7d1r>_<<eM+Hja}G2h$q`C-)2BMIigG0=4&X2C|BQh^i6hw8&)uzgo+*s8>{doZJO z+giMUgUB__-5*i}fb~!-^t2*>EuQhy<XfFP|9~^{2L6(~tCVJ%TUHq@v?g)T6Xzhp z?qmk6V6({thUQTH@Cy(46mOP0Jf1u^kp)asEb1D2)-b;ERwTh!opWKtqmwnTaYueZ z_5}%?8=EfMasar>+>*SF{8RdQ+Mz%1)8Sg=2%gr$cj3X^+k;q3a%N$d<$T7)PW>eM zCc6o5r}0E{qnc?Yn@d&84ryl|^Qw2z4@Ti#w0vJN@J@Wg{`@N;xYgc$s@3ZCZN(Mk zUM$5K2%PKst;kYGaVKWyCX;RJK8ZSk)hd|tSglZdtZK$vA$}{wNh*08KPG$iTK$|g zjx={owS`p!AUshURbi?|)*=sf_G}|rZOL5~Ue+DT+u2L@^@L~E_?lLW>Hp)ba-srj z!XNrk_kgr~qpq>DG-Gld%J*^{6&K99>^3U1=B-c|7d|p?ahX49<ywO4kLI2w@1wn~ z+ZQstjta2$t0!vNjkP=6T<guwUB@~dQ)Aw!#q5NB_(hG)BzDwu5?Q6%D_3ESy5G)H z)Jr?r3ao@>)?|gtnSI=Q=C8Xa51vHsr`4*BqLQqY_or$YZBKQ9!(-AkZ~J3n;Gg5$ znt9Z|w5j<AUurj&-3xrp<fqPqoylx;S$V@-?osn1Z?SJt$zTntT6X9*-*rnp<3(#u zH=Y~E;TLJjsliWiXhjR2!ZRlezH?X%B`dXUQDeZ<EXM6Dgk9?~1GQPKKi8MNMqezF zZ>P1^!|ximes_5!v@zrsa1X}1oOa77K<3jsiR&$734OA2J%{XFBSVkHS~8w5n9DS! z->?5l)8}^*@2_b-$22XGxh}P~J^792+>)_HS`*zVQ<QVyYEkspD<_-fdA}{MZmH!Q zN(0WzM1p;5UhJ18C+2JJd1Nok2J<|1v0r|jS!<cS@?8*}N-VULl1!Ug+k;~7vzS<9 zshT<Bis;HUo?pQ%);5pq8e6hxnLXP$Xvrm^D^XNSOc{q6?&Hh!UFLy#zDfH7zWhwz ze!XQ?c@1Bvu_Wz0$M_8DvH3DA62X+?uO*i@E%&Eo_Q_>h4oa0FPhNxdqdvD{a8<0+ zUL#1lm6mJIEH$xJYiV9(aen5EJWyryT6-d2Z|=7v<};gOZhLP8J5_B@^82ywKhSy5 zPTicx%WD*OQX*ljSg@~YRH)=YuiUR<?Mg<WuC*R){;R42_E_s_SJyQXzMgO<^{-JS k5;8CU%b-^LC{%7O+kg4mZQuLsoWobqbfzd7=Y+-YZ<!+^rT_o{

literal 0 HcmV?d00001

diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index a2d1956..e63add4 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -53,6 +53,7 @@ gMarvellTokenSpaceGuid = { 0xf995c6c8, 0xbc9b, 0x4e93, { 0xbd, 0xcf, 0x49, 0x90, 0xc6, 0xe7, 0x8c, 0x7f } }

gShellEepromHiiGuid = { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce, 0x7b, 0x91, 0x7f, 0x5f, 0x2f } } + gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } }

[PcdsFixedAtBuild.common] #MPP

From: Jan Dąbroś jsd@semihalf.com

'fupdate' command performs updating firmware from file placed on local filesystem or on TFTP server. It uses tftp and sf commands.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Applications/FirmwareUpdate/FUpdate.c | 447 ++++++++++++++++++++++++++++++++ Applications/FirmwareUpdate/FUpdate.inf | 68 +++++ Applications/FirmwareUpdate/FUpdate.uni | Bin 0 -> 5838 bytes Platforms/Marvell/Marvell.dec | 1 + 4 files changed, 516 insertions(+) create mode 100644 Applications/FirmwareUpdate/FUpdate.c create mode 100644 Applications/FirmwareUpdate/FUpdate.inf create mode 100644 Applications/FirmwareUpdate/FUpdate.uni

diff --git a/Applications/FirmwareUpdate/FUpdate.c b/Applications/FirmwareUpdate/FUpdate.c new file mode 100644 index 0000000..f1c7dbf --- /dev/null +++ b/Applications/FirmwareUpdate/FUpdate.c @@ -0,0 +1,447 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include <Uefi.h> +#include <ShellBase.h> + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/ShellCommandLib.h> +#include <Library/ShellLib.h> +#include <Library/UefiLib.h> +#include <Library/PrintLib.h> +#include <Library/UefiLib.h> +#include <Library/ShellCEntryLib.h> +#include <Library/HiiLib.h> +#include <Guid/ShellLibHiiGuid.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/FileHandleLib.h> +#include "../../../ShellPkg/Application/Shell/Shell.h" + +#define CMD_NAME_STRING L"fupdate" + +#define TFTP_CMD_STRING L"tftp " +#define SPACE_STRING L" " +#define SF_PROBE_CMD_STRING L"sf probe" +#define SF_WRITE_CMD_STRING L"sf updatefile " +#define SF_LOAD_ADDR_STRING L"0x0" + +#define MAIN_HDR_MAGIC 0xB105B002 + +typedef struct { + UINT32 Magic; // 0-3 + UINT32 PrologSize; // 4-7 + UINT32 PrologChecksum; // 8-11 + UINT32 BootImageSize; // 12-15 + UINT32 BootImageChecksum; // 16-19 + UINT32 Reserved0; // 20-23 + UINT32 LoadAddr; // 24-27 + UINT32 ExecAddr; // 28-31 + UINT8 UartConfig; // 32 + UINT8 Baudrate; // 33 + UINT8 ExtCount; // 34 + UINT8 AuxFlags; // 35 + UINT32 IoArg0; // 36-39 + UINT32 IoArg1; // 40-43 + UINT32 IoArg2; // 43-47 + UINT32 IoArg3; // 48-51 + UINT32 Reserved1; // 52-55 + UINT32 Reserved2; // 56-59 + UINT32 Reserved3; // 60-63 +} MV_IMAGE_HEADER; + +STATIC +UINT32 +CountChecksum ( + UINT32 *Start, + UINT32 Length + ) +{ + UINT32 Sum = 0; + UINT32 *Startp = Start; + + do { + Sum += *Startp; + Startp++; + Length -= 4; + } while (Length > 0); + + return Sum; +} + +STATIC +EFI_STATUS +CheckImageHeader ( + IN VOID *ImageHeader + ) +{ + MV_IMAGE_HEADER *Header; + UINT32 HeaderLength, Checksum, ChecksumBackup; + + Header = (MV_IMAGE_HEADER *) ImageHeader; + HeaderLength = Header->PrologSize; + ChecksumBackup = Header->PrologChecksum; + + // Compare magic number + if (Header->Magic != MAIN_HDR_MAGIC) { + Print (L"%s: Bad Image magic 0x%08x != 0x%08x\n", CMD_NAME_STRING, + Header->Magic, MAIN_HDR_MAGIC); + return EFI_DEVICE_ERROR; + } + + // The checksum field is discarded from calculation + Header->PrologChecksum = 0; + + Checksum = CountChecksum((UINT32 *)Header, HeaderLength); + if (Checksum != ChecksumBackup) { + Print (L"%s: Bad Image checksum. 0x%x != 0x%x\n", CMD_NAME_STRING, Checksum, + ChecksumBackup); + return EFI_DEVICE_ERROR; + } + + // Restore checksum backup + Header->PrologChecksum = ChecksumBackup; + + return 0; +} + +STATIC +EFI_STATUS +CheckFirmwareImage ( + CONST CHAR16* FirmwareImage + ) +{ + EFI_STATUS Status; + VOID *FileBuffer; + UINT64 OpenMode; + UINTN FileSize; + SHELL_FILE_HANDLE FileHandle = NULL; + + OpenMode = EFI_FILE_MODE_READ; + + Status = ShellOpenFileByName (FirmwareImage, &FileHandle, OpenMode, 0); + if (EFI_ERROR (Status)) { + Print (L"%s: Cannot open Image file\n", CMD_NAME_STRING); + return EFI_DEVICE_ERROR; + } + + Status = FileHandleGetSize (FileHandle, &FileSize); + if (EFI_ERROR (Status)) { + Print (L"%s: Cannot get Image file size\n", CMD_NAME_STRING); + } + + FileBuffer = AllocateZeroPool (FileSize); + + // Read Image header into buffer + Status = FileHandleRead (FileHandle, &FileSize, FileBuffer); + if (EFI_ERROR (Status)) { + Print (L"%s: Cannot read Image file header\n", CMD_NAME_STRING); + ShellCloseFile (&FileHandle); + FreePool (FileBuffer); + return EFI_DEVICE_ERROR; + } + + Status = CheckImageHeader (FileBuffer); + if (EFI_ERROR(Status)) { + return EFI_DEVICE_ERROR; + } + + FreePool (FileBuffer); + + return EFI_SUCCESS; +} + +STATIC +CONST CHAR16 * +FileNameFromFilePath ( + CONST CHAR16 *RemoteFilePath + ) +{ + CONST CHAR16 *Walker; + + // Gather FileName from FilePath + Walker = RemoteFilePath + StrLen (RemoteFilePath); + while ((--Walker) >= RemoteFilePath) { + if ((*Walker == L'\') || (*Walker == L'/')) { + break; + } + } + + return (Walker + 1); +} + +STATIC +CONST CHAR16* +PrepareFile ( + LIST_ENTRY *CheckPackage + ) +{ + EFI_STATUS Status; + CONST CHAR16 *ValueStr; + + ValueStr = ShellCommandLineGetValue (CheckPackage, L"-f"); + if (ValueStr == NULL) { + Print (L"%s: No LocalFilePath parameter!\n", CMD_NAME_STRING); + return NULL; + } else { + Status = ShellIsFile (ValueStr); + if (EFI_ERROR(Status)) { + Print (L"%s: Wrong LocalFilePath parameter!\n", CMD_NAME_STRING); + return NULL; + } + } + return ValueStr; +} + +CONST CHAR16 gShellFUpdateFileName[] = L"ShellCommand"; +EFI_HANDLE gShellFUpdateHiiHandle = NULL; +EFI_HANDLE gShellFUpdateHiiHandle; + +STATIC CONST SHELL_PARAM_ITEM ParamList[] = { + {L"help", TypeFlag}, + {L"-t", TypeFlag}, + {L"-f", TypeValue}, + {NULL , TypeMax} + }; + +/** + Return the file name of the help text file if not using HII. + + @return The string pointer to the file name. +**/ +CONST CHAR16* +EFIAPI +ShellCommandGetManFileNameFUpdate ( + VOID + ) +{ + + return gShellFUpdateFileName; +} + +VOID +FUpdateUsage ( + VOID + ) +{ + Print (L"\nFirmware update command\n" + "fupdate [-f <LocalFilePath>] [-t <Host> <RemoteFilePath>]\n\n" + "LocalFilePath - path to local firmware image file\n" + "Host - IP number of TFTP server\n" + "RemoteFilePath - path to firmware image file on TFTP server\n" + "Examples:\n" + "Update firmware from file fs2:Uefi.img\n" + " fupdate -f fs2:Uefi.img\n" + "Update firmware from file path/Uefi.img TFTP server with IP " + "address 10.0.0.200\n" + " fupdate -t 10.0.0.200 path/Uefi.img\n" + ); +} + +SHELL_STATUS +EFIAPI +ShellCommandRunFUpdate ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + LIST_ENTRY *CheckPackage; + CHAR16 *ProblemParam, *TftpCmd = NULL, *SfCmd = NULL; + CONST CHAR16 *RemoteFilePath, *Host, *FileToWrite; + UINT8 CmdLen; + BOOLEAN FileFlag, TftpFlag; + + Status = ShellInitialize (); + if (EFI_ERROR (Status)) { + Print (L"%s: Error while initializinf Shell\n", CMD_NAME_STRING); + ASSERT_EFI_ERROR (Status); + return SHELL_ABORTED; + } + + Status = ShellCommandLineParse (ParamList, &CheckPackage, &ProblemParam, + TRUE); + if (EFI_ERROR (Status)) { + Print (L"Parse error!\n"); + } + + if (ShellCommandLineGetFlag (CheckPackage, L"help")) { + FUpdateUsage(); + return EFI_SUCCESS; + } + + FileFlag = ShellCommandLineGetFlag (CheckPackage, L"-f"); + TftpFlag = ShellCommandLineGetFlag (CheckPackage, L"-t"); + + if (!FileFlag && !TftpFlag) { + Print (L"%s: Please specify -f or -t flag\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } else if (FileFlag && !TftpFlag) { + // Prepare local file to be burned into flash + FileToWrite = PrepareFile (CheckPackage); + if (FileToWrite == NULL) { + Print (L"%s: Error while preparing file for burn\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + } else if (TftpFlag && !FileFlag) { + Host = ShellCommandLineGetRawValue (CheckPackage, 1); + if (Host == NULL) { + Print (L"%s: No Host parameter!\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + + RemoteFilePath = ShellCommandLineGetRawValue (CheckPackage, 2); + if (RemoteFilePath == NULL) { + Print (L"%s: No remote_file_path parameter!\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + + // Gather firmware image name from remote filepath + FileToWrite = FileNameFromFilePath (RemoteFilePath); + + // Allocate buffer for tftp command string + CmdLen = StrSize (TFTP_CMD_STRING) + StrSize (SPACE_STRING) + + StrSize (Host) + StrSize (RemoteFilePath); + TftpCmd = (CHAR16 *) AllocateZeroPool (CmdLen + sizeof(CHAR16)); + if (TftpCmd == NULL) { + Print (L"%s: Cannot allocate memory\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + + // Concatenate parameters and form tftp command string + StrCatS (TftpCmd, CmdLen / sizeof(CHAR16), TFTP_CMD_STRING); + StrCatS (TftpCmd, CmdLen / sizeof(CHAR16), (CHAR16 *)Host); + // Insert space + StrCatS (TftpCmd, CmdLen / sizeof(CHAR16), SPACE_STRING); + StrCatS (TftpCmd, CmdLen / sizeof(CHAR16), (CHAR16 *)RemoteFilePath); + + RunShellCommand (TftpCmd, &Status); + FreePool (TftpCmd); + if (EFI_ERROR(Status)) { + Print (L"%s: Error while performing tftp command\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + + } else { + Print (L"%s: Both -f and -t flag specified, please choose one\n", + CMD_NAME_STRING); + return SHELL_ABORTED; + } + + // Check image checksum and magic + Status = CheckFirmwareImage (FileToWrite); + if (EFI_ERROR(Status)) { + Print (L"%s: Wrong firmware Image\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + + // Probe spi bus + RunShellCommand (SF_PROBE_CMD_STRING, &Status); + if (EFI_ERROR(Status)) { + Print (L"%s: Error while performing sf probe\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + + // Allocate buffer for sf command string + CmdLen = StrSize (SF_WRITE_CMD_STRING) + StrSize (FileToWrite) + + StrSize (SPACE_STRING) + StrSize (SF_LOAD_ADDR_STRING); + SfCmd = (CHAR16 *) AllocateZeroPool (CmdLen + sizeof(CHAR16)); + if (SfCmd == NULL) { + Print (L"%s: Cannot allocate memory\n"); + return SHELL_ABORTED; + } + + // Concatenate parameters and form command string + StrCatS (SfCmd, CmdLen / sizeof(CHAR16), SF_WRITE_CMD_STRING); + StrCatS (SfCmd, CmdLen / sizeof(CHAR16), (CHAR16 *)FileToWrite); + StrCatS (SfCmd, CmdLen / sizeof(CHAR16), SPACE_STRING); + StrCatS (SfCmd, CmdLen / sizeof(CHAR16), SF_LOAD_ADDR_STRING); + + // Update firmware image in flash + RunShellCommand (SfCmd, &Status); + FreePool (SfCmd); + if (EFI_ERROR(Status)) { + Print (L"%s: Error while performing sf update\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +ShellFUpdateCommandConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + gShellFUpdateHiiHandle = NULL; + + gShellFUpdateHiiHandle = HiiAddPackages ( + &gShellFUpdateHiiGuid, gImageHandle, + UefiShellFUpdateCommandLibStrings, NULL + ); + if (gShellFUpdateHiiHandle == NULL) { + Print (L"%s: Cannot add Hii package\n", CMD_NAME_STRING); + return EFI_DEVICE_ERROR; + } + + Status = ShellCommandRegisterCommandName ( + CMD_NAME_STRING, ShellCommandRunFUpdate, ShellCommandGetManFileNameFUpdate, + 0, CMD_NAME_STRING, TRUE , gShellFUpdateHiiHandle, + STRING_TOKEN (STR_GET_HELP_FUPDATE) + ); + if (EFI_ERROR(Status)) { + Print (L"%s: Error while registering command\n", CMD_NAME_STRING); + return SHELL_ABORTED; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +ShellFUpdateCommandDestructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + if (gShellFUpdateHiiHandle != NULL) { + HiiRemovePackages (gShellFUpdateHiiHandle); + } + return EFI_SUCCESS; +} diff --git a/Applications/FirmwareUpdate/FUpdate.inf b/Applications/FirmwareUpdate/FUpdate.inf new file mode 100644 index 0000000..53b5305 --- /dev/null +++ b/Applications/FirmwareUpdate/FUpdate.inf @@ -0,0 +1,68 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = UefiShellFUpdateCommandLib + FILE_GUID = 470292b2-926b-4ed8-8080-be7a260db627 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 0.1 + LIBRARY_CLASS = NULL|UEFI_APPLICATION UEFI_DRIVER + CONSTRUCTOR = ShellFUpdateCommandConstructor + DESTRUCTOR = ShellFUpdateCommandDestructor + +[Sources] + FUpdate.c + FUpdate.uni + +[Packages] + MdePkg/MdePkg.dec + ShellPkg/ShellPkg.dec + MdeModulePkg/MdeModulePkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec + +[LibraryClasses] + UefiLib + UefiBootServicesTableLib + MemoryAllocationLib + BaseLib + BaseMemoryLib + DebugLib + ShellCommandLib + ShellLib + UefiLib + UefiRuntimeServicesTableLib + PcdLib + HiiLib + FileHandleLib + +[Guids] + gShellFUpdateHiiGuid diff --git a/Applications/FirmwareUpdate/FUpdate.uni b/Applications/FirmwareUpdate/FUpdate.uni new file mode 100644 index 0000000000000000000000000000000000000000..6143c0580f1d1ef8ce4fe619a1df1ce380adf2c0 GIT binary patch literal 5838 zcmd6r?N1v=5XSd&rTz~m@+FOuK&z@BXdB5G6OhbHeI_(&s)*P?EX6>LDdL}R`}}4Y z_Fim)B2|h`_TBEy&OY<Z%kJL4|E#8GU-k8E`X+VLMY>G4X_hAGEPYJ#RHUcs{Z98E z(pvgH{iLVebS#O#(@FZIt4KTPT#_g1JJ*}J#$MPH@A_(w)60Z*e$BBPsZ5(DH%TMu zI8RslFVenngr*p~lTP*KR@$$1pGl4p6GJjq&s>Nn8egO>-9MS0Q^{SVsru?OKUYs^ znhN!;+Src8b3GNB10={X)7Ui6^*l)*^bUIqjXT$yRmsoHx~ZO!JT-lb@LbynxN^K` zIn^kbyht}1doJb+wK5;k=NwOk%lRBE#O3S<wy>ix&4tFo-prWGG9T<MUWEtn%*5H1 zSq~;Gfgeyu8$Ga<Z3c1n|8rvmo!EG(e{`Y?JMh~dM@OiCW&nJZN~Bn~_GrJG$Ij zd>%7RrE8wn?<20zyXy5!t%sOH*M&t|ohxPqCl(VMpv1PhX2wGq^RXfXyO3p6Go#Mc z2Xdm<S*qfT=Nvu6g3sr;me~&{8O5Tg@+clDy1)!mvr2Bp%yEAVQ*Qa<_-Qib{vL}x zEYC<E=8NnPMAdtpMc3xp|Nrt8nS_5%EXt~=;(06|k7OwvQyp_&MAmuLAl6(HxkV-N zET8D<lf1qtOCkd^gYD|%d6DaG;EFrG-4iy??Rq_;ii11ypk6r(+2fVKanpABoH=Nv z<&j#gnvCR4)Z7mbaOf4-W15N#lkkcLM+avfRa7Cb$<-)x6l5)Rn~X$TUK4VTk?W_@ za3fp1Vg<`y=axm`l~uNpw4drXy2AteUMrc`D;^ahSHUaU(DczTZEGzpC0A<w+e*W9 zlsc+aJ@t71fm-|Njar-P-BkZZdaHj%BGuK~1N96f@mhUD^=+%KZ}J1v-I3oJiR_*v zkljd!dfL}Bv#)4Y?##KOyN`eYo|vzfe%Cx8D@~G-$nUDRue)P&^aC3;wBFKIlpSg5 zO72iNcz$iYj)AD$H{9si)o*yG4ScM|VQYOh&@Gyeoy3+#?Mll)vu@v^>B#0C!#XsJ zf|V_saqr%;En@`^3fYD?u%s*OeQVKssNMs~l^TU4ynqMmO0%@1ClG9^+QQSG{;?A# z-{^-Q@H*)Fy0VpvJi0GSK?vv0{BmDzNRD0Djx=xRPRnho`V*v}?g|GSgK$w_S8s?s z@PZWCQnoXa8N7$+=-tHvY`itODpHvGO}x1#A6ZCqN25B52jU8RPYubJ$BO3*-oiRO z;7of=l<H^yiARTeCejMczOQRj{lPA12bOhRJ(cNa!`7EnL_ZOBs8-J`#SZv^9k<$X zcx*8~`ic3{Y>Z5Td2kGL9g117k*Dmy$>bxwBVzD<S9AER<a0zY(pBGjzJP<wb;~0j zat46)NHg>_BmbVy#A%ML&V78q8Fhnr$<bBU=9YU^87}oEdC(K*Aj0od2E5>-sRWMZ zNblhn9*8MgUOOV6qBc<l+)_Lm7Dv@^zN)=wg0E)Hg^|ck=D^1t#Rb(DByjF*hHkF` z;HuY_9BtH}dYtDK`s+R&t{O-1w3>cRPwrb!Y%j@~g;kdG85b+{3yV!w6Iy3>qPfzZ zX{9ojT`eo5pLsm0-dh|D(|hxLUpeqz+>;BQS42nq$~dmIf}d&5CJLW-MHLu-u?x7? zdOVi2?;F<Cx1yOQLNu-H0}g9a>}aO8dtoo~QX}3;{+%qy`l;i@HPx)wdSBPauAx3( z>^nf%KE)1&a40S~$+4?pPs1L58H!T5z)Evq`BJvzidIjPmp|l5{Q8S>lszr`Qdr`A zePHZ;Os~?Pl0b59lG~ERx38?lX)E?;i$*TP4(h0Xk3mjUJT#X_%?n8_X0gin<(*~h zvDtgF@4S(hIi(+~mG|D+OX0buJ?&^+)>Dm0=76ngbhQ19reJ%S)<S+^oo4sxJJnmY zGY6%`kVg`g?m$uXqa?6%tocvmOTIZQvTJ!v1RCa!I0-gk(Id$@uiD7@iqnDTaIo8+ zyV>(n7Ls@DKFB<FqO7V-xpu@iN36HTd@g76i6Zb~*Ok7Rt*dfT7boHmyUtp=;i;K( zo^g-W@FnOXzE@lLs*zExG5O1n$4E0i3Vj`1la=w~d*Rw6t)*%#8qJA``utI=&gXax z|FhF$H#bn-d!tC;obk9gsE#aZW7`pd*NC^C^!K$wv6t-H-o^KX5&g~k(7qbL-AH!% z2@qzF6)k>Vp2}uwYkVd1H)P>oTCvDQf3r9rtC-mFvyX}sR8P6g7q^*ax)F|8UHrt% QHyJ;b`f6NX>FQbZ9}*T`00000

literal 0 HcmV?d00001

diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index e63add4..f9d2660 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -54,6 +54,7 @@

gShellEepromHiiGuid = { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce, 0x7b, 0x91, 0x7f, 0x5f, 0x2f } } gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } } + gShellFUpdateHiiGuid = { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } }

[PcdsFixedAtBuild.common] #MPP