An upcoming fix to the generic PciHostBridgeDxe driver code requires that the limit of an unused region does not exceed the base, since they describe a 1 byte region if base equals limit.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel ard.biesheuvel@linaro.org --- Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c index 432e4230a59b..8d8c76a0f7f6 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c +++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c @@ -106,9 +106,9 @@ PciHostBridgeGetRootBridges ( // // No separate ranges for prefetchable and non-prefetchable BARs // - RootBridge->PMem.Base = 0; + RootBridge->PMem.Base = MAX_UINT64; RootBridge->PMem.Limit = 0; - RootBridge->PMemAbove4G.Base = 0; + RootBridge->PMemAbove4G.Base = MAX_UINT64; RootBridge->PMemAbove4G.Limit = 0;

ASSERT (FixedPcdGet64 (PcdPciMmio32Translation) == 0);