Code can also be found in inaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-17.04-03
Mainly include * fix SCT test fail issue * fix luvOS test fail issue * support the compatibility of kernel PCIe driver * refine the code style according Leif and Graeme's comments * drop some unnessary and some wrong patchset at v1
Chenhui Sun (6): Hisilicon: disable RC Option Rom Hisilicon: Add reconfig lane number feature Hisilicon/D03/D05: Change Monotonic Drive D03: update acpi tables to ACPI6.1 D05: update acpi tables to ACPI6.1 D02: update acpi tables to ACPI6.1
hensonwang (3): Hisilicon/D05: support the compatibility of kernel PCIe driver Hisilicon/D03: support the compatibility of kernel PCIe driver Hisilicon/D05: add num-pins package for Roce
shaochangliang (2): Hisilicon/UpdateFdtDxe: fix memory overflow issue Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue.
wangyue (6): Hisilicon: Fix ACPI/DSDT table checksum error Hisilicon/D02: fix IORT test issue in luvOS test Hisilicon/D03: Fix IORT test issue in luvOS test Hisilicon/D05: Fix IORT test issue in luvOS test Hisilicon/FlashFvbDxe: Add Reset interface for block IO protocol Hisilicon/RamDisk: Add Reset interface for block IO protocol
Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c | 22 ++ Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 13 + .../Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c | 2 +- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 184 ++++++++- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 + .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 12 +- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 20 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 159 ++++---- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 30 +- .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 120 +++--- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 32 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 16 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 152 ++++---- .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 7 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 399 ++++++++++++++++++- Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 42 +- .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 424 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 28 +- Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 30 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 126 +++--- Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 20 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 6 +- Drivers/Block/ramdisk/ramdisk.c | 13 + Platforms/Hisilicon/D03/D03.dsc | 1 - Platforms/Hisilicon/D03/D03.fdf | 2 +- Platforms/Hisilicon/D05/D05.dsc | 1 - Platforms/Hisilicon/D05/D05.fdf | 2 +- 38 files changed, 1335 insertions(+), 698 deletions(-)
The size of the updated DTB file may be increased, so we need to allocate more memory than the original DTB size,or memory overflow may happen.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang shaochangliang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c index 8586e33..699a820 100644 --- a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c +++ b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c @@ -112,7 +112,7 @@ EFIAPI UpdateFdt ( Size = (UINTN)fdt_totalsize ((VOID*)(PcdGet64(FdtFileAddress))); NewFdtBlobSize = Size + ADD_FILE_LENGTH;
- Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(Size), &NewFdtBlobBase); + Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); if (EFI_ERROR (Status)) { return EFI_OUT_OF_RESOURCES;
On Sat, Apr 01, 2017 at 07:29:06PM +0800, Chenhui Sun wrote:
The size of the updated DTB file may be increased, so we need to allocate more memory than the original DTB size,or memory overflow may happen.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang shaochangliang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Thanks, pushed as bb301e7ef8.
Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c index 8586e33..699a820 100644 --- a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c +++ b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c @@ -112,7 +112,7 @@ EFIAPI UpdateFdt ( Size = (UINTN)fdt_totalsize ((VOID*)(PcdGet64(FdtFileAddress))); NewFdtBlobSize = Size + ADD_FILE_LENGTH;
- Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(Size), &NewFdtBlobBase);
- Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); if (EFI_ERROR (Status)) { return EFI_OUT_OF_RESOURCES;
-- 1.9.1
The I350 Hilink state is not stable, so we need to modify the rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang shaochangliang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 2 ++ Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 ++++ 2 files changed, 6 insertions(+)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 0b5a659..be02044 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -470,6 +470,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); Value |= (1 << 20); //bit 20: rxvalid enable RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \ + CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG); } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9671c57..9a0f636 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -70,6 +70,10 @@
#define PCS_SDS_CFG_REG 0x204 #define SDS_CFG_STRIDE 0x4 +#define MUX_LOS_ALOS_REG_OFFSET 0x508 +#define MUX_CFG_STRIDE 0x4 +#define CH_RXTX_STATUS_CFG_EN BIT1 +#define CH_RXTX_STATUS_CFG BIT2 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr))
On Sat, Apr 01, 2017 at 07:29:07PM +0800, Chenhui Sun wrote:
The I350 Hilink state is not stable, so we need to modify the rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang shaochangliang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 2 ++ Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 ++++ 2 files changed, 6 insertions(+)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 0b5a659..be02044 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -470,6 +470,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); Value |= (1 << 20); //bit 20: rxvalid enable RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG);
Not addressed from previous feedback: spaces around '|'.
The rest looks fine now.
/ Leif
} PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9671c57..9a0f636 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -70,6 +70,10 @@ #define PCS_SDS_CFG_REG 0x204 #define SDS_CFG_STRIDE 0x4 +#define MUX_LOS_ALOS_REG_OFFSET 0x508 +#define MUX_CFG_STRIDE 0x4 +#define CH_RXTX_STATUS_CFG_EN BIT1 +#define CH_RXTX_STATUS_CFG BIT2 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr)) -- 1.9.1
The M3(the coprocessor)PCIe driver will read Option Rom header durning enumeration, this operation will cause a completion error when there is no device inserted to the RC port, and the Option rom is uesless now. So we need to disable the RC Option Rom.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index be02044..8ec094f 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -901,6 +901,50 @@ void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) return; }
+UINT32 +SysRegRead ( + IN UINT32 SocType, + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINTN Reg + ) +{ + UINT32 Value; + if (SocType == 0x1610) { + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value); + } else { + //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE + //in the same hostbridge. + RegRead (PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value); + } + return Value; +} + +VOID +DisableRcOptionRom ( + IN UINT32 Soctype, + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN PCIE_PORT_TYPE PcieType +) +{ + UINT32 Value = 0; + if (PcieType == PCIE_ROOT_COMPLEX) { + Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); + Value |= BIT2; //cs2 enable + SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); + + Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG); + Value &= ~BIT0; //disable option rom + SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG, Value); + + Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); + Value &= ~BIT2; //cs2 disable + SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); + } + return; +} + EFI_STATUS EFIAPI PciePortInit ( @@ -961,6 +1005,8 @@ PciePortInit ( /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
+ /* Disable RC Option Rom */ + DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) {
On Sat, Apr 01, 2017 at 07:29:08PM +0800, Chenhui Sun wrote:
The M3(the coprocessor)PCIe driver will read Option Rom header durning enumeration, this operation will cause a completion error when there is no device inserted to the RC port, and the Option rom is uesless now. So we need to disable the RC Option Rom.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
.../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index be02044..8ec094f 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -901,6 +901,50 @@ void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) return; } +UINT32 +SysRegRead (
- IN UINT32 SocType,
- IN UINT32 HostBridgeNum,
- IN UINT32 Port,
- IN UINTN Reg
- )
+{
- UINT32 Value;
- if (SocType == 0x1610) {
- RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value);
- } else {
- //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
- //in the same hostbridge.
- RegRead (PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value);
- }
- return Value;
+}
+VOID +DisableRcOptionRom (
- IN UINT32 Soctype,
- IN UINT32 HostBridgeNum,
- IN UINT32 Port,
- IN PCIE_PORT_TYPE PcieType
+) +{
- UINT32 Value = 0;
- if (PcieType == PCIE_ROOT_COMPLEX) {
- Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG);
- Value |= BIT2; //cs2 enable
- SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value);
- Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG);
- Value &= ~BIT0; //disable option rom
- SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG, Value);
- Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG);
- Value &= ~BIT2; //cs2 disable
- SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value);
- }
- return;
+}
EFI_STATUS EFIAPI PciePortInit ( @@ -961,6 +1005,8 @@ PciePortInit ( /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
/* Disable RC Option Rom */DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) {-- 1.9.1
In some cases, the PCIe device may close part of lanes in config state of LTSSM, the hip06 RC should reconfig lane number and try to linkup again.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 136 ++++++++++++++++++++- Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + 2 files changed, 139 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 8ec094f..bd91ca4 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -39,6 +39,14 @@ extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg; extern PCIE_IATU gastr_pcie_iatu_cfg; extern PCIE_IATU_VA mPcieIatuTable;
+EFI_STATUS +EFIAPI +PciePortInit ( + IN UINT32 soctype, + IN UINT32 HostBridgeNum, + IN PCIE_DRIVER_CFG *PcieCfg + ); + VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value) { RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value); @@ -149,8 +157,131 @@ VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN } } } +/* + * The ltssm register is assigned in an asynchronous way, the value + * of register may not right in metastable state. + * Read the register twice to get stable value. + */ +VOID PcieGetLtssmValue ( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINT32 *Value + ) +{ + UINT32 ValueA; + UINT32 ValueB = 0; + UINT32 Count; + + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueA); + ValueA = ValueA & PCIE_LTSSM_STATE_MASK; + + Count = 0; + while (Count < 2) { + + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueB); + ValueB = ValueB & PCIE_LTSSM_STATE_MASK; + + /* Get the same state in continuous two times*/ + if (ValueA == ValueB) { + break; + } + + //If the second value not equal to the first, we return the second one as the stable + ValueA = ValueB; + Count++; + } + + *Value = ValueB; + + return; + +} + +/* + * In some cases, the PCIe device may close part of lanes in + * config state of LTSSM, the hip06 RC should reconfig lane num + * and try to linkup again. + */ +VOID PcieReconfigLaneNum ( + IN UINT32 soctype, + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN PCIE_DRIVER_CFG *PcieCfg + ) +{ + EFI_STATUS Status; + UINT32 LtssmStatus; + UINT32 RegVal; + UINT32 LoopCnt = 0; + UINT32 LaneNumCnt = 0; + PCIE_PORT_WIDTH PortWidth = PcieCfg->PortInfo.PortWidth; + + // 500 * 200us = 100ms, so it takes 100 ms must to reconfig lane numbers + while (LoopCnt < 500) { + + /* + * The minimum lanenum is 1, no need to try any more. + */ + if (PortWidth <= 1) { + DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum PortWidth <= 1 !\n")); + return; + } + + /* + * Check the lane num config state is normal or not. + */ + PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus); + if ((LtssmStatus == PCIE_LTSSM_CFG_LANENUM_ACPT) || (LtssmStatus == PCIE_LTSSM_CFG_COMPLETE)) { + LaneNumCnt++; + } else if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) { + PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus); + if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) { + break; + } + } else { + LaneNumCnt = 0; + } + + /* + * The lane num config state is abnormal, need to reconfig + * the lane num and try to establish link again. + */ + if (LaneNumCnt > MAX_TRY_LINK_NUM) { + /* Disable LTSSM */ + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal); + RegVal &= ~(LTSSM_ENABLE); + RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal); + /* + * Decrease the PortWidth and try to link again, + * the value of PortWidth 0xf (X8), 0x7(x4), 0x3(X2), 0x1(X1) + */ + PcieCfg->PortInfo.PortWidth = (PCIE_PORT_WIDTH)((UINT8)PcieCfg->PortInfo.PortWidth >> 1); + + Status = PciePortInit (soctype, HostBridgeNum, PcieCfg); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port)); + } + return; + } + + LoopCnt++; + /* Pcie 3.0 Spec,part 4.2.6.3.4.1: the Upstream Lanes are permitted + * delay up to 1 ms before transitioning to Configuration.Lanenum.Accept. + * So the delay time 200 us * 5(LanNumCnt) = 1ms, not beyond the reasonable range. + */ + MicroSecondDelay (200); + } + + return ; +}
-EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) +EFI_STATUS +PcieEnableItssm ( + IN UINT32 soctype, + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN PCIE_DRIVER_CFG *PcieCfg + ) { PCIE_CTRL_7_U pcie_ctrl7; UINT32 Value = 0; @@ -165,6 +296,7 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) Value |= BIT11|BIT30|BIT31; RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1); + PcieReconfigLaneNum (soctype, HostBridgeNum, Port, PcieCfg); return EFI_SUCCESS; } else @@ -1008,7 +1140,7 @@ PciePortInit ( /* Disable RC Option Rom */ DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ - (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); + (VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { //PCIe will still work even if performance tuning fails, //and there is warning message inside the function to print diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index 539d567..bf57652 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -8982,6 +8982,7 @@ typedef union tagIepMsiCtrlIntStatus #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) #define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) +#define PCIE_SYS_STATE4_REG (PCI_SYS_BASE + 0x31C) #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) @@ -12694,7 +12695,11 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6814) #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6818) #define PCIE_LTSSM_STATE_MASK (0x3f) +#define PCIE_LTSSM_CFG_LANENUM_ACPT 0x0a +#define PCIE_LTSSM_CFG_COMPLETE 0x0b #define PCIE_LTSSM_LINKUP_STATE (0x11) +#define LTSSM_ENABLE BIT11 +#define MAX_TRY_LINK_NUM 5 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6880) #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6884) #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6890)
On Sat, Apr 01, 2017 at 07:29:09PM +0800, Chenhui Sun wrote:
In some cases, the PCIe device may close part of lanes in config state of LTSSM, the hip06 RC should reconfig lane number and try to linkup again.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
.../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 136 ++++++++++++++++++++- Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + 2 files changed, 139 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 8ec094f..bd91ca4 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -39,6 +39,14 @@ extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg; extern PCIE_IATU gastr_pcie_iatu_cfg; extern PCIE_IATU_VA mPcieIatuTable; +EFI_STATUS +EFIAPI +PciePortInit (
- IN UINT32 soctype,
- IN UINT32 HostBridgeNum,
- IN PCIE_DRIVER_CFG *PcieCfg
- );
VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value) { RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value); @@ -149,8 +157,131 @@ VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN } } } +/*
- The ltssm register is assigned in an asynchronous way, the value
- of register may not right in metastable state.
- Read the register twice to get stable value.
- */
+VOID PcieGetLtssmValue (
- IN UINT32 HostBridgeNum,
- IN UINT32 Port,
- IN UINT32 *Value
- )
+{
- UINT32 ValueA;
- UINT32 ValueB = 0;
- UINT32 Count;
- RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueA);
- ValueA = ValueA & PCIE_LTSSM_STATE_MASK;
- Count = 0;
- while (Count < 2) {
- RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueB);
- ValueB = ValueB & PCIE_LTSSM_STATE_MASK;
- /* Get the same state in continuous two times*/
- if (ValueA == ValueB) {
break;- }
- //If the second value not equal to the first, we return the second one as the stable
- ValueA = ValueB;
- Count++;
- }
- *Value = ValueB;
- return;
+}
+/*
- In some cases, the PCIe device may close part of lanes in
- config state of LTSSM, the hip06 RC should reconfig lane num
- and try to linkup again.
- */
+VOID PcieReconfigLaneNum (
- IN UINT32 soctype,
- IN UINT32 HostBridgeNum,
- IN UINT32 Port,
- IN PCIE_DRIVER_CFG *PcieCfg
- )
+{
- EFI_STATUS Status;
- UINT32 LtssmStatus;
- UINT32 RegVal;
- UINT32 LoopCnt = 0;
- UINT32 LaneNumCnt = 0;
- PCIE_PORT_WIDTH PortWidth = PcieCfg->PortInfo.PortWidth;
- // 500 * 200us = 100ms, so it takes 100 ms must to reconfig lane numbers
- while (LoopCnt < 500) {
- /*
* The minimum lanenum is 1, no need to try any more.*/- if (PortWidth <= 1) {
DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum PortWidth <= 1 !\n"));return;- }
- /*
* Check the lane num config state is normal or not.*/- PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus);
- if ((LtssmStatus == PCIE_LTSSM_CFG_LANENUM_ACPT) || (LtssmStatus == PCIE_LTSSM_CFG_COMPLETE)) {
LaneNumCnt++;- } else if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) {
PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus);if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) {break;}- } else {
LaneNumCnt = 0;- }
- /*
* The lane num config state is abnormal, need to reconfig* the lane num and try to establish link again.*/- if (LaneNumCnt > MAX_TRY_LINK_NUM) {
/* Disable LTSSM */RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal);RegVal &= ~(LTSSM_ENABLE);RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal);/** Decrease the PortWidth and try to link again,* the value of PortWidth 0xf (X8), 0x7(x4), 0x3(X2), 0x1(X1)*/PcieCfg->PortInfo.PortWidth = (PCIE_PORT_WIDTH)((UINT8)PcieCfg->PortInfo.PortWidth >> 1);Status = PciePortInit (soctype, HostBridgeNum, PcieCfg);if (EFI_ERROR(Status)) {DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));}return;- }
- LoopCnt++;
- /* Pcie 3.0 Spec,part 4.2.6.3.4.1: the Upstream Lanes are permitted
* delay up to 1 ms before transitioning to Configuration.Lanenum.Accept.* So the delay time 200 us * 5(LanNumCnt) = 1ms, not beyond the reasonable range.*/- MicroSecondDelay (200);
- }
- return ;
+} -EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) +EFI_STATUS +PcieEnableItssm (
- IN UINT32 soctype,
- IN UINT32 HostBridgeNum,
- IN UINT32 Port,
- IN PCIE_DRIVER_CFG *PcieCfg
- )
{ PCIE_CTRL_7_U pcie_ctrl7; UINT32 Value = 0; @@ -165,6 +296,7 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) Value |= BIT11|BIT30|BIT31; RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
PcieReconfigLaneNum (soctype, HostBridgeNum, Port, PcieCfg); return EFI_SUCCESS;@@ -1008,7 +1140,7 @@ PciePortInit ( /* Disable RC Option Rom */ DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */
(VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex);
(VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { //PCIe will still work even if performance tuning fails, //and there is warning message inside the function to printdiff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index 539d567..bf57652 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -8982,6 +8982,7 @@ typedef union tagIepMsiCtrlIntStatus #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) #define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) +#define PCIE_SYS_STATE4_REG (PCI_SYS_BASE + 0x31C) #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) @@ -12694,7 +12695,11 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6814) #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6818) #define PCIE_LTSSM_STATE_MASK (0x3f) +#define PCIE_LTSSM_CFG_LANENUM_ACPT 0x0a +#define PCIE_LTSSM_CFG_COMPLETE 0x0b #define PCIE_LTSSM_LINKUP_STATE (0x11) +#define LTSSM_ENABLE BIT11 +#define MAX_TRY_LINK_NUM 5 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6880) #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6884)
#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6890)
1.9.1
Refresh checksum after changing DSDT table.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c index 41f5692..e22015a 100644 --- a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c +++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c @@ -442,6 +442,27 @@ static EFI_STATUS ProcessDSDT( return EFI_SUCCESS; }
+VOID +AcpiChecksum ( + IN OUT UINT8 *Buffer, + IN UINTN Size + ) +{ + UINTN ChecksumOffset; + + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + + // + // set checksum to 0 first + // + Buffer[ChecksumOffset] = 0; + + // + // Update checksum value + // + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size); +} + EFI_STATUS EthMacInit(void) { EFI_STATUS Status; @@ -478,6 +499,7 @@ EFI_STATUS EthMacInit(void) ProcessDSDT(AcpiTableProtocol, TableHandle);
AcpiTableProtocol->Close(TableHandle); + AcpiChecksum ((UINT8*)Table, Table->Length); }
return EFI_SUCCESS;
On Sat, Apr 01, 2017 at 07:29:10PM +0800, Chenhui Sun wrote:
Refresh checksum after changing DSDT table.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
See my last comment on v1.
Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c index 41f5692..e22015a 100644 --- a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c +++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c @@ -442,6 +442,27 @@ static EFI_STATUS ProcessDSDT( return EFI_SUCCESS; } +VOID +AcpiChecksum (
- IN OUT UINT8 *Buffer,
- IN UINTN Size
- )
+{
- UINTN ChecksumOffset;
- ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
- //
- // set checksum to 0 first
- //
- Buffer[ChecksumOffset] = 0;
- //
- // Update checksum value
- //
- Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
+}
EFI_STATUS EthMacInit(void) { EFI_STATUS Status; @@ -478,6 +499,7 @@ EFI_STATUS EthMacInit(void) ProcessDSDT(AcpiTableProtocol, TableHandle); AcpiTableProtocol->Close(TableHandle);
- AcpiChecksum ((UINT8*)Table, Table->Length); }
return EFI_SUCCESS; -- 1.9.1
Luvos test report: "FAILED [HIGH] IORTMemAttrInvalid: Test 1, IORT PCI Root Complex Node Memory Attributes are illegal, CCA cannot be 1 if CPM is 0."
Reference to 《DEN0049B_IO_Remapping_Table》 3.1.1.4 Table13 and Table14: “Note that if CCA is 0x1, CPM must also be 0x1. Conversely, If CPM is 0x0 then CCA must be 0x0.”
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.com --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index bcd31d6..8f38359 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -205,8 +205,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000001 @@ -234,8 +234,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002
On Sat, Apr 01, 2017 at 07:29:11PM +0800, Chenhui Sun wrote:
Luvos test report: "FAILED [HIGH] IORTMemAttrInvalid: Test 1, IORT PCI Root Complex Node Memory Attributes are illegal, CCA cannot be 1 if CPM is 0."
Reference to 《DEN0049B_IO_Remapping_Table》 3.1.1.4 Table13 and Table14: “Note that if CCA is 0x1, CPM must also be 0x1. Conversely, If CPM is 0x0 then CCA must be 0x0.”
Thanks for the change
For Patches 6,7,8
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.com
Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index bcd31d6..8f38359 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -205,8 +205,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0+[0001] Memory Flags (decoded below) : 01
Coherency : 1 Device Attribute : 0[0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000001 @@ -234,8 +234,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0+[0001] Memory Flags (decoded below) : 01
Coherency : 1 Device Attribute : 0[0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 -- 1.9.1
On Sat, Apr 01, 2017 at 07:29:11PM +0800, Chenhui Sun wrote:
Luvos test report: "FAILED [HIGH] IORTMemAttrInvalid: Test 1, IORT PCI Root Complex Node Memory Attributes are illegal, CCA cannot be 1 if CPM is 0."
Reference to 《DEN0049B_IO_Remapping_Table》 3.1.1.4 Table13 and Table14: “Note that if CCA is 0x1, CPM must also be 0x1. Conversely, If CPM is 0x0 then CCA must be 0x0.”
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.com
This, and the following two: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Pushed as bb301e7ef8..fd643be501.
/ Leif
Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index bcd31d6..8f38359 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -205,8 +205,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0+[0001] Memory Flags (decoded below) : 01
Coherency : 1 Device Attribute : 0[0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000001 @@ -234,8 +234,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00
Coherency : 0+[0001] Memory Flags (decoded below) : 01
Coherency : 1 Device Attribute : 0[0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 -- 1.9.1
CLuvos test report: "FAILED [HIGH] IORTMemAttrInvalid: Test 1, IORT PCI Root Complex Node Memory Attributes are illegal, CCA cannot be 1 if CPM is 0."
Reference to 《DEN0049B_IO_Remapping_Table》 3.1.1.4 Table13 and Table14: “Note that if CCA is 0x1, CPM must also be 0x1. Conversely, If CPM is 0x0 then CCA must be 0x0.”
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.com --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index 9a045b7..9295485 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -296,8 +296,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000000 @@ -325,8 +325,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000001 @@ -354,8 +354,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002
CLuvos test report: "FAILED [HIGH] IORTMemAttrInvalid: Test 1, IORT PCI Root Complex Node Memory Attributes are illegal, CCA cannot be 1 if CPM is 0."
Reference to 《DEN0049B_IO_Remapping_Table》 3.1.1.4 Table13 and Table14: “Note that if CCA is 0x1, CPM must also be 0x1. Conversely, If CPM is 0x0 then CCA must be 0x0.”
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.com --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 61a3c33..50ccac1 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -406,8 +406,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 @@ -434,8 +434,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000004 @@ -463,8 +463,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005 @@ -492,8 +492,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000006 @@ -520,8 +520,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000007 @@ -548,8 +548,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000a @@ -577,8 +577,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000c @@ -606,8 +606,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000d
Add Reset interface for block IO protocol to make it compliant with UEFI specification, or it will cause exception when the interface is called.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c index 544228a..7c6b64c 100644 --- a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c +++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c @@ -444,6 +444,18 @@ FvbGetBlockSize ( return Status; }
+STATIC +EFI_STATUS +EFIAPI +FvbReset( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification +) +{ + return EFI_SUCCESS; +} + + /** Reads the specified number of bytes into a buffer from the specified block.
@@ -921,6 +933,7 @@ FlashCreateInstance ( Instance->Size = FlashSize;
Instance->BlockIoProtocol.Media = &Instance->Media; + Instance->BlockIoProtocol.Reset = FvbReset; Instance->Media.MediaId = MediaId; Instance->Media.BlockSize = BlockSize; Instance->Media.LastBlock = (FlashSize / BlockSize) - 1;
On Sat, Apr 01, 2017 at 07:29:14PM +0800, Chenhui Sun wrote:
Add Reset interface for block IO protocol to make it compliant with UEFI specification, or it will cause exception when the interface is called.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Pushed.
Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c index 544228a..7c6b64c 100644 --- a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c +++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c @@ -444,6 +444,18 @@ FvbGetBlockSize ( return Status; } +STATIC +EFI_STATUS +EFIAPI +FvbReset(
- IN EFI_BLOCK_IO_PROTOCOL *This,
- IN BOOLEAN ExtendedVerification
+) +{
- return EFI_SUCCESS;
+}
/** Reads the specified number of bytes into a buffer from the specified block. @@ -921,6 +933,7 @@ FlashCreateInstance ( Instance->Size = FlashSize; Instance->BlockIoProtocol.Media = &Instance->Media;
- Instance->BlockIoProtocol.Reset = FvbReset; Instance->Media.MediaId = MediaId; Instance->Media.BlockSize = BlockSize; Instance->Media.LastBlock = (FlashSize / BlockSize) - 1;
-- 1.9.1
Add Reset interface for block IO protocol to make it compliant with UEFI specification, or it will cause exception when the interface is called.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- Drivers/Block/ramdisk/ramdisk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/Drivers/Block/ramdisk/ramdisk.c b/Drivers/Block/ramdisk/ramdisk.c index 21e090b..1403018 100644 --- a/Drivers/Block/ramdisk/ramdisk.c +++ b/Drivers/Block/ramdisk/ramdisk.c @@ -200,6 +200,18 @@ UINT8 TestSize(UINT32 ts)
EFI_SYSTEM_TABLE BackupSystemTable;
+STATIC +EFI_STATUS +EFIAPI +RamDiskReset( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification +) +{ + return EFI_SUCCESS; +} + + /* * Entry point for RamDisk driver. */ @@ -274,6 +286,7 @@ EFI_STATUS InitializeRamDiskDriver( RamDiskDev->BlkIo.ReadBlocks = RamDiskReadBlocks; RamDiskDev->BlkIo.WriteBlocks = RamDiskWriteBlocks; RamDiskDev->BlkIo.FlushBlocks = RamDiskFlushBlocks; + RamDiskDev->BlkIo.Reset = RamDiskReset;
RamDiskDev->DevicePath = DuplicateDevicePath((EFI_DEVICE_PATH*)&RamDiskDevicePath);
On Sat, Apr 01, 2017 at 07:29:15PM +0800, Chenhui Sun wrote:
Add Reset interface for block IO protocol to make it compliant with UEFI specification, or it will cause exception when the interface is called.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Pushed.
Drivers/Block/ramdisk/ramdisk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/Drivers/Block/ramdisk/ramdisk.c b/Drivers/Block/ramdisk/ramdisk.c index 21e090b..1403018 100644 --- a/Drivers/Block/ramdisk/ramdisk.c +++ b/Drivers/Block/ramdisk/ramdisk.c @@ -200,6 +200,18 @@ UINT8 TestSize(UINT32 ts) EFI_SYSTEM_TABLE BackupSystemTable; +STATIC +EFI_STATUS +EFIAPI +RamDiskReset(
- IN EFI_BLOCK_IO_PROTOCOL *This,
- IN BOOLEAN ExtendedVerification
+) +{
- return EFI_SUCCESS;
+}
/*
- Entry point for RamDisk driver.
*/ @@ -274,6 +286,7 @@ EFI_STATUS InitializeRamDiskDriver( RamDiskDev->BlkIo.ReadBlocks = RamDiskReadBlocks; RamDiskDev->BlkIo.WriteBlocks = RamDiskWriteBlocks; RamDiskDev->BlkIo.FlushBlocks = RamDiskFlushBlocks;
- RamDiskDev->BlkIo.Reset = RamDiskReset;
RamDiskDev->DevicePath = DuplicateDevicePath((EFI_DEVICE_PATH*)&RamDiskDevicePath); -- 1.9.1
As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx).
1. add _OSC support 2. put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver. 3. add reserved ecam resource
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 399 ++++++++++++++++++++- 1 file changed, 384 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index f9b4722..79267e5 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -40,6 +40,49 @@ Scope(_SB) } }
+/* + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 +*/ +#define PCI_OSC_SUPPORT() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Do not allow native PME, AER */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x10,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + // 1P NA PCIe2 Device (PCI2) { @@ -89,17 +132,44 @@ Scope(_SB) Device (RES2) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (0xf) }
} // Device(PCI2) + + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x2) // Unique ID + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + Device (R1NA) // reserve 1p NA ECAM resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + // 1p NB PCIe0 Device (PCI4) { @@ -149,10 +219,9 @@ Scope(_SB) Device (RES4) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory ( - ResourceProducer, + ResourceConsumer, PosDecode, MinFixed, MaxFixed, @@ -166,12 +235,38 @@ Scope(_SB) ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) }
} // Device(PCI4) + Device (RES4) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x4) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0090000, // Min Base Address + 0x8a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + }
// 1P NB PCI1 Device (PCI5) @@ -222,10 +317,9 @@ Scope(_SB) Device (RES5) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory ( - ResourceProducer, + ResourceConsumer, PosDecode, MinFixed, MaxFixed, @@ -239,11 +333,37 @@ Scope(_SB) ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI5) + Device (RES5) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x5) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0200000, // Min Base Address + 0x8a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + }
// 1P NB PCIe2 Device (PCI6) @@ -294,10 +414,9 @@ Scope(_SB) Device (RES6) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory ( - ResourceProducer, + ResourceConsumer, PosDecode, MinFixed, MaxFixed, @@ -311,11 +430,37 @@ Scope(_SB) ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI6) + Device (RES6) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x6) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00a0000, // Min Base Address + 0x8a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } // 1P NB PCIe3 Device (PCI7) { @@ -365,10 +510,9 @@ Scope(_SB) Device (RES7) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory ( - ResourceProducer, + ResourceConsumer, PosDecode, MinFixed, MaxFixed, @@ -382,11 +526,100 @@ Scope(_SB) ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI7) + Device (RES7) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x7) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00b0000, // Min Base Address + 0x8a00bffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } + + Device (R1NB) // reserve 1p NB ECAM resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 88-8f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a8800000, // Min Base Address + 0x8a8ffffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus 0-7] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8b0000000, // Min Base Address + 0x8b07fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus c0-c7] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8ac000000, // Min Base Address + 0x8ac7fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus 90-97] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8b9000000, // Min Base Address + 0x8b97fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } // 2P NA PCIe2 Device (PCIa) { @@ -436,10 +669,9 @@ Scope(_SB) Device (RESa) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory ( - ResourceProducer, + ResourceConsumer, PosDecode, MinFixed, MaxFixed, @@ -453,11 +685,61 @@ Scope(_SB) ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (0xf) } } // Device(PCIa) + Device (RESa) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xa) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x600a00a0000, // Min Base Address + 0x600a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + Device (R2NA) //reserve for 2p NA ecam resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 10-1f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x64001000000, // Min Base Address + 0x64001ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } // 2P NB PCIe0 Device (PCIc) { @@ -507,10 +789,9 @@ Scope(_SB) Device (RESc) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory ( - ResourceProducer, + ResourceConsumer, PosDecode, MinFixed, MaxFixed, @@ -524,12 +805,38 @@ Scope(_SB) ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCIc)
+ Device (RESc) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xc) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0090000, // Min Base Address + 0x700a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } //2P NB PCIe1 Device (PCId) { @@ -579,10 +886,9 @@ Scope(_SB) Device (RESd) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory ( - ResourceProducer, + ResourceConsumer, PosDecode, MinFixed, MaxFixed, @@ -596,10 +902,73 @@ Scope(_SB) ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCId) + Device (RESd) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xd) // Unique ID + Name (_CRS, ResourceTemplate (){ //host bridge register space + QwordMemory ( + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0200000, // Min Base Address + 0x700a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } + + Device (R2NB) //reserve for 2p NB ecam resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 20-2f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x74002000000, // Min Base Address + 0x74002ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + QwordMemory ( //ECAM space for [bus 30-3f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x78003000000, // Min Base Address + 0x78003ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } }
On Sat, Apr 01, 2017 at 07:29:16PM +0800, Chenhui Sun wrote:
As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx).
- add _OSC support
- put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver.
- add reserved ecam resource
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
Thanks much easier to read without the indentation changes.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
.../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 399 ++++++++++++++++++++- 1 file changed, 384 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index f9b4722..79267e5 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -40,6 +40,49 @@ Scope(_SB) } } +/*
- See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
+*/ +#define PCI_OSC_SUPPORT() \
- Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
- Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
- Method(_OSC,4) { \
- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
/* Create DWord-adressable fields from the Capabilities Buffer */ \CreateDWordField(Arg3,0,CDW1) \CreateDWordField(Arg3,4,CDW2) \CreateDWordField(Arg3,8,CDW3) \/* Save Capabilities DWord2 & 3 */ \Store(CDW2,SUPP) \Store(CDW3,CTRL) \/* Only allow native hot plug control if OS supports: */ \/* ASPM */ \/* Clock PM */ \/* MSI/MSI-X */ \If(LNotEqual(And(SUPP, 0x16), 0x16)) { \And(CTRL,0x1E,CTRL) \}\\/* Do not allow native PME, AER */ \/* Never allow SHPC (no SHPC controller in this system)*/ \And(CTRL,0x10,CTRL) \If(LNotEqual(Arg1,One)) { /* Unknown revision */ \Or(CDW1,0x08,CDW1) \} \\If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \Or(CDW1,0x10,CDW1) \} \\/* Update DWORD3 in the buffer */ \Store(CTRL,CDW3) \Return(Arg3) \- } Else { \
Or(CDW1,4,CDW1) /* Unrecognized UUID */ \Return(Arg3) \- } \
- } // End _OSC
- // 1P NA PCIe2 Device (PCI2) {
@@ -89,17 +132,44 @@ Scope(_SB) Device (RES2) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) })
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (0xf) }
} // Device(PCI2)
- Device (RES2)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x2) // Unique ID
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)- }
- }
- Device (R1NA) // reserve 1p NA ECAM resource
- {
- Name (_HID, "PNP0C02") // Motherboard reserved resource
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87]- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)- }
- }
- // 1p NB PCIe0 Device (PCI4) {
@@ -149,10 +219,9 @@ Scope(_SB) Device (RES4) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -166,12 +235,38 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) }
} // Device(PCI4)
- Device (RES4)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x4) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a0090000, // Min Base Address0x8a009ffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
// 1P NB PCI1 Device (PCI5) @@ -222,10 +317,9 @@ Scope(_SB) Device (RES5) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -239,11 +333,37 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI5)
- Device (RES5)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x5) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a0200000, // Min Base Address0x8a020ffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
// 1P NB PCIe2 Device (PCI6) @@ -294,10 +414,9 @@ Scope(_SB) Device (RES6) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -311,11 +430,37 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI6)
- Device (RES6)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x6) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a00a0000, // Min Base Address0x8a00affff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- } // 1P NB PCIe3 Device (PCI7) {
@@ -365,10 +510,9 @@ Scope(_SB) Device (RES7) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -382,11 +526,100 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI7)
- Device (RES7)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x7) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a00b0000, // Min Base Address0x8a00bffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
- Device (R1NB) // reserve 1p NB ECAM resource
- {
- Name (_HID, "PNP0C02") // Motherboard reserved resource
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //ECAM space for [bus 88-8f]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a8800000, // Min Base Address0x8a8ffffff, // Max Base Address0x0, // Translate0x800000 // Length)QwordMemory ( //ECAM space for [bus 0-7]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8b0000000, // Min Base Address0x8b07fffff, // Max Base Address0x0, // Translate0x800000 // Length)QwordMemory ( //ECAM space for [bus c0-c7]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8ac000000, // Min Base Address0x8ac7fffff, // Max Base Address0x0, // Translate0x800000 // Length)QwordMemory ( //ECAM space for [bus 90-97]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8b9000000, // Min Base Address0x8b97fffff, // Max Base Address0x0, // Translate0x800000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- } // 2P NA PCIe2 Device (PCIa) {
@@ -436,10 +669,9 @@ Scope(_SB) Device (RESa) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -453,11 +685,61 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (0xf) } } // Device(PCIa)
- Device (RESa)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0xa) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x600a00a0000, // Min Base Address0x600a00affff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)- }
- }
- Device (R2NA) //reserve for 2p NA ecam resource
- {
- Name (_HID, "PNP0C02") // Motherboard reserved resource
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //ECAM space for [bus 10-1f]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x64001000000, // Min Base Address0x64001ffffff, // Max Base Address0x0, // Translate0x1000000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)- }
- } // 2P NB PCIe0 Device (PCIc) {
@@ -507,10 +789,9 @@ Scope(_SB) Device (RESc) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -524,12 +805,38 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCIc)
- Device (RESc)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0xc) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x700a0090000, // Min Base Address0x700a009ffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- } //2P NB PCIe1 Device (PCId) {
@@ -579,10 +886,9 @@ Scope(_SB) Device (RESd) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -596,10 +902,73 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCId)
- Device (RESd)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0xd) // Unique ID
- Name (_CRS, ResourceTemplate (){ //host bridge register space
QwordMemory (ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x700a0200000, // Min Base Address0x700a020ffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
- Device (R2NB) //reserve for 2p NB ecam resource
- {
- Name (_HID, "PNP0C02") // Motherboard reserved resource
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //ECAM space for [bus 20-2f]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x74002000000, // Min Base Address0x74002ffffff, // Max Base Address0x0, // Translate0x1000000 // Length)QwordMemory ( //ECAM space for [bus 30-3f]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x78003000000, // Min Base Address0x78003ffffff, // Max Base Address0x0, // Translate0x1000000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
} -- 1.9.1
On Sat, Apr 01, 2017 at 07:29:16PM +0800, Chenhui Sun wrote:
As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx).
- add _OSC support
- put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver.
- add reserved ecam resource
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Pushed.
.../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 399 ++++++++++++++++++++- 1 file changed, 384 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index f9b4722..79267e5 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -40,6 +40,49 @@ Scope(_SB) } } +/*
- See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
+*/ +#define PCI_OSC_SUPPORT() \
- Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
- Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
- Method(_OSC,4) { \
- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
/* Create DWord-adressable fields from the Capabilities Buffer */ \CreateDWordField(Arg3,0,CDW1) \CreateDWordField(Arg3,4,CDW2) \CreateDWordField(Arg3,8,CDW3) \/* Save Capabilities DWord2 & 3 */ \Store(CDW2,SUPP) \Store(CDW3,CTRL) \/* Only allow native hot plug control if OS supports: */ \/* ASPM */ \/* Clock PM */ \/* MSI/MSI-X */ \If(LNotEqual(And(SUPP, 0x16), 0x16)) { \And(CTRL,0x1E,CTRL) \}\\/* Do not allow native PME, AER */ \/* Never allow SHPC (no SHPC controller in this system)*/ \And(CTRL,0x10,CTRL) \If(LNotEqual(Arg1,One)) { /* Unknown revision */ \Or(CDW1,0x08,CDW1) \} \\If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \Or(CDW1,0x10,CDW1) \} \\/* Update DWORD3 in the buffer */ \Store(CTRL,CDW3) \Return(Arg3) \- } Else { \
Or(CDW1,4,CDW1) /* Unrecognized UUID */ \Return(Arg3) \- } \
- } // End _OSC
- // 1P NA PCIe2 Device (PCI2) {
@@ -89,17 +132,44 @@ Scope(_SB) Device (RES2) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) })
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (0xf) }
} // Device(PCI2)
- Device (RES2)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x2) // Unique ID
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)- }
- }
- Device (R1NA) // reserve 1p NA ECAM resource
- {
- Name (_HID, "PNP0C02") // Motherboard reserved resource
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87]- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)- }
- }
- // 1p NB PCIe0 Device (PCI4) {
@@ -149,10 +219,9 @@ Scope(_SB) Device (RES4) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -166,12 +235,38 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) }
} // Device(PCI4)
- Device (RES4)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x4) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a0090000, // Min Base Address0x8a009ffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
// 1P NB PCI1 Device (PCI5) @@ -222,10 +317,9 @@ Scope(_SB) Device (RES5) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -239,11 +333,37 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI5)
- Device (RES5)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x5) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a0200000, // Min Base Address0x8a020ffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
// 1P NB PCIe2 Device (PCI6) @@ -294,10 +414,9 @@ Scope(_SB) Device (RES6) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -311,11 +430,37 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI6)
- Device (RES6)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x6) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a00a0000, // Min Base Address0x8a00affff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- } // 1P NB PCIe3 Device (PCI7) {
@@ -365,10 +510,9 @@ Scope(_SB) Device (RES7) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -382,11 +526,100 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCI7)
- Device (RES7)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x7) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a00b0000, // Min Base Address0x8a00bffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
- Device (R1NB) // reserve 1p NB ECAM resource
- {
- Name (_HID, "PNP0C02") // Motherboard reserved resource
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //ECAM space for [bus 88-8f]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8a8800000, // Min Base Address0x8a8ffffff, // Max Base Address0x0, // Translate0x800000 // Length)QwordMemory ( //ECAM space for [bus 0-7]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8b0000000, // Min Base Address0x8b07fffff, // Max Base Address0x0, // Translate0x800000 // Length)QwordMemory ( //ECAM space for [bus c0-c7]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8ac000000, // Min Base Address0x8ac7fffff, // Max Base Address0x0, // Translate0x800000 // Length)QwordMemory ( //ECAM space for [bus 90-97]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x8b9000000, // Min Base Address0x8b97fffff, // Max Base Address0x0, // Translate0x800000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- } // 2P NA PCIe2 Device (PCIa) {
@@ -436,10 +669,9 @@ Scope(_SB) Device (RESa) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -453,11 +685,61 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (0xf) } } // Device(PCIa)
- Device (RESa)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0xa) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x600a00a0000, // Min Base Address0x600a00affff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)- }
- }
- Device (R2NA) //reserve for 2p NA ecam resource
- {
- Name (_HID, "PNP0C02") // Motherboard reserved resource
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //ECAM space for [bus 10-1f]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x64001000000, // Min Base Address0x64001ffffff, // Max Base Address0x0, // Translate0x1000000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)- }
- } // 2P NB PCIe0 Device (PCIc) {
@@ -507,10 +789,9 @@ Scope(_SB) Device (RESc) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -524,12 +805,38 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCIc)
- Device (RESc)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0xc) // Unique ID
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //host bridge register spaceResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x700a0090000, // Min Base Address0x700a009ffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- } //2P NB PCIe1 Device (PCId) {
@@ -579,10 +886,9 @@ Scope(_SB) Device (RESd) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ QwordMemory (ResourceProducer,
ResourceConsumer, PosDecode, MinFixed, MaxFixed,@@ -596,10 +902,73 @@ Scope(_SB) ) }) }
- PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCId)
- Device (RESd)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0xd) // Unique ID
- Name (_CRS, ResourceTemplate (){ //host bridge register space
QwordMemory (ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x700a0200000, // Min Base Address0x700a020ffff, // Max Base Address0x0, // Translate0x10000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
- Device (R2NB) //reserve for 2p NB ecam resource
- {
- Name (_HID, "PNP0C02") // Motherboard reserved resource
- Name (_CRS, ResourceTemplate (){
QwordMemory ( //ECAM space for [bus 20-2f]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x74002000000, // Min Base Address0x74002ffffff, // Max Base Address0x0, // Translate0x1000000 // Length)QwordMemory ( //ECAM space for [bus 30-3f]ResourceConsumer,PosDecode,MinFixed,MaxFixed,NonCacheable,ReadWrite,0x0, // Granularity0x78003000000, // Min Base Address0x78003ffffff, // Max Base Address0x0, // Translate0x1000000 // Length)- })
- Method (_STA, 0x0, NotSerialized)
- {
Return (RBYV())- }
- }
} -- 1.9.1
As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx).
1. add _OSC support 2. put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver. 3. add reserved ecam resource
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 159 ++++++++++++--------- 1 file changed, 89 insertions(+), 70 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl index 573c0a3..5b01345 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl @@ -17,12 +17,55 @@ **/
//#include "ArmPlatform.h" +/* + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 +*/ +#define PCI_OSC_SUPPORT() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Do not allow native PME, AER */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x10,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + Scope(_SB) { // PCIe Root bus Device (PCI0) { - Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 0) // Segment of this Root complex Name(_BBN, 0) // Base Bus Number @@ -65,6 +108,7 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) + PCI_OSC_SUPPORT()
Device (RES0) { @@ -74,34 +118,22 @@ Scope(_SB) }) }
- OperationRegion(SCTR, SystemMemory, 0xa009131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } } // Device(PCI0)
+ Device (RES0) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x0) // Unique ID + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000) + }) + } + // PCIe Root bus Device (PCI1) { - Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 1) // Segment of this Root complex Name(_BBN, 0xe0) // Base Bus Number @@ -144,44 +176,33 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) + PCI_OSC_SUPPORT()
Device (RES1) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x1) // Unique ID Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) }) }
- OperationRegion(SCTR, SystemMemory, 0xa020131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
- switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } } // Device(PCI1)
+ Device (RES1) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) + }) + } + // PCIe Root bus Device (PCI2) { - Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex Name(_BBN, 0x80) // Base Bus Number @@ -224,6 +245,7 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) + PCI_OSC_SUPPORT()
Device (RES2) { @@ -233,29 +255,26 @@ Scope(_SB) }) }
- OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) - { - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } } // Device(PCI2) + + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x2) // Unique ID + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) + }) + } + + Device (RESP) //reserve for ecam resource + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xb0000000, 0x2000000) //ECAM space for PCI0 [bus 00-1f] + Memory32Fixed (ReadWrite, 0xbe000000, 0x2000000) //ECAM space for PCI1 [bus e0-ff] + Memory32Fixed (ReadWrite, 0xa8000000, 0x2000000) //ECAM space for PCI2 [bus 80-9f] + }) + } }
On Sat, Apr 01, 2017 at 07:29:17PM +0800, Chenhui Sun wrote:
As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx).
- add _OSC support
- put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver.
- add reserved ecam resource
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
Thanks much easier to read without indentation changes.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 159 ++++++++++++--------- 1 file changed, 89 insertions(+), 70 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl index 573c0a3..5b01345 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl @@ -17,12 +17,55 @@ **/ //#include "ArmPlatform.h" +/*
- See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
+*/ +#define PCI_OSC_SUPPORT() \
- Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
- Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
- Method(_OSC,4) { \
- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
/* Create DWord-adressable fields from the Capabilities Buffer */ \CreateDWordField(Arg3,0,CDW1) \CreateDWordField(Arg3,4,CDW2) \CreateDWordField(Arg3,8,CDW3) \/* Save Capabilities DWord2 & 3 */ \Store(CDW2,SUPP) \Store(CDW3,CTRL) \/* Only allow native hot plug control if OS supports: */ \/* ASPM */ \/* Clock PM */ \/* MSI/MSI-X */ \If(LNotEqual(And(SUPP, 0x16), 0x16)) { \And(CTRL,0x1E,CTRL) \}\\/* Do not allow native PME, AER */ \/* Never allow SHPC (no SHPC controller in this system)*/ \And(CTRL,0x10,CTRL) \If(LNotEqual(Arg1,One)) { /* Unknown revision */ \Or(CDW1,0x08,CDW1) \} \\If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \Or(CDW1,0x10,CDW1) \} \\/* Update DWORD3 in the buffer */ \Store(CTRL,CDW3) \Return(Arg3) \- } Else { \
Or(CDW1,4,CDW1) /* Unrecognized UUID */ \Return(Arg3) \- } \
- } // End _OSC
Scope(_SB) { // PCIe Root bus Device (PCI0) {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 0) // Segment of this Root complex Name(_BBN, 0) // Base Bus Number
@@ -65,6 +108,7 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS)
- PCI_OSC_SUPPORT()
Device (RES0) { @@ -74,34 +118,22 @@ Scope(_SB) }) }
- OperationRegion(SCTR, SystemMemory, 0xa009131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- } } // Device(PCI0)
- Device (RES0)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x0) // Unique ID
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)- })
- }
- // PCIe Root bus Device (PCI1) {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 1) // Segment of this Root complex Name(_BBN, 0xe0) // Base Bus Number
@@ -144,44 +176,33 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS)
- PCI_OSC_SUPPORT()
Device (RES1) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resourceName (_UID, 0x1) // Unique ID Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) })
- OperationRegion(SCTR, SystemMemory, 0xa020131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- } } // Device(PCI1)
- Device (RES1)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)- })
- }
- // PCIe Root bus Device (PCI2) {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex Name(_BBN, 0x80) // Base Bus Number
@@ -224,6 +245,7 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS)
- PCI_OSC_SUPPORT()
Device (RES2) { @@ -233,29 +255,26 @@ Scope(_SB) }) }
- OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))){switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- } } // Device(PCI2)
- Device (RES2)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x2) // Unique ID
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)- })
- }
- Device (RESP) //reserve for ecam resource
- {
- Name (_HID, "PNP0C02")
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xb0000000, 0x2000000) //ECAM space for PCI0 [bus 00-1f]Memory32Fixed (ReadWrite, 0xbe000000, 0x2000000) //ECAM space for PCI1 [bus e0-ff]Memory32Fixed (ReadWrite, 0xa8000000, 0x2000000) //ECAM space for PCI2 [bus 80-9f]- })
- }
} -- 1.9.1
On Sat, Apr 01, 2017 at 07:29:17PM +0800, Chenhui Sun wrote:
As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx).
- add _OSC support
- put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver.
- add reserved ecam resource
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Signed-off-by: Chenhui Sun chenhui.sun@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Pushed.
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 159 ++++++++++++--------- 1 file changed, 89 insertions(+), 70 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl index 573c0a3..5b01345 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl @@ -17,12 +17,55 @@ **/ //#include "ArmPlatform.h" +/*
- See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
+*/ +#define PCI_OSC_SUPPORT() \
- Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
- Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
- Method(_OSC,4) { \
- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
/* Create DWord-adressable fields from the Capabilities Buffer */ \CreateDWordField(Arg3,0,CDW1) \CreateDWordField(Arg3,4,CDW2) \CreateDWordField(Arg3,8,CDW3) \/* Save Capabilities DWord2 & 3 */ \Store(CDW2,SUPP) \Store(CDW3,CTRL) \/* Only allow native hot plug control if OS supports: */ \/* ASPM */ \/* Clock PM */ \/* MSI/MSI-X */ \If(LNotEqual(And(SUPP, 0x16), 0x16)) { \And(CTRL,0x1E,CTRL) \}\\/* Do not allow native PME, AER */ \/* Never allow SHPC (no SHPC controller in this system)*/ \And(CTRL,0x10,CTRL) \If(LNotEqual(Arg1,One)) { /* Unknown revision */ \Or(CDW1,0x08,CDW1) \} \\If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \Or(CDW1,0x10,CDW1) \} \\/* Update DWORD3 in the buffer */ \Store(CTRL,CDW3) \Return(Arg3) \- } Else { \
Or(CDW1,4,CDW1) /* Unrecognized UUID */ \Return(Arg3) \- } \
- } // End _OSC
Scope(_SB) { // PCIe Root bus Device (PCI0) {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 0) // Segment of this Root complex Name(_BBN, 0) // Base Bus Number
@@ -65,6 +108,7 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS)
- PCI_OSC_SUPPORT()
Device (RES0) { @@ -74,34 +118,22 @@ Scope(_SB) }) }
- OperationRegion(SCTR, SystemMemory, 0xa009131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- } } // Device(PCI0)
- Device (RES0)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x0) // Unique ID
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)- })
- }
- // PCIe Root bus Device (PCI1) {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 1) // Segment of this Root complex Name(_BBN, 0xe0) // Base Bus Number
@@ -144,44 +176,33 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS)
- PCI_OSC_SUPPORT()
Device (RES1) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resourceName (_UID, 0x1) // Unique ID Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) })
- OperationRegion(SCTR, SystemMemory, 0xa020131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- } } // Device(PCI1)
- Device (RES1)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)- })
- }
- // PCIe Root bus Device (PCI2) {
- Name (_HID, "HISI0080") // PCI Express Root Bridge
- Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex Name(_BBN, 0x80) // Base Bus Number
@@ -224,6 +245,7 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS)
- PCI_OSC_SUPPORT()
Device (RES2) { @@ -233,29 +255,26 @@ Scope(_SB) }) }
- OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4)
- Field(SCTR, AnyAcc, NoLock, Preserve) {
LSTA, 32,- }
- Method(_DSM, 0x4, Serialized) {
If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))){switch(ToInteger(Arg2)){// Function 0: Return LinkStatuscase(0) {Store (0, Local0)Store (LSTA, Local0)Return (Local0)}default {}}}// If not one of the function identifiers we recognize, then return a buffer// with bit 0 set to 0 indicating no functions supported.return(Buffer(){0})- } } // Device(PCI2)
- Device (RES2)
- {
- Name (_HID, "HISI0081") // HiSi PCIe RC config base address
- Name (_CID, "PNP0C02") // Motherboard reserved resource
- Name (_UID, 0x2) // Unique ID
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)- })
- }
- Device (RESP) //reserve for ecam resource
- {
- Name (_HID, "PNP0C02")
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xb0000000, 0x2000000) //ECAM space for PCI0 [bus 00-1f]Memory32Fixed (ReadWrite, 0xbe000000, 0x2000000) //ECAM space for PCI1 [bus e0-ff]Memory32Fixed (ReadWrite, 0xa8000000, 0x2000000) //ECAM space for PCI2 [bus 80-9f]- })
- }
} -- 1.9.1
SCT test report: "BS.GetNextMonotonicCount - GetNextMonotonicCount() gets the high 32-bit after reset at EFI_TPL_APPLICATION."
Reference 《UEFI Spec 2.6》chapter 7.5.2: “The GetNextHighMonotonicCount() function returns the next high 32 bits of the platform’s monotonic counter. The platform’s monotonic counter is comprised of two 32-bit quantities: the high 32 bits and the low 32 bits. During boot service time the low 32-bit value is volatile: it is reset to zero on every system reset and is increased by 1 on every call to GetNextMonotonicCount(). The high 32-bit value is nonvolatile and is increased by 1 whenever the system resets, whenever GetNextHighMonotonicCount() is called, or whenever the low 32-bit count (returned by GetNextMonoticCount()) overflows.”
In EmbeddedMonotonicCounter.inf driver, The high 32-bit value is nonvolatile and is increased by 1 whenever the system resets, but When GetNextHighMonotonicCount() is called, or whenever the low 32-bit count (returned by GetNextMonoticCount()) overflows don’t increased by 1.
So Monotonic Driver is switched from EmbeddedPkg to MdeModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun chenhui.sun@linaro.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com --- Platforms/Hisilicon/D03/D03.dsc | 1 - Platforms/Hisilicon/D03/D03.fdf | 2 +- Platforms/Hisilicon/D05/D05.dsc | 1 - Platforms/Hisilicon/D05/D05.fdf | 2 +- 4 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 9c73494..ca6295e 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -372,7 +372,6 @@ } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 3302ec9..3102f94 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -167,7 +167,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 2877da0..c1f4dfd 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -492,7 +492,6 @@ } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf index bdfb211..5a646f3 100644 --- a/Platforms/Hisilicon/D05/D05.fdf +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -171,7 +171,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
On Sat, Apr 01, 2017 at 07:29:18PM +0800, Chenhui Sun wrote:
SCT test report: "BS.GetNextMonotonicCount - GetNextMonotonicCount() gets the high 32-bit after reset at EFI_TPL_APPLICATION."
Reference 《UEFI Spec 2.6》chapter 7.5.2: “The GetNextHighMonotonicCount() function returns the next high 32 bits of the platform’s monotonic counter. The platform’s monotonic counter is comprised of two 32-bit quantities: the high 32 bits and the low 32 bits. During boot service time the low 32-bit value is volatile: it is reset to zero on every system reset and is increased by 1 on every call to GetNextMonotonicCount(). The high 32-bit value is nonvolatile and is increased by 1 whenever the system resets, whenever GetNextHighMonotonicCount() is called, or whenever the low 32-bit count (returned by GetNextMonoticCount()) overflows.”
In EmbeddedMonotonicCounter.inf driver, The high 32-bit value is nonvolatile and is increased by 1 whenever the system resets, but When GetNextHighMonotonicCount() is called, or whenever the low 32-bit count (returned by GetNextMonoticCount()) overflows don’t increased by 1.
So Monotonic Driver is switched from EmbeddedPkg to MdeModulePkg.
Much better, thanks!
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun chenhui.sun@linaro.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Pushed as 04f95ed263.
Platforms/Hisilicon/D03/D03.dsc | 1 - Platforms/Hisilicon/D03/D03.fdf | 2 +- Platforms/Hisilicon/D05/D05.dsc | 1 - Platforms/Hisilicon/D05/D05.fdf | 2 +- 4 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 9c73494..ca6295e 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -372,7 +372,6 @@ } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 3302ec9..3102f94 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -167,7 +167,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 2877da0..c1f4dfd 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -492,7 +492,6 @@ } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf index bdfb211..5a646f3 100644 --- a/Platforms/Hisilicon/D05/D05.fdf +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -171,7 +171,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf -- 1.9.1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org --- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 20 ++-- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 39 +++---- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 30 +++--- .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 120 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 2 +- 6 files changed, 110 insertions(+), 109 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc index ed47a44..7e5c8ef 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc @@ -11,7 +11,7 @@ #include <IndustryStandard/Acpi.h> #include "Hi1610Platform.h"
-#define ACPI_5_0_MCFG_VERSION 0x1 +#define ACPI_6_1_MCFG_VERSION 0x1
#pragma pack(1) typedef struct @@ -21,28 +21,28 @@ typedef struct UINT8 ucStartBusNum; UINT8 ucEndBusNum; UINT32 Reserved2; -}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; +}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE;
typedef struct { EFI_ACPI_DESCRIPTION_HEADER Header; UINT64 Reserved1; -}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; +}EFI_ACPI_6_1_MCFG_TABLE_CONFIG;
typedef struct { - EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3]; -}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[3]; +}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; #pragma pack()
-EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { { { - EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - ACPI_5_0_MCFG_VERSION, + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_6_1_MCFG_VERSION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID, diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc index 72cc66c..d5bc299 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc @@ -19,15 +19,15 @@
#include <IndustryStandard/Acpi.h>
-EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length +EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length 0xA152, // UINT32 HardwareSignature 0, // UINT32 FirmwareWakingVector 0, // UINT32 GlobalLock 0, // UINT32 Flags 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc index 5307041..025b42c 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc @@ -22,16 +22,16 @@ #include <Library/AcpiLib.h> #include <IndustryStandard/Acpi.h>
-EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { ARM_ACPI_HEADER ( - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION ), 0, // UINT32 FirmwareCtrl 0, // UINT32 Dsdt EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile 0, // UINT16 SciInt 0, // UINT32 SmiCmd 0, // UINT8 AcpiEnable @@ -65,23 +65,24 @@ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 0, // UINT8 Century 0, // UINT16 IaPcBootArch 0, // UINT8 Reserved1 - EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue - EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 Hypervisor Vendor Identify };
// diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc index 922f5c3..4c1050a 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -23,9 +23,9 @@ #include <Library/PcdLib.h> #include <IndustryStandard/Acpi.h>
-#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT #define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 -#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE #define GTDT_GLOBAL_FLAGS_LEVEL 0
// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer @@ -36,9 +36,9 @@ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF #endif
-#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE #define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY #define GTDT_TIMER_ACTIVE_HIGH 0
#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) @@ -46,18 +46,18 @@ #pragma pack (1)
typedef struct { - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT]; -} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES;
#pragma pack ()
-EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress 0, // UINT32 Reserved @@ -72,14 +72,14 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress #ifdef notyet PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), 0, 0, 0, 0), - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) 0, 0, 0, 0) } #else /* !notyet */ diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc index 7bebe8f..f302dd6 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc @@ -37,20 +37,20 @@ #pragma pack (1)
typedef struct { - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1]; -} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { { ARM_ACPI_HEADER ( - EFI_ACPI_1_0_APIC_SIGNATURE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // // MADT specific fields @@ -59,65 +59,65 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 0, // Flags }, { - // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, // GsivId, GicRBase, Mpidr) // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of // ACPI v5.1). // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0), },
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), { - EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000), + EFI_ACPI_6_1_GIC_ITS_INIT(0,0xC6000000), } };
diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h index 5a810ec..0e65b1f 100644 --- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h @@ -35,7 +35,7 @@ #define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ { \ - 3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ + 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ ACPIProcessorUID, Flags, ClockDomain \ }
On Sat, Apr 01, 2017 at 07:29:19PM +0800, Chenhui Sun wrote:
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
Thanks - for D02, D03 and D05 platforms: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Pushed as 04f95ed263..b689c9d0a6.
.../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 20 ++-- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 39 +++---- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 30 +++--- .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 120 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 2 +- 6 files changed, 110 insertions(+), 109 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc index ed47a44..7e5c8ef 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc @@ -11,7 +11,7 @@ #include <IndustryStandard/Acpi.h> #include "Hi1610Platform.h" -#define ACPI_5_0_MCFG_VERSION 0x1 +#define ACPI_6_1_MCFG_VERSION 0x1 #pragma pack(1) typedef struct @@ -21,28 +21,28 @@ typedef struct UINT8 ucStartBusNum; UINT8 ucEndBusNum; UINT32 Reserved2; -}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; +}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE; typedef struct { EFI_ACPI_DESCRIPTION_HEADER Header; UINT64 Reserved1; -}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; +}EFI_ACPI_6_1_MCFG_TABLE_CONFIG; typedef struct {
- EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
- EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3];
-}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
- EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
- EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[3];
+}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; #pragma pack() -EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { { {
EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),ACPI_5_0_MCFG_VERSION,
EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),ACPI_6_1_MCFG_VERSION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID,diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc index 72cc66c..d5bc299 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc @@ -19,15 +19,15 @@ #include <IndustryStandard/Acpi.h> -EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
- sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
+EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
- EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
- sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length 0xA152, // UINT32 HardwareSignature 0, // UINT32 FirmwareWakingVector 0, // UINT32 GlobalLock 0, // UINT32 Flags 0, // UINT64 XFirmwareWakingVector
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
- EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc index 5307041..025b42c 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc @@ -22,16 +22,16 @@ #include <Library/AcpiLib.h> #include <IndustryStandard/Acpi.h> -EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { ARM_ACPI_HEADER (
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION ), 0, // UINT32 FirmwareCtrl 0, // UINT32 Dsdt EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
- EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
- EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile 0, // UINT16 SciInt 0, // UINT32 SmiCmd 0, // UINT8 AcpiEnable
@@ -65,23 +65,24 @@ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 0, // UINT8 Century 0, // UINT16 IaPcBootArch 0, // UINT8 Reserved1
- EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
- EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue
- EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
- EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
- NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg
- NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
- 0 // UINT64 Hypervisor Vendor Identify
}; // diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc index 922f5c3..4c1050a 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -23,9 +23,9 @@ #include <Library/PcdLib.h> #include <IndustryStandard/Acpi.h> -#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT #define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 -#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE #define GTDT_GLOBAL_FLAGS_LEVEL 0 // Note: We could have a build flag that switches between memory mapped/non-memory mapped timer @@ -36,9 +36,9 @@ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF #endif -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE #define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY #define GTDT_TIMER_ACTIVE_HIGH 0 #define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) @@ -46,18 +46,18 @@ #pragma pack (1) typedef struct {
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
- EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT];
-} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
- EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
- EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT];
+} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; #pragma pack () -EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER(
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES,EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES,EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION@@ -72,14 +72,14 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress #ifdef notyet PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
- sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
- sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, {
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
- EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), 0, 0, 0, 0),
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
//FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
- EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
//FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) 0, 0, 0, 0)#else /* !notyet */ diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc index 7bebe8f..f302dd6 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc @@ -37,20 +37,20 @@ #pragma pack (1) typedef struct {
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16];
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1];
-} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16];
- EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1];
+} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; #pragma pack () -EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { { ARM_ACPI_HEADER (
EFI_ACPI_1_0_APIC_SIGNATURE,EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE,EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION@@ -59,65 +59,65 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 0, // Flags }, {
- // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
- // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, // GsivId, GicRBase, Mpidr) // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of // ACPI v5.1). // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */),- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */),
- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0),- EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0),
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4),
- EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), {
- EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000),
- EFI_ACPI_6_1_GIC_ITS_INIT(0,0xC6000000), }
}; diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h index 5a810ec..0e65b1f 100644 --- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h @@ -35,7 +35,7 @@ #define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ { \
- 3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \
- 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ ACPIProcessorUID, Flags, ClockDomain \ }
1.9.1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 16 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 152 ++++---- Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 42 +- .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 424 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 26 +- 9 files changed, 358 insertions(+), 353 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc index bdf42c0..b47cfec 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -40,7 +40,7 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { { { - EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, sizeof (EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), MCFG_VERSION, 0x00, // Checksum will be updated at runtime diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc index 89cc4a9..0845d66 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc @@ -19,25 +19,25 @@ #pragma pack(1) typedef struct { UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; -} EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; +} EFI_ACPI_6_1_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
typedef struct { - EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; - EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; + EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; + EFI_ACPI_6_1_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
-} EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE; +} EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE; #pragma pack()
// // System Locality Information Table // Please modify all values in Slit.h only. // -EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { +EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { { { - EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE), - EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, + EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE), + EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID, diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc index e1c26c9..0cda870 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc @@ -25,7 +25,7 @@ #define SPCR_FLOW_CONTROL_NONE 0
STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { - ARM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), // UINT8 InterfaceType; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc index 00c2015..b448a29 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc @@ -24,9 +24,9 @@ // EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = { { - {EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + {EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE), - EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, + EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID, @@ -43,83 +43,83 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = { // Memory Affinity // { - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), },
{ - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63 }, };
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc index 2908b24..a5e2e7d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc @@ -19,15 +19,15 @@
#include <IndustryStandard/Acpi.h>
-EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length +EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length 0xA152, // UINT32 HardwareSignature 0, // UINT32 FirmwareWakingVector 0, // UINT32 GlobalLock 0, // UINT32 Flags 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc index 152410b..67fa4d6 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc @@ -22,16 +22,16 @@ #include <Library/AcpiLib.h> #include <IndustryStandard/Acpi.h>
-EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { ARM_ACPI_HEADER ( - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION ), 0, // UINT32 FirmwareCtrl 0, // UINT32 Dsdt EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile 0, // UINT16 SciInt 0, // UINT32 SmiCmd 0, // UINT8 AcpiEnable @@ -65,23 +65,24 @@ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 0, // UINT8 Century 0, // UINT16 IaPcBootArch 0, // UINT8 Reserved1 - EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue - EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 Hypervisor Vendor Identify };
// diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc index b472828..16e2c6a 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc @@ -22,43 +22,31 @@ #include <Library/PcdLib.h> #include "Hi1616Platform.h"
-#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT -#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 -#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE -#define GTDT_GLOBAL_FLAGS_LEVEL 0 - -// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer -#ifdef SYSTEM_TIMER_BASE_ADDRESS - #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) -#else - #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) - #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF -#endif - -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE #define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY #define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
#pragma pack (1)
typedef struct { - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1616_WATCHDOG_COUNT]; -} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1616_WATCHDOG_COUNT]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES;
#pragma pack ()
-EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), - SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0xFFFFFFFFFFFFFFFF, // UINT64 CntControl Base PhysicalAddress 0, // UINT32 Reserved FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags @@ -71,14 +59,14 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress #ifdef notyet PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), 0, 0, 0, 0), - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) 0, 0, 0, 0) } #else /* !notyet */ diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc index b83c221..169ee72 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc @@ -40,20 +40,20 @@ #pragma pack (1)
typedef struct { - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[64]; - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[8]; -} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[64]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { { ARM_ACPI_HEADER ( - EFI_ACPI_1_0_APIC_SIGNATURE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // // MADT specific fields @@ -62,216 +62,216 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 0, // Flags }, { - // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, // GsivId, GicRBase, Mpidr) // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of - // ACPI v5.1). + // ACPI v6.1). // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 16, 16, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 17, 17, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 18, 18, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 19, 19, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 21, 21, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 22, 22, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 23, 23, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x2C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 24, 24, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x300000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 25, 25, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 26, 26, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x380000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 27, 27, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x3C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x400000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 29, 29, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x440000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 30, 30, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x480000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 31, 31, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x4C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 32, 32, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 33, 33, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 34, 34, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 35, 35, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 37, 37, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 38, 38, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 39, 39, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 40, 40, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 41, 41, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 42, 42, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 43, 43, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 45, 45, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 46, 46, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 47, 47, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 48, 48, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 49, 49, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 50, 50, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 51, 51, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 53, 53, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 54, 54, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 55, 55, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x2C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 56, 56, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x300000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 57, 57, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 58, 58, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x380000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 59, 59, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x3C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x400000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 61, 61, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x440000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 62, 62, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x480000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 63, 63, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x4C0000 /* GicRBase */), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 16, 16, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 17, 17, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 18, 18, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 19, 19, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 21, 21, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 22, 22, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 23, 23, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x2C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 24, 24, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x300000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 25, 25, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 26, 26, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x380000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 27, 27, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x3C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x400000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 29, 29, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x440000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 30, 30, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x480000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 31, 31, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x4C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 32, 32, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 33, 33, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 34, 34, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 35, 35, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 37, 37, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 38, 38, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 39, 39, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 40, 40, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 41, 41, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 42, 42, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 43, 43, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 45, 45, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 46, 46, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 47, 47, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 48, 48, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 49, 49, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 50, 50, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 51, 51, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 53, 53, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 54, 54, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 55, 55, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x2C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 56, 56, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x300000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 57, 57, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 58, 58, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x380000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 59, 59, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x3C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x400000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 61, 61, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x440000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 62, 62, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x480000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 63, 63, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x4C0000 /* GicRBase */, 0), },
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4), + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4), { - EFI_ACPI_6_0_GIC_ITS_INIT(0,0x4C000000), //peri a - EFI_ACPI_6_0_GIC_ITS_INIT(1,0x6C000000), //peri b - EFI_ACPI_6_0_GIC_ITS_INIT(2,0xC6000000), //dsa a - EFI_ACPI_6_0_GIC_ITS_INIT(3,0x8C6000000), //dsa b - EFI_ACPI_6_0_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a - EFI_ACPI_6_0_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b - EFI_ACPI_6_0_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a - EFI_ACPI_6_0_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b + EFI_ACPI_6_1_GIC_ITS_INIT(0,0x4C000000), //peri a + EFI_ACPI_6_1_GIC_ITS_INIT(1,0x6C000000), //peri b + EFI_ACPI_6_1_GIC_ITS_INIT(2,0xC6000000), //dsa a + EFI_ACPI_6_1_GIC_ITS_INIT(3,0x8C6000000), //dsa b + EFI_ACPI_6_1_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a + EFI_ACPI_6_1_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b + EFI_ACPI_6_1_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a + EFI_ACPI_6_1_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b } };
diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h index 0e65b1f..60f9925 100644 --- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h @@ -19,9 +19,9 @@ #ifndef __ACPI_NEXT_LIB_H__ #define __ACPI_NEXT_LIB_H__
-#define EFI_ACPI_6_0_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ +#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ { \ - EFI_ACPI_6_0_GIC_ITS, sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD\ }
@@ -32,21 +32,37 @@ GicRBase, GicRlength \ }
-#define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ { \ 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ ACPIProcessorUID, Flags, ClockDomain \ }
-#define EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ { \ - 1, sizeof (EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ + 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \ EFI_ACPI_RESERVED_QWORD \ }
+#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \ + GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \ + { \ + EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \ + GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \ + } + +#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \ + { \ + EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicDistHwId, GicDistBase, GicDistVector, GicVersion, \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \ + } + + #pragma pack(1) // // Define the number of each table type.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Signed-off-by: Yi Li phoenix.liyi@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 39 ++++---- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 30 +++--- Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 126 ++++++++++++------------ Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 20 ++-- Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 6 +- 7 files changed, 119 insertions(+), 118 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc index 93b2c90..3a8313a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc @@ -32,7 +32,7 @@
typedef struct { EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; - EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; } EFI_ACPI_DBG2_DDI_STRUCT; @@ -47,7 +47,7 @@ typedef struct { EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { { ARM_ACPI_HEADER( - EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, EFI_ACPI_DEBUG_PORT_2_TABLE, EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION ), @@ -72,10 +72,10 @@ EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { }, { { - EFI_ACPI_6_0_SYSTEM_MEMORY, + EFI_ACPI_6_1_SYSTEM_MEMORY, 32, 0, - EFI_ACPI_6_0_BYTE, + EFI_ACPI_6_1_BYTE, FixedPcdGet64(PcdSerialRegisterBase) } }, diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc index 72cc66c..d5bc299 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc @@ -19,15 +19,15 @@
#include <IndustryStandard/Acpi.h>
-EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length +EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length 0xA152, // UINT32 HardwareSignature 0, // UINT32 FirmwareWakingVector 0, // UINT32 GlobalLock 0, // UINT32 Flags 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc index 5907c65..76b281f 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc @@ -23,16 +23,16 @@ #include <Library/AcpiLib.h> #include <IndustryStandard/Acpi.h>
-EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { ARM_ACPI_HEADER ( - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION ), 0, // UINT32 FirmwareCtrl 0, // UINT32 Dsdt EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile 0, // UINT16 SciInt 0, // UINT32 SmiCmd 0, // UINT8 AcpiEnable @@ -66,23 +66,24 @@ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 0, // UINT8 Century 0, // UINT16 IaPcBootArch 0, // UINT8 Reserved1 - EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue - EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0, // UINT64 Hypervisor Vendor Identify };
// diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc index f677feb..054eb2c 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc @@ -23,9 +23,9 @@ #include <Library/PcdLib.h> #include <IndustryStandard/Acpi.h>
-#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT #define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 -#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE #define GTDT_GLOBAL_FLAGS_LEVEL 0
// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer @@ -36,9 +36,9 @@ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF #endif
-#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE #define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY #define GTDT_TIMER_ACTIVE_HIGH 0
#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) @@ -46,18 +46,18 @@ #pragma pack (1)
typedef struct { - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[PV660_WATCHDOG_COUNT]; -} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[PV660_WATCHDOG_COUNT]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES;
#pragma pack ()
-EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress 0, // UINT32 Reserved @@ -72,14 +72,14 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress #ifdef notyet PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), 0, 0, 0, 0), - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) 0, 0, 0, 0) } #else /* !notyet */ diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc index 4edb95d..d83584a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc @@ -36,20 +36,20 @@ #pragma pack (1)
typedef struct { - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[4]; -} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[4]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { { ARM_ACPI_HEADER ( - EFI_ACPI_1_0_APIC_SIGNATURE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // // MADT specific fields @@ -58,68 +58,68 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 0, // Flags }, { - // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, // GsivId, GicRBase, Mpidr) // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of // ACPI v5.1). // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0), },
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), { - EFI_ACPI_6_0_GIC_ITS_INIT(0,0x8C000000), // pc - EFI_ACPI_6_0_GIC_ITS_INIT(1,0xC6000000), // dsa - EFI_ACPI_6_0_GIC_ITS_INIT(2,0xA3000000), // m3 - EFI_ACPI_6_0_GIC_ITS_INIT(3,0xB7000000) // pcie + EFI_ACPI_6_1_GIC_ITS_INIT(0,0x8C000000), // pc + EFI_ACPI_6_1_GIC_ITS_INIT(1,0xC6000000), // dsa + EFI_ACPI_6_1_GIC_ITS_INIT(2,0xA3000000), // m3 + EFI_ACPI_6_1_GIC_ITS_INIT(3,0xB7000000) // pcie } };
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc index f783534..69b7b38 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc @@ -13,7 +13,7 @@ #include <IndustryStandard/Acpi.h> #include "Pv660Platform.h"
-#define ACPI_5_0_MCFG_VERSION 0x1 +#define ACPI_6_1_MCFG_VERSION 0x1
#pragma pack(1) typedef struct @@ -23,28 +23,28 @@ typedef struct UINT8 ucStartBusNum; UINT8 ucEndBusNum; UINT32 Reserved2; -}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; +}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE;
typedef struct { EFI_ACPI_DESCRIPTION_HEADER Header; UINT64 Reserved1; -}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; +}EFI_ACPI_6_1_MCFG_TABLE_CONFIG;
typedef struct { - EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2]; -}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[2]; +}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; #pragma pack()
-EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { { { - EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - ACPI_5_0_MCFG_VERSION, + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_6_1_MCFG_VERSION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID, diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc index 7eef5f9..5a9ce4a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc @@ -24,7 +24,7 @@ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { //Header; ARM_ACPI_HEADER( - EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION ), @@ -32,10 +32,10 @@ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, //Reserved1[3]; //BaseAddress; { - EFI_ACPI_6_0_SYSTEM_MEMORY, + EFI_ACPI_6_1_SYSTEM_MEMORY, 32, 0, - EFI_ACPI_6_0_BYTE, + EFI_ACPI_6_1_BYTE, FixedPcdGet64(PcdSerialRegisterBase) }, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //InterruptType;
Add num-pins package for Roce driver.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo guoheyi@huawei.com Signed-off-by: Yi Li phoenix.liyi@huawei.com --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl index 9ee9d83..cdf3e57 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl @@ -434,5 +434,12 @@ Scope(_SB) 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, } }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 34} + } + }) } }
On Sat, Apr 01, 2017 at 07:29:22PM +0800, Chenhui Sun wrote:
Add num-pins package for Roce driver.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo guoheyi@huawei.com Signed-off-by: Yi Li phoenix.liyi@huawei.com
Routine usage of _DSD so all fine with me.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl index 9ee9d83..cdf3e57 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl @@ -434,5 +434,12 @@ Scope(_SB) 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, } })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 34}}- }) }
}
1.9.1
On Sat, Apr 01, 2017 at 07:29:22PM +0800, Chenhui Sun wrote:
Add num-pins package for Roce driver.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo guoheyi@huawei.com Signed-off-by: Yi Li phoenix.liyi@huawei.com
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Pushed as e4e13d3ad9.
Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl index 9ee9d83..cdf3e57 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl @@ -434,5 +434,12 @@ Scope(_SB) 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, } })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),Package (){Package () {"num-pins", 34}}- }) }
}
1.9.1
Hi Chenhui,
17.04 release will happen Thursday this week - when will you have time to provide updated versions of the last remaining patches by?
Regards,
Leif
On Sat, Apr 01, 2017 at 07:29:05PM +0800, Chenhui Sun wrote:
Code can also be found in inaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-17.04-03
Mainly include
- fix SCT test fail issue
- fix luvOS test fail issue
- support the compatibility of kernel PCIe driver
- refine the code style according Leif and Graeme's comments
- drop some unnessary and some wrong patchset at v1
Chenhui Sun (6): Hisilicon: disable RC Option Rom Hisilicon: Add reconfig lane number feature Hisilicon/D03/D05: Change Monotonic Drive D03: update acpi tables to ACPI6.1 D05: update acpi tables to ACPI6.1 D02: update acpi tables to ACPI6.1
hensonwang (3): Hisilicon/D05: support the compatibility of kernel PCIe driver Hisilicon/D03: support the compatibility of kernel PCIe driver Hisilicon/D05: add num-pins package for Roce
shaochangliang (2): Hisilicon/UpdateFdtDxe: fix memory overflow issue Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue.
wangyue (6): Hisilicon: Fix ACPI/DSDT table checksum error Hisilicon/D02: fix IORT test issue in luvOS test Hisilicon/D03: Fix IORT test issue in luvOS test Hisilicon/D05: Fix IORT test issue in luvOS test Hisilicon/FlashFvbDxe: Add Reset interface for block IO protocol Hisilicon/RamDisk: Add Reset interface for block IO protocol
Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c | 22 ++ Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 13 + .../Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c | 2 +- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 184 ++++++++- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 + .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 12 +- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 20 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 159 ++++---- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 30 +- .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 120 +++--- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 32 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 16 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 152 ++++---- .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 7 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 399 ++++++++++++++++++- Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 42 +- .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 424 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 28 +- Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 30 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 126 +++--- Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 20 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 6 +- Drivers/Block/ramdisk/ramdisk.c | 13 + Platforms/Hisilicon/D03/D03.dsc | 1 - Platforms/Hisilicon/D03/D03.fdf | 2 +- Platforms/Hisilicon/D05/D05.dsc | 1 - Platforms/Hisilicon/D05/D05.fdf | 2 +- 38 files changed, 1335 insertions(+), 698 deletions(-)
-- 1.9.1
Hi Leif,
I will send out the nessary remaing pathches today, I saw most of these pathes have been reviewed passed, thank you.
I am preparing the other fixing luvos/sct test issue patches and binaries updated pathes,
we think that pathes can be send out after ERP17.04.
Thanks and Regards,
Chenhui
在 2017/4/10 19:36, Leif Lindholm 写道:
Hi Chenhui,
17.04 release will happen Thursday this week - when will you have time to provide updated versions of the last remaining patches by?
Regards,
Leif
On Sat, Apr 01, 2017 at 07:29:05PM +0800, Chenhui Sun wrote:
Code can also be found in inaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-17.04-03
Mainly include
- fix SCT test fail issue
- fix luvOS test fail issue
- support the compatibility of kernel PCIe driver
- refine the code style according Leif and Graeme's comments
- drop some unnessary and some wrong patchset at v1
Chenhui Sun (6): Hisilicon: disable RC Option Rom Hisilicon: Add reconfig lane number feature Hisilicon/D03/D05: Change Monotonic Drive D03: update acpi tables to ACPI6.1 D05: update acpi tables to ACPI6.1 D02: update acpi tables to ACPI6.1
hensonwang (3): Hisilicon/D05: support the compatibility of kernel PCIe driver Hisilicon/D03: support the compatibility of kernel PCIe driver Hisilicon/D05: add num-pins package for Roce
shaochangliang (2): Hisilicon/UpdateFdtDxe: fix memory overflow issue Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue.
wangyue (6): Hisilicon: Fix ACPI/DSDT table checksum error Hisilicon/D02: fix IORT test issue in luvOS test Hisilicon/D03: Fix IORT test issue in luvOS test Hisilicon/D05: Fix IORT test issue in luvOS test Hisilicon/FlashFvbDxe: Add Reset interface for block IO protocol Hisilicon/RamDisk: Add Reset interface for block IO protocol
Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c | 22 ++ Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 13 + .../Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c | 2 +- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 184 ++++++++- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 + .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 12 +- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 20 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 159 ++++---- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 30 +- .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 120 +++--- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 32 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 16 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 152 ++++---- .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 7 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 399 ++++++++++++++++++- Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 42 +- .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 424 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 28 +- Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 30 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 126 +++--- Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 20 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 6 +- Drivers/Block/ramdisk/ramdisk.c | 13 + Platforms/Hisilicon/D03/D03.dsc | 1 - Platforms/Hisilicon/D03/D03.fdf | 2 +- Platforms/Hisilicon/D05/D05.dsc | 1 - Platforms/Hisilicon/D05/D05.fdf | 2 +- 38 files changed, 1335 insertions(+), 698 deletions(-)
-- 1.9.1
-
Chenhui Sun -
graeme.gregory＠linaro.org -
Leif Lindholm