Hi Ard,

2017-04-18 13:24 GMT+02:00 Ard Biesheuvel ard.biesheuvel@linaro.org:

On 14 April 2017 at 22:16, Marcin Wojtas mw@semihalf.com wrote:

...

This patch adds analog parameters configuration for SATA with the values defined during electrical tests of the interface.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com

---

Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 207 ++++++++++++++++++++-- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 148 +++++++++++++--- 2 files changed, 321 insertions(+), 34 deletions(-)

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c index ee3ce99..d1a91b7 100755 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -608,20 +608,203 @@ ComPhySataPhyConfiguration ( STATIC VOID ComPhySataSetAnalogParameters (

• IN EFI_PHYSICAL_ADDRESS HpipeAddr

• IN EFI_PHYSICAL_ADDRESS HpipeAddr,
• IN EFI_PHYSICAL_ADDRESS SdIpAddr

) {

• UINT32 Mask, Data;
• /* Hpipe Generation 1 settings 1 */
• Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |

•     HPIPE_GX_SET1_RX_SELMUPP_MASK |
  

•     HPIPE_GX_SET1_RX_SELMUFI_MASK |
  

•     HPIPE_GX_SET1_RX_SELMUFF_MASK |
  

•     HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
  

• Data = (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |

•     (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, Mask, Data);

Are you missing a negation of mask here?

Indeed, good catch, thanks!

Marcin

...

• /* Hpipe Generation 1 settings 3 */
• Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |

•     HPIPE_GX_SET3_FFE_RES_SEL_MASK |
  

•     HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK |
  

•     HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
  

•     HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
  

• Data = 0xf |

•     (0x2 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data);
• /* Hpipe Generation 2 settings 1 */
• Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |

•     HPIPE_GX_SET1_RX_SELMUPP_MASK |
  

•     HPIPE_GX_SET1_RX_SELMUFI_MASK |
  

•     HPIPE_GX_SET1_RX_SELMUFF_MASK |
  

•     HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
  

• Data = (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |

•     (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET1_REG, ~Mask, Data);
• /* Hpipe Generation 3 settings 1 */
• Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |

•     HPIPE_GX_SET1_RX_SELMUPP_MASK |
  

•     HPIPE_GX_SET1_RX_SELMUFI_MASK |
  

•     HPIPE_GX_SET1_RX_SELMUFF_MASK |
  

•     HPIPE_GX_SET1_RX_DFE_EN_MASK |
  

•     HPIPE_GX_SET1_RX_DIGCK_DIV_MASK |
  

•     HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK;
  

• Data = 0x2 |

•     (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
  

•     (0x3 << HPIPE_GX_SET1_RX_SELMUFI_OFFSET) |
  

•     (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET) |
  

•     (0x2 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
• /* DTL Control */
• Mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK |

•     HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK |
  

•     HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK |
  

•     HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK |
  

•     HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK |
  

•     HPIPE_PWR_CTR_DTL_CLK_MODE_MASK |
  

•     HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
  

• Data = 0x1 |

•     (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) |
  

•     (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) |
  

•     (0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) |
  

•     (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) |
  

•     (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) |
  

•     (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~Mask, Data);
• /* Trigger sampler enable pulse (by toggling the bit) */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
  

•      ~HPIPE_SAMPLER_MASK,
  

•      0x1 << HPIPE_SAMPLER_OFFSET
  

•      );
  

• MmioAnd32 (

•      HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
  

•      ~HPIPE_SAMPLER_MASK
  

•      );
  

• /* VDD Calibration Control 3 */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
  

•      ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
  

•      0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
  

•      );
  

• /* DFE Resolution Control */
• MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
• /* DFE F3-F5 Coefficient Control */
• MmioAnd32 (

•      HpipeAddr + HPIPE_DFE_F3_F5_REG,
  

•      ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
  

•      );
  

• /* Hpipe Generation 3 settings 3 */
• Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |

•     HPIPE_GX_SET3_FFE_RES_SEL_MASK |
  

•     HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK |
  

•     HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
  

•     HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
  

• Data = 0xf |

•     (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
  

•     (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data);
• /* Hpipe Generation 3 settings 4 */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_G3_SET4_REG,
  

•      ~HPIPE_GX_SET4_DFE_RES_MASK,
  

•      0x2 << HPIPE_GX_SET4_DFE_RES_OFFSET
  

•      );
  

• /* Offset Phase Control - force offset and toggle 'valid' bit */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_PHASE_CONTROL_REG,
  

•      ~(HPIPE_OS_PH_OFFSET_MASK | HPIPE_OS_PH_OFFSET_FORCE_MASK),
  

•      0x5c | (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
  

•      );
  

• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_PHASE_CONTROL_REG,
  

•      ~HPIPE_OS_PH_VALID_MASK,
  

•      0x1 << HPIPE_OS_PH_VALID_OFFSET
  

•      );
  

• MmioAnd32 (

•      HpipeAddr + HPIPE_PHASE_CONTROL_REG,
  

•      ~HPIPE_OS_PH_VALID_MASK
  

•      );
  

• /* Set G1 TX amplitude and TX post emphasis value */
• Mask = HPIPE_GX_SET0_TX_AMP_MASK |

•     HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
  

•     HPIPE_GX_SET0_TX_EMPH1_MASK |
  

•     HPIPE_GX_SET0_TX_EMPH1_EN_MASK;
  

• Data = (0x8 << HPIPE_GX_SET0_TX_AMP_OFFSET) |

•     (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data);
• /* Set G2 TX amplitude and TX post emphasis value */
• Mask = HPIPE_GX_SET0_TX_AMP_MASK |

•     HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
  

•     HPIPE_GX_SET0_TX_EMPH1_MASK |
  

•     HPIPE_GX_SET0_TX_EMPH1_EN_MASK;
  

• Data = (0xa << HPIPE_GX_SET0_TX_AMP_OFFSET) |

•     (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
  

•     (0x2 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET0_REG, ~Mask, Data);
• /* Set G3 TX amplitude and TX post emphasis value */
• Mask = HPIPE_GX_SET0_TX_AMP_MASK |

•     HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
  

•     HPIPE_GX_SET0_TX_EMPH1_MASK |
  

•     HPIPE_GX_SET0_TX_EMPH1_EN_MASK |
  

•     HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK |
  

•     HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK;
  

• Data = (0xe << HPIPE_GX_SET0_TX_AMP_OFFSET) |

•     (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
  

•     (0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET) |
  

•     (0x4 << HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET0_REG, ~Mask, Data);
• /* SERDES External Configuration 2 register - enable spread spectrum clock */
• MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK);
• /* DFE reset sequence */

• RegSet (HpipeAddr + HPIPE_PWR_CTR_REG,
• 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK);
• RegSet (HpipeAddr + HPIPE_PWR_CTR_REG,
• 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK);

• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_PWR_CTR_REG,
  

•      ~HPIPE_PWR_CTR_RST_DFE_MASK,
  

•      0x1
  

•      );
  

• MmioAnd32 (

•      HpipeAddr + HPIPE_PWR_CTR_REG,
  

•      ~HPIPE_PWR_CTR_RST_DFE_MASK
  

•      );
  
  

  /* SW reset for interupt logic */

• RegSet (HpipeAddr + HPIPE_PWR_CTR_REG,
• 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK);
• RegSet (HpipeAddr + HPIPE_PWR_CTR_REG,
• 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK);

• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_PWR_CTR_REG,
  

•      ~HPIPE_PWR_CTR_SFT_RST_MASK,
  

•      0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET
  

•      );
  

• MmioAnd32 (

•      HpipeAddr + HPIPE_PWR_CTR_REG,
  

•      ~HPIPE_PWR_CTR_SFT_RST_MASK
  

•      );
  

}

STATIC @@ -738,7 +921,7 @@ ComPhySataPowerUp (

DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));

• ComPhySataSetAnalogParameters (HpipeAddr);

• ComPhySataSetAnalogParameters (HpipeAddr, SdIpAddr);

  DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));

@@ -930,8 +1113,8 @@ ComPhySgmiiPowerUp ( /* Set analog paramters from ETP(HW) - for now use the default data */ DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));

• RegSet (HpipeAddr + HPIPE_G1_SET_0_REG,
• 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);

• RegSet (HpipeAddr + HPIPE_G1_SET0_REG,

• 0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET, HPIPE_GX_SET0_TX_EMPH1_MASK);

  DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h index 24839b2..8418315 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -143,6 +143,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)

+#define SD_EXTERNAL_CONFIG2_REG 0x8 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)

#define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 @@ -176,19 +181,39 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)

-#define HPIPE_G1_SET_0_REG 0x034 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)

-#define HPIPE_G1_SET_1_REG 0x038 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)

-#define HPIPE_G2_SETTINGS_1_REG 0x040 +#define HPIPE_G1_SET0_REG 0x034 +#define HPIPE_G2_SET0_REG 0x03c +#define HPIPE_G3_SET0_REG 0x044 +#define HPIPE_GX_SET0_TX_AMP_OFFSET 1 +#define HPIPE_GX_SET0_TX_AMP_MASK (0x1f << HPIPE_GX_SET0_TX_AMP_OFFSET) +#define HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_GX_SET0_TX_AMP_ADJ_MASK (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) +#define HPIPE_GX_SET0_TX_EMPH1_OFFSET 7 +#define HPIPE_GX_SET0_TX_EMPH1_MASK (0xf << HPIPE_GX_SET0_TX_EMPH1_OFFSET) +#define HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_GX_SET0_TX_EMPH1_EN_MASK (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET) +#define HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET 12 +#define HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK (0x7 << HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET) +#define HPIPE_GX_SET0_TX_SLEW_CTRL_EN_OFFSET 15 +#define HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK (0x1 << HPIPE_GX_SET0_TX_SLEW_CTRL_EN_OFFSET)

+#define HPIPE_G1_SET1_REG 0x038 +#define HPIPE_G2_SET1_REG 0x040 +#define HPIPE_G3_SET1_REG 0x048 +#define HPIPE_GX_SET1_RX_SELMUPI_OFFSET 0 +#define HPIPE_GX_SET1_RX_SELMUPI_MASK (0x7 << HPIPE_GX_SET1_RX_SELMUPI_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUPP_OFFSET 3 +#define HPIPE_GX_SET1_RX_SELMUPP_MASK (0x7 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUFI_OFFSET 6 +#define HPIPE_GX_SET1_RX_SELMUFI_MASK (0x3 << HPIPE_GX_SET1_RX_SELMUFI_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUFF_OFFSET 8 +#define HPIPE_GX_SET1_RX_SELMUFF_MASK (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) +#define HPIPE_GX_SET1_RX_DFE_EN_OFFSET 10 +#define HPIPE_GX_SET1_RX_DFE_EN_MASK (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET) +#define HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_GX_SET1_RX_DIGCK_DIV_MASK (0x3 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET) +#define HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_OFFSET 13 +#define HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK (0x1 << HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_OFFSET)

#define HPIPE_LOOPBACK_REG 0x08c #define HPIPE_LOOPBACK_SEL_OFFSET 1 @@ -210,6 +235,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

#define HPIPE_VTHIMPCAL_CTRL_REG 0x104

+#define HPIPE_VDD_CAL_CTRL_REG 0x114 +#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 +#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)

+#define HPIPE_VDD_CAL_0_REG 0x108 +#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 +#define HPIPE_CAL_VDD_CONT_MODE_MASK (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)

#define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 #define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) @@ -244,11 +277,57 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

#define HPIPE_PLLINTP_REG1 0x150

-#define HPIPE_PWR_CTR_DTL_REG 0x184 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 0x2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)

-#define HPIPE_RX_REG3 0x188 +#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C +#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 +#define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) +#define HPIPE_SAMPLER_OFFSET 12 +#define HPIPE_SAMPLER_MASK (0x1 << HPIPE_SAMPLER_OFFSET)

+#define HPIPE_TX_REG1_REG 0x174 +#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_OFFSET 10 +#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)

+#define HPIPE_PWR_CTR_DTL_REG 0x184 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)

+#define HPIPE_PHASE_CONTROL_REG 0x188 +#define HPIPE_OS_PH_OFFSET_OFFSET 0 +#define HPIPE_OS_PH_OFFSET_MASK (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) +#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 +#define HPIPE_OS_PH_OFFSET_FORCE_MASK (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) +#define HPIPE_OS_PH_VALID_OFFSET 8 +#define HPIPE_OS_PH_VALID_MASK (0x1 << HPIPE_OS_PH_VALID_OFFSET)

+#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 +#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 +#define HPIPE_TRAIN_PAT_NUM_MASK (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)

+#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)

+#define HPIPE_DME_REG 0x228 +#define HPIPE_DME_ETHERNET_MODE_OFFSET 7 +#define HPIPE_DME_ETHERNET_MODE_MASK (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)

+#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 +#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)

#define HPIPE_TX_TRAIN_CTRL_REG 0x26C #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 @@ -267,10 +346,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)

-#define HPIPE_G1_SETTINGS_3_REG 0x440 -#define HPIPE_G1_SETTINGS_4_REG 0x444 -#define HPIPE_G2_SETTINGS_3_REG 0x448 -#define HPIPE_G2_SETTINGS_4_REG 0x44C +#define HPIPE_G1_SET3_REG 0x440 +#define HPIPE_G2_SET3_REG 0x448 +#define HPIPE_G3_SET3_REG 0x450 +#define HPIPE_GX_SET3_FFE_CAP_SEL_OFFSET 0 +#define HPIPE_GX_SET3_FFE_CAP_SEL_MASK (0xf << HPIPE_GX_SET3_FFE_CAP_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_RES_SEL_OFFSET 4 +#define HPIPE_GX_SET3_FFE_RES_SEL_MASK (0x7 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET 7 +#define HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_GX_SET3_FBCK_SEL_OFFSET 9 +#define HPIPE_GX_SET3_FBCK_SEL_MASK (0x1 << HPIPE_GX_SET3_FBCK_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET 12 +#define HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET 14 +#define HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET)

+#define HPIPE_G1_SET4_REG 0x444 +#define HPIPE_G2_SET4_REG 0x44C +#define HPIPE_G3_SET4_REG 0x454 +#define HPIPE_GX_SET4_DFE_RES_OFFSET 8 +#define HPIPE_GX_SET4_DFE_RES_MASK (0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET)

+#define HPIPE_TX_PRESET_INDEX_REG 0x468 +#define HPIPE_TX_PRESET_INDEX_OFFSET 0 +#define HPIPE_TX_PRESET_INDEX_MASK (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)

+#define HPIPE_DFE_CONTROL_REG 0x470 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)

#define HPIPE_DFE_CTRL_28_REG 0x49C

#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7

1.8.3.1

On 14 April 2017 at 22:16, Marcin Wojtas mw@semihalf.com wrote:

This patch adds analog parameters configuration for PCIE with the values defined during electrical tests of the interface.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com

Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org

---

Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 149 +++++++++++++++++++++- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 53 +++++++- 2 files changed, 200 insertions(+), 2 deletions(-)

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c index d1a91b7..1d2140a 100755 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -187,6 +187,10 @@ ComPhyPciePhyConfiguration ( Mask |= HPIPE_MISC_REFCLK_SEL_MASK; Data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; }

• /* Force ICP */

• Mask |= HPIPE_MISC_ICP_FORCE_MASK;

• Data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask);

  if (PcieClk) {

@@ -216,7 +220,9 @@ ComPhyPciePhyConfiguration ( /* Set Maximal PHY Generation Setting (8Gbps) */ Mask = HPIPE_INTERFACE_GEN_MAX_MASK; Data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;

• /* Bypass frame detection and sync detection for RX DATA */
• Mask |= HPIPE_INTERFACE_DET_BYPASS_MASK;
• Data |= 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; /* Set Link Train Mode (Tx training control pins are used) */ Mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; Data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;

@@ -256,6 +262,143 @@ ComPhyPciePhyConfiguration (

STATIC VOID +ComPhyPcieSetAnalogParameters (

• IN EFI_PHYSICAL_ADDRESS HpipeAddr

+) +{

• UINT32 Data, Mask;
• /* Set preset sweep configurations */
• Mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK |

•     HPIPE_TX_NUM_OF_PRESET_MASK |
  

•     HPIPE_TX_SWEEP_PRESET_EN_MASK;
  

• Data = (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) |

•     (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) |
  

•     (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_11_REG, ~Mask, Data);
• /* Tx train start configuration */
• Mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK |

•     HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK |
  

•     HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK |
  

•     HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
  

• Data = (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) |

•     (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~Mask, Data);
• /* Enable Tx train P2P */
• MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD_MASK);
• /* Configure Tx train timeout */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_TX_TRAIN_CTRL_4_REG,
  

•      ~HPIPE_TRX_TRAIN_TIMER_MASK,
  

•      0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET
  

•      );
  

• /* Disable G0/G1/GN1 adaptation */
• MmioAnd32 (

•      HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG,
  

•      ~(HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK | HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
  

•      );
  

• /* Disable DTL frequency loop */
• MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
• /* Configure Generation 3 DFE */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_G3_SET4_REG,
  

•      ~HPIPE_GX_SET4_DFE_RES_MASK,
  

•      0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET
  

•      );
  

• /* Use TX/RX training result for DFE */
• MmioAnd32 (HpipeAddr + HPIPE_DFE_REG0, ~HPIPE_DFE_RES_FORCE_MASK);
• /* Configure initial and final coefficient value for receiver */
• MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
• Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |

•     HPIPE_GX_SET1_RX_SELMUPP_MASK |
  

•     HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK;
  

• Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET);
• MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
• /* Trigger sampler 5us enable pulse */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
  

•      ~HPIPE_SAMPLER_MASK,
  

•      0x1 << HPIPE_SAMPLER_OFFSET
  

•      );
  

• MicroSecondDelay (5);
• MmioAnd32 (

•      HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
  

•      ~HPIPE_SAMPLER_MASK
  

•      );
  

• /* FFE resistor tuning for different bandwidth */
• Mask = HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |

•     HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
  

• Data = (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |

•     (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data);
• /* Pattern lock lost timeout disable */
• MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK);
• /* Configure DFE adaptations */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_CDR_CONTROL_REG,
  

•      ~(HPIPE_CDR_MAX_DFE_ADAPT_1_MASK | HPIPE_CDR_MAX_DFE_ADAPT_0_MASK | HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK),
  

•      0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET
  

•      );
  

• MmioAnd32 (HpipeAddr + HPIPE_DFE_CONTROL_REG, ~HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK);
• /* Hpipe Generation 2 setting 1*/
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_G2_SET1_REG,
  

•      ~(HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK | HPIPE_GX_SET1_RX_SELMUFI_MASK),
  

•      0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET
  

•      );
  

• /* DFE enable */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_G2_SET4_REG,
  

•      ~HPIPE_GX_SET4_DFE_RES_MASK,
  

•      0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET
  

•      );
  

• /* Configure DFE Resolution */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_LANE_CFG4_REG,
  

•      ~HPIPE_LANE_CFG4_DFE_EN_SEL_MASK,
  

•      0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET
  

•      );
  

• /* VDD calibration control */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
  

•      ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
  

•      0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
  

•      );
  

• /* Set PLL Charge-pump Current Control */
• MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK, 0x4);
• /* Set lane rqualization remote setting */
• Mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK |

•     HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK |
  

•     HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
  

• Data = (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) |

•     (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) |
  

•     (0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Data);
• /* Set phy in root complex mode */
• MmioOr32 (HpipeAddr + HPIPE_LANE_EQU_CONFIG_0_REG, HPIPE_CFG_PHY_RC_EP_MASK);

+}

+STATIC +VOID ComPhyPciePhyPowerUp ( IN EFI_PHYSICAL_ADDRESS HpipeAddr ) @@ -312,6 +455,10 @@ ComPhyPciePowerUp (

ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr);

• DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));

• ComPhyPcieSetAnalogParameters (HpipeAddr);

• DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));

  ComPhyPciePhyPowerUp (HpipeAddr);

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h index 8418315..58f1d81 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -174,7 +174,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_DFE_RES_FORCE_OFFSET 15 #define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)

#define HPIPE_DFE_F3_F5_REG 0x028 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 #define HPIPE_DFE_F3_F5_DFE_EN_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) @@ -224,6 +223,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_INTERFACE_REG 0x94 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 #define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 +#define HPIPE_INTERFACE_DET_BYPASS_MASK (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 #define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)

@@ -256,6 +257,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_MISC_REG 0x13C #define HPIPE_MISC_CLK100M_125M_OFFSET 4 #define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) +#define HPIPE_MISC_ICP_FORCE_OFFSET 5 +#define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 #define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) #define HPIPE_MISC_CLK500_EN_OFFSET 7 @@ -337,15 +340,45 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 #define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)

+#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 +#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 +#define HPIPE_TRX_TRAIN_TIMER_MASK (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)

#define HPIPE_PCIE_REG1 0x288 #define HPIPE_PCIE_REG3 0x290

+#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 +#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 +#define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)

#define HPIPE_TX_TRAIN_REG 0x31C #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 #define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)

+#define HPIPE_CDR_CONTROL_REG 0x418 +#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 +#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 +#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)

+#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 +#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 +#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) +#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 +#define HPIPE_TX_NUM_OF_PRESET_MASK (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) +#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 +#define HPIPE_TX_SWEEP_PRESET_EN_MASK (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)

#define HPIPE_G1_SET3_REG 0x440 #define HPIPE_G2_SET3_REG 0x448 #define HPIPE_G3_SET3_REG 0x450 @@ -380,6 +413,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 #define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)

+#define HPIPE_G3_SET5_REG 0x548 +#define HPIPE_GX_SET5_ICP_OFFSET 0 +#define HPIPE_GX_SET5_ICP_MASK (0xf << HPIPE_GX_SET5_ICP_OFFSET)

#define HPIPE_LANE_CONFIG0_REG 0x604 #define HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET 9 #define HPIPE_LANE_CONFIG0_MAX_PLL_MASK (0x1 << HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET) @@ -393,15 +430,29 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_LANE_CFG4_REG 0x620 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 +#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 #define HPIPE_LANE_CFG4_DFE_OVER_MASK (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 #define HPIPE_LANE_CFG4_SSC_CTRL_MASK (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)

+#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C +#define HPIPE_CFG_PHY_RC_EP_OFFSET 12 +#define HPIPE_CFG_PHY_RC_EP_MASK (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)

#define HPIPE_LANE_EQ_CFG1_REG 0x6a0 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 #define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)

+#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)

#define HPIPE_RST_CLK_CTRL_REG 0x704 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0

#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)

1.8.3.1

On 14 April 2017 at 22:16, Marcin Wojtas mw@semihalf.com wrote:

Despite the fact, that SFI and RXAUI modes are present on supported feature list, their configuration was non existent and could not be executed. This patch adds the missing initialization sequences. Because ComPhySgmiiRFUPowerUp routine is common for SGMII, SFI and RXAUI, rename it and reuse for those modes.

Also add an option to use XFI mode (SFI @ 5156 MHz).

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com

Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org

---

Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 464 +++++++++++++++++++++- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 6 +- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 54 ++- 3 files changed, 515 insertions(+), 9 deletions(-)

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c index 1d2140a..a5bceb7 100755 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -1179,7 +1179,7 @@ ComPhySgmiiPhyConfiguration (

STATIC EFI_STATUS -ComPhySgmiiRFUPowerUp ( +ComPhyEthCommonRFUPowerUp ( IN EFI_PHYSICAL_ADDRESS SdIpAddr ) { @@ -1265,7 +1265,460 @@ ComPhySgmiiPowerUp (

DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));

• Status = ComPhySgmiiRFUPowerUp (SdIpAddr);

• Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);
• return Status;

+}

+STATIC +VOID +ComPhySfiRFUConfiguration (

• IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
• IN EFI_PHYSICAL_ADDRESS SdIpAddr

+) +{

• UINT32 Mask, Data;
• MmioAndThenOr32 (

•      ComPhyAddr + COMMON_PHY_CFG1_REG,
  

•      ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK),
  

•      COMMON_PHY_CFG1_PWR_UP_MASK
  

•      );
  

• /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
• Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK |

•     SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK |
  

•     SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK |
  

•     SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK |
  

•     SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK |
  

•     SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
  

• Data = (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) |

•     (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET);
  

• MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data);
• /* Release from hard reset */
• Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |

•     SD_EXTERNAL_CONFIG1_RESET_CORE_MASK |
  

•     SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
  

• Data = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |

•     SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
  

• MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data);
• /* Wait 1ms - until band gap and ref clock are ready */
• MicroSecondDelay (1000);
• MemoryFence ();

+}

+STATIC +VOID +ComPhySfiPhyConfiguration (

• IN EFI_PHYSICAL_ADDRESS HpipeAddr,
• IN UINT32 SfiSpeed

+) +{

• UINT32 Mask, Data;
• /* Set reference clock */
• Mask = HPIPE_MISC_ICP_FORCE_MASK | HPIPE_MISC_REFCLK_SEL_MASK;
• Data = (SfiSpeed == PHY_SPEED_5_15625G) ?
• (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET);
• MmioAndThenOr32 (HpipeAddr + HPIPE_MISC_REG, ~Mask, Data);
• /* Power and PLL Control */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_PWR_PLL_REG,
  

•      ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK),
  

•      0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
  

•      );
  

• /* Loopback register */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_LOOPBACK_REG,
  

•      ~HPIPE_LOOPBACK_SEL_MASK,
  

•      0x1 << HPIPE_LOOPBACK_SEL_OFFSET
  

•      );
  

• /* Rx control 1 */
• MmioOr32 (

•      HpipeAddr + HPIPE_RX_CONTROL_1_REG,
  

•      HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_EN_MASK
  

•      );
  

• /* DTL Control */
• MmioOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
• /* Transmitter/Receiver Speed Divider Force */
• if (SfiSpeed == PHY_SPEED_5_15625G) {
• Mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK |

•       HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK |
  

•       HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK |
  

•       HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
  

• Data = (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) |

•       (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) |
  

•       (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) |
  

•       (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, ~Mask, Data);
• } else {
• MmioOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, HPIPE_TXDIGCK_DIV_FORCE_MASK);
• }

+}

+STATIC +VOID +ComPhySfiSetAnalogParameters (

• IN EFI_PHYSICAL_ADDRESS HpipeAddr,
• IN EFI_PHYSICAL_ADDRESS SdIpAddr,
• IN UINT32 SfiSpeed

+) +{

• UINT32 Mask, Data;
• /* SERDES External Configuration 2 */
• MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
• /* DFE Resolution control */
• MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
• /* Generation 1 setting_0 */
• if (SfiSpeed == PHY_SPEED_5_15625G) {
• Mask = HPIPE_GX_SET0_TX_EMPH1_MASK;
• Data = 0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET;
• } else {
• Mask = HPIPE_GX_SET0_TX_AMP_MASK | HPIPE_GX_SET0_TX_EMPH1_MASK;
• Data = (0x1c << HPIPE_GX_SET0_TX_AMP_OFFSET) | (0xe << HPIPE_GX_SET0_TX_EMPH1_OFFSET);
• }
• MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data);
• /* Generation 1 setting 2 */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_GX_SET2_REG,
  

•      ~HPIPE_GX_SET2_TX_EMPH0_MASK,
  

•      HPIPE_GX_SET2_TX_EMPH0_EN_MASK
  

•      );
  

• /* Transmitter Slew Rate Control register */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_TX_REG1_REG,
  

•      ~(HPIPE_TX_REG1_TX_EMPH_RES_MASK | HPIPE_TX_REG1_SLC_EN_MASK),
  

•      (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) | (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
  

•      );
  

• /* Impedance Calibration Control register */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_CAL_REG1_REG,
  

•      ~(HPIPE_CAL_REG_1_EXT_TXIMP_MASK | HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK),
  

•      (0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) | HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK
  

•      );
  

• /* Generation 1 setting 5 */
• MmioAnd32 (HpipeAddr + HPIPE_G1_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK);
• /* Generation 1 setting 1 */
• if (SfiSpeed == PHY_SPEED_5_15625G) {
• Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK;
• Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET);
• } else {
• Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |

•       HPIPE_GX_SET1_RX_SELMUPP_MASK |
  

•       HPIPE_GX_SET1_RX_SELMUFI_MASK |
  

•       HPIPE_GX_SET1_RX_SELMUFF_MASK |
  

•       HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
  

• Data = 0x2 |

•       (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
  

•       (0x1 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
  

•       (0x3 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
  

• }
• MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data);
• MmioOr32 (HpipeAddr + HPIPE_G1_SET1_REG, HPIPE_GX_SET1_RX_DFE_EN_MASK);
• /* DFE F3-F5 Coefficient Control */
• MmioAnd32 (

•      HpipeAddr + HPIPE_DFE_F3_F5_REG,
  

•      ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
  

•      );
  

• /* Configure Generation 1 setting 4 (DFE) */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_G1_SET4_REG,
  

•      ~HPIPE_GX_SET4_DFE_RES_MASK,
  

•      0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET
  

•      );
  

• /* Generation 1 setting 3 */
• MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK);
• if (SfiSpeed == PHY_SPEED_5_15625G) {
• /* Force FFE (Feed Forward Equalization) to 5G */
• Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |

•       HPIPE_GX_SET3_FFE_RES_SEL_MASK |
  

•       HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK;
  

• Data = 0xf | (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK;
• MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data);
• }
• /* Configure RX training timer */
• MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~HPIPE_RX_TRAIN_TIMER_MASK, 0x13);
• /* Enable TX train peak to peak hold */
• MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD_MASK);
• /* Configure TX preset index */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_TX_PRESET_INDEX_REG,
  

•      ~HPIPE_TX_PRESET_INDEX_MASK,
  

•      0x2 << HPIPE_TX_PRESET_INDEX_OFFSET
  

•      );
  

• /* Disable pattern lock lost timeout */
• MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK);
• /* Configure TX training pattern and TX training 16bit auto */
• MmioOr32 (

•      HpipeAddr + HPIPE_TX_TRAIN_REG,
  

•      HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK | HPIPE_TX_TRAIN_PAT_SEL_MASK
  

•      );
  

• /* Configure training pattern number */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_FRAME_DETECT_CTRL_0_REG,
  

•      ~HPIPE_TRAIN_PAT_NUM_MASK,
  

•      0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET
  

•      );
  

• /* Configure differential manchester encoder to ethernet mode */
• MmioOr32 (HpipeAddr + HPIPE_DME_REG, HPIPE_DME_ETHERNET_MODE_MASK);
• /* Configure VDD Continuous Calibration */
• MmioOr32 (HpipeAddr + HPIPE_VDD_CAL_0_REG, HPIPE_CAL_VDD_CONT_MODE_MASK);
• /* Configure sampler gain */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
  

•      ~HPIPE_RX_SAMPLER_OS_GAIN_MASK,
  

•      0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET
  

•      );
  

• /* Trigger sampler enable pulse (by toggling the bit) */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
  

•      ~HPIPE_SAMPLER_MASK,
  

•      0x1 << HPIPE_SAMPLER_OFFSET
  

•      );
  

• MmioAnd32 (

•      HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
  

•      ~HPIPE_SAMPLER_MASK
  

•      );
  

• /* VDD calibration control */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
  

•      ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
  

•      0x1a << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
  

•      );
  

+}

+STATIC +EFI_STATUS +ComPhySfiPowerUp (

• IN UINT32 Lane,
• IN EFI_PHYSICAL_ADDRESS HpipeBase,
• IN EFI_PHYSICAL_ADDRESS ComPhyBase,
• IN UINT32 SfiSpeed
• )

+{

• EFI_STATUS Status;
• EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
• EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
• EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
• DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
• ComPhySfiRFUConfiguration (ComPhyAddr, SdIpAddr);
• DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
• ComPhySfiPhyConfiguration (HpipeAddr, SfiSpeed);
• DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
• ComPhySfiSetAnalogParameters (HpipeAddr, SdIpAddr, SfiSpeed);
• DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));
• Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);
• return Status;

+}

+STATIC +EFI_STATUS +ComPhyRxauiRFUConfiguration (

• IN UINT32 Lane,
• IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
• IN EFI_PHYSICAL_ADDRESS SdIpAddr

+) +{

• UINT32 Mask, Data;
• MmioAndThenOr32 (

•      ComPhyAddr + COMMON_PHY_CFG1_REG,
  

•      ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK),
  

•      COMMON_PHY_CFG1_PWR_UP_MASK
  

•      );
  

• switch (Lane) {
• case 2:
• case 4:
• MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
• case 3:
• case 5:
• MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
• break;
• default:
• DEBUG ((DEBUG_ERROR, "RXAUI used on invalid lane %d\n", Lane));
• return EFI_INVALID_PARAMETER;
• }
• /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
• Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK |

•     SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK |
  

•     SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK |
  

•     SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK |
  

•     SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK |
  

•     SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK |
  

•     SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
  

• Data = (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) |

•     (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) |
  

•     (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET);
  

• MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data);
• /* Release from hard reset */
• Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |

•     SD_EXTERNAL_CONFIG1_RESET_CORE_MASK |
  

•     SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
  

• Data = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |

•     SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
  

• MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data);
• /* Wait 1ms - until band gap and ref clock are ready */
• MicroSecondDelay (1000);
• MemoryFence ();
• return EFI_SUCCESS;

+}

+STATIC +VOID +ComPhyRxauiPhyConfiguration (

• IN EFI_PHYSICAL_ADDRESS HpipeAddr

+) +{

• /* Set reference clock */
• MmioAnd32 (HpipeAddr + HPIPE_MISC_REG, ~HPIPE_MISC_REFCLK_SEL_MASK);
• /* Power and PLL Control */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_PWR_PLL_REG,
  

•      ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK),
  

•      0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
  

•      );
  

• /* Loopback register */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_LOOPBACK_REG,
  

•      ~HPIPE_LOOPBACK_SEL_MASK,
  

•      0x1 << HPIPE_LOOPBACK_SEL_OFFSET
  

•      );
  

• /* Rx control 1 */
• MmioOr32 (

•      HpipeAddr + HPIPE_RX_CONTROL_1_REG,
  

•      HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_EN_MASK
  

•      );
  

• /* DTL Control */
• MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);

+}

+STATIC +VOID +ComPhyRxauiSetAnalogParameters (

• IN EFI_PHYSICAL_ADDRESS HpipeAddr,
• IN EFI_PHYSICAL_ADDRESS SdIpAddr

+) +{

• UINT32 Mask, Data;
• /* SERDES External Configuration 2 */
• MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
• /* DFE Resolution control */
• MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
• /* Generation 1 setting_0 */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_G1_SET0_REG,
  

•      ~HPIPE_GX_SET0_TX_EMPH1_MASK,
  

•      0xe << HPIPE_GX_SET0_TX_EMPH1_OFFSET
  

•      );
  

• /* Generation 1 setting 1 */
• Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |

•     HPIPE_GX_SET1_RX_SELMUPP_MASK |
  

•     HPIPE_GX_SET1_RX_DFE_EN_MASK;
  

• Data = 0x1 |

•     (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
  

•     (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET);
  

• MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data);
• /* DFE F3-F5 Coefficient Control */
• MmioAnd32 (

•      HpipeAddr + HPIPE_DFE_F3_F5_REG,
  

•      ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
  

•      );
  

• /* Configure Generation 1 setting 4 (DFE) */
• MmioAndThenOr32 (

•      HpipeAddr + HPIPE_G1_SET4_REG,
  

•      ~HPIPE_GX_SET4_DFE_RES_MASK,
  

•      0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET
  

•      );
  

• /* Generation 1 setting 3 */
• MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK);

+}

+STATIC +EFI_STATUS +ComPhyRxauiPowerUp (

• IN UINT32 Lane,
• IN EFI_PHYSICAL_ADDRESS HpipeBase,
• IN EFI_PHYSICAL_ADDRESS ComPhyBase
• )

+{

• EFI_STATUS Status;

• EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);

• EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);

• EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);

• DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));

• Status = ComPhyRxauiRFUConfiguration (Lane, ComPhyAddr, SdIpAddr);

• if (EFI_ERROR(Status)) {

• return Status;

• }

• DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));

• ComPhyRxauiPhyConfiguration (HpipeAddr);

• DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));

• ComPhyRxauiSetAnalogParameters (HpipeAddr, SdIpAddr);

• DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));

• Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);

  return Status;

} @@ -1372,6 +1825,13 @@ ComPhyCp110Init ( Status = ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAddr, ComPhyBaseAddr); break;

• case PHY_TYPE_SFI:

•  Status = ComPhySfiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr, PtrComPhyMap->Speed);
  

•  break;
  

• case PHY_TYPE_RXAUI0:
• case PHY_TYPE_RXAUI1:

•  Status = ComPhyRxauiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);
  

•  break;
  

  default: DEBUG((DEBUG_ERROR, "Unknown SerDes Type, skip initialize SerDes %d\n", Lane));

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c index 88680fc..174f10d 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -42,7 +42,7 @@ CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"};

CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps",

•                            L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps",
  

•                            L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", L"5.156 Gbps",
                             L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"};
  
  

CHIP_COMPHY_CONFIG ChipCfgTbl[] = { @@ -142,9 +142,9 @@ ParseSerdesSpeed ( { UINT32 i; UINT32 ValueTable [] = {0, 1250, 1500, 2500, 3000, 3125,

•                      5000, 6000, 6250, 10310};
  

•                      5000, 5156, 6000, 6250, 10310};
  
  

• for (i = 0; i < 10; i++) {

• for (i = 0; i < PHY_SPEED_MAX; i++) { if (Value == ValueTable[i]) { return i; }

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h index 58f1d81..56bb991 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -80,10 +80,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PHY_SPEED_3G 4 #define PHY_SPEED_3_125G 5 #define PHY_SPEED_5G 6 -#define PHY_SPEED_6G 7 -#define PHY_SPEED_6_25G 8 -#define PHY_SPEED_10_3125G 9 -#define PHY_SPEED_MAX 10 +#define PHY_SPEED_5_15625G 7 +#define PHY_SPEED_6G 8 +#define PHY_SPEED_6_25G 9 +#define PHY_SPEED_10_3125G 10 +#define PHY_SPEED_MAX 11 #define PHY_SPEED_INVALID 0xff

#define PHY_TYPE_UNCONNECTED 0 @@ -132,6 +133,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)

#define SD_EXTERNAL_CONFIG1_REG 0x4 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 @@ -168,6 +171,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)

+#define HPIPE_CAL_REG1_REG 0xc +#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 +#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) +#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 +#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)

#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018

#define HPIPE_DFE_REG0 0x01C @@ -234,6 +243,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)

+#define HPIPE_GX_SET2_REG 0xf4 +#define HPIPE_GX_SET2_TX_EMPH0_OFFSET 0 +#define HPIPE_GX_SET2_TX_EMPH0_MASK (0xf << HPIPE_GX_SET2_TX_EMPH0_OFFSET) +#define HPIPE_GX_SET2_TX_EMPH0_EN_OFFSET 4 +#define HPIPE_GX_SET2_TX_EMPH0_EN_MASK (0x1 << HPIPE_GX_SET2_TX_EMPH0_MASK)

#define HPIPE_VTHIMPCAL_CTRL_REG 0x104

#define HPIPE_VDD_CAL_CTRL_REG 0x114 @@ -280,6 +295,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

#define HPIPE_PLLINTP_REG1 0x150

+#define HPIPE_SPD_DIV_FORCE_REG 0x154 +#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 +#define HPIPE_TXDIGCK_DIV_FORCE_MASK (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)

#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 #define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) @@ -292,6 +319,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 #define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)

+#define HPIPE_TX_REG1_REG 0x174 +#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_OFFSET 10 +#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)

#define HPIPE_PWR_CTR_DTL_REG 0x184 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) @@ -348,6 +381,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_PCIE_REG3 0x290

#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 +#define HPIPE_RX_TRAIN_TIMER_OFFSET 0 +#define HPIPE_RX_TRAIN_TIMER_MASK (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 @@ -362,6 +397,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) +#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 +#define HPIPE_TX_TRAIN_PAT_SEL_MASK (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)

#define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 @@ -413,6 +452,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 #define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)

+#define HPIPE_G1_SET5_REG 0x538 #define HPIPE_G3_SET5_REG 0x548 #define HPIPE_GX_SET5_ICP_OFFSET 0 #define HPIPE_GX_SET5_ICP_MASK (0xf << HPIPE_GX_SET5_ICP_OFFSET) @@ -502,6 +542,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define COMMON_SELECTOR_PHY_OFFSET 0x140 #define COMMON_SELECTOR_PIPE_OFFSET 0x144

+#define COMMON_PHY_SD_CTRL1 0x148 +#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 +#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 +#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)

/***** SATA registers *****/ #define SATA3_VENDOR_ADDRESS 0xA0

#define SATA3_VENDOR_ADDR_OFSSET 0

1.8.3.1

On 14 April 2017 at 22:16, Marcin Wojtas mw@semihalf.com wrote:

This patch introduces ComPhy description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple ComPhy chips and also significantly reduces amount of used PCD's for that purpose. Update PortingGuide documentation accordingly.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com

Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org

---

Documentation/Marvell/PortingGuide/ComPhy.txt | 64 +++------------- Platforms/Marvell/Armada/Armada70x0.dsc | 13 +--- Platforms/Marvell/Include/Library/MvComPhyLib.h | 5 ++ Platforms/Marvell/Include/Library/MvHwDescLib.h | 38 ++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 89 +++++++++++++++-------- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 14 +--- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 26 +------ Platforms/Marvell/Marvell.dec | 28 +------ 8 files changed, 122 insertions(+), 155 deletions(-)

diff --git a/Documentation/Marvell/PortingGuide/ComPhy.txt b/Documentation/Marvell/PortingGuide/ComPhy.txt index b5c4727..a96015e 100644 --- a/Documentation/Marvell/PortingGuide/ComPhy.txt +++ b/Documentation/Marvell/PortingGuide/ComPhy.txt @@ -2,44 +2,18 @@ COMPHY configuration

---

In order to configure ComPhy library, following PCDs are available:

• gMarvellTokenSpaceGuid.PcdComPhyChipCount

• gMarvellTokenSpaceGuid.PcdComPhyDevices

-Indicates how many different chips are placed on board. So far, up to 4 chips -are supported. +This array indicates, which ones of the ComPhy chips defined in +MVHW_COMPHY_DESC template will be configured.

Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not important, but configuration will be set for first PcdComPhyChipCount chips).

-Every chip has 8 ComPhy PCDs and three of them concern lanes settings for this -chip. Below is example for the first chip (Chip0).

-General PCDs:

• gMarvellTokenSpaceGuid.PcdChip0Compatible

-Unicode string indicating type of chip - currently supported is -{ L"Cp110" }

• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress

-Indicates COMPHY unit base address.

• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress

-Indicates Hpipe3 unit base address.

• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount

-Indicates number of bits that are allocated for every MUX in the -COMPHY-selector register.

• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes

-Indicates maximum ComPhy lanes number.

-Next three PCDs are in unicode string format containing settings for up to 10 -lanes. Setting for each one is separated with semicolon. These PCDs form -structure describing outputs of PHY integrated in simple cihp. +Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes +settings for this chip. Their format is unicode string, containing settings +for up to 10 lanes. Setting for each one is separated with semicolon. +These PCDs together describe outputs of PHY integrated in simple cihp. Below is example for the first chip (Chip0).

gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes @@ -48,16 +22,9 @@ Unicode string indicating PHY types. Currently supported are:

{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", -L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", +L"SGMII1", L"SGMII2", L"SGMII3", L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", -L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", -L"RXAUI1", L"KR" }

-Below documents describes some of above interfaces' types:

-SGMII, QSGMII, XAUI - IEEE 802.3 -KR - IEEE 802.3a -RXAUI - RXAUI Interface and RXAUI Adapter Specification, Marvell +L"RXAUI0", L"RXAUI1", L"SFI" }

gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds

@@ -72,14 +39,7 @@ Indicates lane polarity invert. Example

---

#ComPhy

• gMarvellTokenSpaceGuid.PcdComPhyChipCount|1
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6
• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000
• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4
• gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110"
• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
• gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;1250;5000;5000;5000"

• gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1;USB3_HOST1;PCIE2"
• gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;5000"

diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 5512d61..6ea46d7 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -97,13 +97,9 @@ gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18

#ComPhy

• gMarvellTokenSpaceGuid.PcdComPhyChipCount|1
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6
• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000
• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4
• gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110m"

• gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }

• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"

• gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000"

  #UtmiPhy gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2

@@ -112,9 +108,6 @@ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1"

• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
• gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000"
• #MDIO gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200

diff --git a/Platforms/Marvell/Include/Library/MvComPhyLib.h b/Platforms/Marvell/Include/Library/MvComPhyLib.h index 6bd6243..6076ede 100644 --- a/Platforms/Marvell/Include/Library/MvComPhyLib.h +++ b/Platforms/Marvell/Include/Library/MvComPhyLib.h @@ -35,6 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef __MVCOMPHYLIB_H__ #define __MVCOMPHYLIB_H__

+typedef enum {

• MvComPhyTypeCp110,
• MvComPhyTypeMax,

+} MV_COMPHY_CHIP_TYPE;

EFI_STATUS MvComPhyInit ( VOID diff --git a/Platforms/Marvell/Include/Library/MvHwDescLib.h b/Platforms/Marvell/Include/Library/MvHwDescLib.h index 32284a0..ac8dc37 100644 --- a/Platforms/Marvell/Include/Library/MvHwDescLib.h +++ b/Platforms/Marvell/Include/Library/MvHwDescLib.h @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef __MVHWDESCLIB_H__ #define __MVHWDESCLIB_H__

+#include <Library/MvComPhyLib.h> #include <Library/NonDiscoverableDeviceRegistrationLib.h>

// @@ -45,6 +46,20 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index])

// +// CommonPhy devices description template definition +// +#define MVHW_MAX_COMPHY_DEVS 4

+typedef struct {

• UINT8 ComPhyDevCount;
• UINTN ComPhyBaseAddresses[MVHW_MAX_COMPHY_DEVS];
• UINTN ComPhyHpipe3BaseAddresses[MVHW_MAX_COMPHY_DEVS];
• UINTN ComPhyLaneCount[MVHW_MAX_COMPHY_DEVS];
• UINTN ComPhyMuxBitCount[MVHW_MAX_COMPHY_DEVS];
• MV_COMPHY_CHIP_TYPE ComPhyChipType[MVHW_MAX_COMPHY_DEVS];

+} MVHW_COMPHY_DESC;

+// // NonDiscoverable devices description template definition // #define MVHW_MAX_XHCI_DEVS 4 @@ -81,6 +96,29 @@ typedef struct { } MVHW_RTC_DESC;

// +// Platform description of CommonPhy devices +// +#define MVHW_CP0_COMPHY_BASE 0xF2441000 +#define MVHW_CP0_HPIPE3_BASE 0xF2120000 +#define MVHW_CP0_COMPHY_LANES 6 +#define MVHW_CP0_COMPHY_MUX_BITS 4 +#define MVHW_CP1_COMPHY_BASE 0xF4441000 +#define MVHW_CP1_HPIPE3_BASE 0xF4120000 +#define MVHW_CP1_COMPHY_LANES 6 +#define MVHW_CP1_COMPHY_MUX_BITS 4

+#define DECLARE_A7K8K_COMPHY_TEMPLATE \ +STATIC \ +MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate = {\

• 2,\
• { MVHW_CP0_COMPHY_BASE, MVHW_CP1_COMPHY_BASE },\
• { MVHW_CP0_HPIPE3_BASE, MVHW_CP1_HPIPE3_BASE },\
• { MVHW_CP0_COMPHY_LANES, MVHW_CP1_COMPHY_LANES },\
• { MVHW_CP0_COMPHY_MUX_BITS, MVHW_CP1_COMPHY_MUX_BITS },\
• { MvComPhyTypeCp110, MvComPhyTypeCp110 }\

+}

+// // Platform description of NonDiscoverable devices // #define MVHW_CP0_XHCI0_BASE 0xF2500000 diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c index 174f10d..b61ccb6 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -33,6 +33,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/

#include "ComPhyLib.h" +#include <Library/MvComPhyLib.h> +#include <Library/MvHwDescLib.h>

+DECLARE_A7K8K_COMPHY_TEMPLATE;

CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3", @@ -46,14 +50,10 @@ CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps", L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"};

CHIP_COMPHY_CONFIG ChipCfgTbl[] = {

• { /* CP master */
• .ChipType = L"Cp110m",

• {
• .ChipType = MvComPhyTypeCp110, .Init = ComPhyCp110Init },

• { /* CP slave */
• .ChipType = L"Cp110s",
• .Init = ComPhyCp110Init
• }

};

VOID @@ -208,13 +208,12 @@ GetChipComPhyInit ( TblSize = sizeof(ChipCfgTbl) / sizeof(ChipCfgTbl[0]);

for (i = 0; i < TblSize ; i++) {

• if (StrCmp (PtrChipCfg->ChipType, ChipCfgTbl[i].ChipType) == 0) {

• if (PtrChipCfg->ChipType == ChipCfgTbl[i].ChipType) { PtrChipCfg->Init = ChipCfgTbl[i].Init; return EFI_SUCCESS; } }

• DEBUG((DEBUG_ERROR, "ComPhy: Empty ChipType string\n")); return EFI_D_ERROR;

}

@@ -222,18 +221,35 @@ STATIC VOID InitComPhyConfig ( IN OUT CHIP_COMPHY_CONFIG *ChipConfig,

• IN OUT PCD_LANE_MAP *LaneData

• IN OUT PCD_LANE_MAP *LaneData,
• IN UINT8 Id )

{

• MVHW_COMPHY_DESC *Desc = &mA7k8kComPhyDescTemplate;
• ChipConfig->ChipType = Desc->ComPhyChipType[Id];
• ChipConfig->ComPhyBaseAddr = Desc->ComPhyBaseAddresses[Id];
• ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id];
• ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id];
• ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id];
• /*

• • Below macro contains variable name concatenation (used to form PCD's name)
• • and that's why invoking it cannot be automated, e.g. using for loop.
• • Currently up to 4 ComPhys might be configured.

• • Below macro contains variable name concatenation (used to form PCD's name).
  */

• GetComPhyPcd(ChipConfig, LaneData, 0);
• GetComPhyPcd(ChipConfig, LaneData, 1);
• GetComPhyPcd(ChipConfig, LaneData, 2);
• GetComPhyPcd(ChipConfig, LaneData, 3);

• switch (Id) {
• case 0:
• GetComPhyPcd (ChipConfig, LaneData, 0);
• break;
• case 1:
• GetComPhyPcd (ChipConfig, LaneData, 1);
• break;
• case 2:
• GetComPhyPcd (ChipConfig, LaneData, 2);
• break;
• case 3:
• GetComPhyPcd (ChipConfig, LaneData, 3);
• break;
• }

}

EFI_STATUS @@ -242,29 +258,42 @@ MvComPhyInit ( ) { EFI_STATUS Status;

• CHIP_COMPHY_CONFIG ChipConfig[MAX_CHIPS], *PtrChipCfg;
• PCD_LANE_MAP LaneData[MAX_CHIPS];
• UINT32 Lane, ChipCount, i, MaxComphyCount;
• ChipCount = PcdGet32 (PcdComPhyChipCount);
• InitComPhyConfig(ChipConfig, LaneData);

• CHIP_COMPHY_CONFIG ChipConfig[MVHW_MAX_COMPHY_DEVS], *PtrChipCfg;
• PCD_LANE_MAP LaneData[MVHW_MAX_COMPHY_DEVS];
• UINT32 Lane, MaxComphyCount;
• UINT8 *ComPhyDeviceTable, Index;
• /* Obtain table with enabled ComPhy devices */
• ComPhyDeviceTable = (UINT8 *)PcdGetPtr (PcdComPhyDevices);
• if (ComPhyDeviceTable == NULL) {
• DEBUG ((DEBUG_ERROR, "Missing PcdComPhyDevices\n"));
• return EFI_INVALID_PARAMETER;
• }

• if (ChipCount <= 0 || ChipCount > MAX_CHIPS)

• if (PcdGetSize (PcdComPhyDevices) > MVHW_MAX_COMPHY_DEVS) {
• DEBUG ((DEBUG_ERROR, "Wrong PcdComPhyDevices format\n")); return EFI_INVALID_PARAMETER;
• }
• /* Initialize enabled chips */
• for (Index = 0; Index < PcdGetSize (PcdComPhyDevices); Index++) {
• if (!MVHW_DEV_ENABLED (ComPhy, Index)) {

•  DEBUG ((DEBUG_ERROR, "Skip ComPhy chip %d\n", Index));
  

•  continue;
  

• }

• for (i = 0; i < ChipCount ; i++) {
• PtrChipCfg = &ChipConfig[i];

• PtrChipCfg = &ChipConfig[Index];

• InitComPhyConfig(PtrChipCfg, LaneData, Index);

  /* Get the count of the SerDes of the specific chip */ MaxComphyCount = PtrChipCfg->LanesCount; for (Lane = 0; Lane < MaxComphyCount; Lane++) { /* Parse PCD with string indicating SerDes Type */ PtrChipCfg->MapData[Lane].Type =

•    ParseSerdesTypeString (LaneData[i].TypeStr[Lane]);
  

•    ParseSerdesTypeString (LaneData[Index].TypeStr[Lane]);
   PtrChipCfg->MapData[Lane].Speed =
  

•    ParseSerdesSpeed (LaneData[i].SpeedValue[Lane]);
  

•  PtrChipCfg->MapData[Lane].Invert = (UINT32) LaneData[i].InvFlag[Lane];
  

•    ParseSerdesSpeed (LaneData[Index].SpeedValue[Lane]);
  

•  PtrChipCfg->MapData[Lane].Invert = (UINT32)LaneData[Index].InvFlag[Lane];
  
   if ((PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_INVALID) ||
       (PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_ERROR) ||
  

@@ -278,7 +307,7 @@ MvComPhyInit (

 Status = GetChipComPhyInit (PtrChipCfg);
 if (EFI_ERROR(Status)) {

• DEBUG((DEBUG_ERROR, "ComPhy: Invalid Chip%dType name\n", i));
  

• DEBUG ((DEBUG_ERROR, "ComPhy: Invalid Chip%d type\n", Index));
  return Status;
  

  }

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h index 56bb991..3c589f2 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -40,22 +40,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include <Library/DebugLib.h> #include <Library/PcdLib.h> #include <Library/MemoryAllocationLib.h> +#include <Library/MvComPhyLib.h> #include <Library/IoLib.h> #include <Library/TimerLib.h> #include <Library/ParsePcdLib.h>

#define MAX_LANE_OPTIONS 10 -#define MAX_CHIPS 4

/***** Parsing PCD *****/ -#define GET_TYPE_STRING(id) PcdGetPtr(PcdChip##id##Compatible) #define GET_LANE_TYPE(id) PcdGetPtr(PcdChip##id##ComPhyTypes) #define GET_LANE_SPEED(id) PcdGetPtr(PcdChip##id##ComPhySpeeds) #define GET_LANE_INV(id) PcdGetPtr(PcdChip##id##ComPhyInvFlags) -#define GET_COMPHY_BASE_ADDR(id) PcdGet64(PcdChip##id##ComPhyBaseAddress) -#define GET_HPIPE3_BASE_ADDR(id) PcdGet64(PcdChip##id##Hpipe3BaseAddress) -#define GET_MUX_BIT_COUNT(id) PcdGet32(PcdChip##id##ComPhyMuxBitCount) -#define GET_MAX_LANES(id) PcdGet32(PcdChip##id##ComPhyMaxLanes)

#define FillLaneMap(chip_struct, lane_struct, id) { \ ParsePcdString((CHAR16 *) GET_LANE_TYPE(id), chip_struct[id].LanesCount, NULL, lane_struct[id].TypeStr); \ @@ -64,11 +59,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. }

#define GetComPhyPcd(chip_struct, lane_struct, id) { \

• chip_struct[id].ChipType = (CHAR16 *) GET_TYPE_STRING(id); \
• chip_struct[id].ComPhyBaseAddr = GET_COMPHY_BASE_ADDR(id); \
• chip_struct[id].Hpipe3BaseAddr = GET_HPIPE3_BASE_ADDR(id); \
• chip_struct[id].MuxBitCount = GET_MUX_BIT_COUNT(id); \
• chip_struct[id].LanesCount = GET_MAX_LANES(id); \ FillLaneMap(chip_struct, lane_struct, id); \

}

@@ -601,7 +591,7 @@ VOID );

struct _CHIP_COMPHY_CONFIG {

• CHAR16* ChipType;

• MV_COMPHY_CHIP_TYPE ChipType; COMPHY_MAP MapData[MAX_LANE_OPTIONS]; COMPHY_MUX_DATA *MuxData; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr;

diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf index 02905a5..ea0b83f 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -59,48 +59,24 @@ ComPhyMux.c

[FixedPcd]

• gMarvellTokenSpaceGuid.PcdComPhyChipCount

• gMarvellTokenSpaceGuid.PcdComPhyDevices

  #Chip0

• gMarvellTokenSpaceGuid.PcdChip0Compatible

• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress

• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress

• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount

• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes

• gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags

  #Chip1

• gMarvellTokenSpaceGuid.PcdChip1Compatible

• gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress

• gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress

• gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount

• gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes

• gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags

  #Chip2

• gMarvellTokenSpaceGuid.PcdChip2Compatible

• gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress

• gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress

• gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount

• gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes

• gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags

  #Chip3

• gMarvellTokenSpaceGuid.PcdChip3Compatible

• gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress

• gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress

• gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount

• gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes

• gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags

diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 735a71f..5cbf0c3 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -130,48 +130,24 @@ gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056

#ComPhy

• #Chip0
• gMarvellTokenSpaceGuid.PcdComPhyChipCount|0|UINT32|0x30000098
• gMarvellTokenSpaceGuid.PcdChip0Compatible|{ 0x0 }|VOID*|0x30000064
• gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0|UINT64|0x30000065
• gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0|UINT64|0x30000066
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|0|UINT32|0x30000067
• gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|0|UINT32|0x30001267

• gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098

• #Chip0 gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0x0 }|VOID*|0x30000068 gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x0 }|VOID*|0x30000069 gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0x0 }|VOID*|0x30000070

  #Chip1

• gMarvellTokenSpaceGuid.PcdChip1Compatible|{ 0x0 }|VOID*|0x30000100

• gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress|0|UINT64|0x30000101

• gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress|0|UINT64|0x30000102

• gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount|0|UINT32|0x30000103

• gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes|0|UINT32|0x30001304

• gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0x0 }|VOID*|0x30000105 gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0x0 }|VOID*|0x30000106 gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0x0 }|VOID*|0x30000107

  #Chip2

• gMarvellTokenSpaceGuid.PcdChip2Compatible|{ 0x0 }|VOID*|0x30000135

• gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress|0|UINT64|0x30000136

• gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress|0|UINT64|0x30000137

• gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount|0|UINT32|0x30000138

• gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes|0|UINT32|0x30000139

• gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0x0 }|VOID*|0x30000140 gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0x0 }|VOID*|0x30000141 gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0x0 }|VOID*|0x30000142

  #Chip3

• gMarvellTokenSpaceGuid.PcdChip3Compatible|{ 0x0 }|VOID*|0x30000170

• gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress|0|UINT64|0x30000171

• gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress|0|UINT64|0x30000172

• gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount|0|UINT32|0x30000173

• gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes|0|UINT32|0x30000174

• gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0x0 }|VOID*|0x30000175 gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000176 gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177

-- 1.8.3.1