This patch set include: 1 Add cpu on/off support for SBSA PE test; 2 Modify IoInitDxe.efi for SBSA test issue.
Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: d06-acs-non-osi
Ming Huang (4): Hisilicon/D06: Add cpu on/off feature in TrustedFirmware Hisilicon/D06: Fix SBSA test case 42 failed issues Hisilicon/D06: Fix set usb reg failed issue Hisilicon/D06: Fix SBSA PE-15 failed issue
.../D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 229216 -> 230816 bytes Platform/Hisilicon/D06/bl1.bin | Bin 12432 -> 12432 bytes Platform/Hisilicon/D06/fip.bin | Bin 113578 -> 113450 bytes 3 files changed, 0 insertions(+), 0 deletions(-)
Add cpu on/off feature to support SBSA-PE test.
Build commit information: TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/bl1.bin | Bin 12432 -> 12432 bytes Platform/Hisilicon/D06/fip.bin | Bin 113578 -> 113450 bytes 2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/bl1.bin b/Platform/Hisilicon/D06/bl1.bin index d291359..524c7fd 100644 Binary files a/Platform/Hisilicon/D06/bl1.bin and b/Platform/Hisilicon/D06/bl1.bin differ diff --git a/Platform/Hisilicon/D06/fip.bin b/Platform/Hisilicon/D06/fip.bin index a72bef8..078758f 100644 Binary files a/Platform/Hisilicon/D06/fip.bin and b/Platform/Hisilicon/D06/fip.bin differ
As SBSA uefi tool can't configuare interrupt following WatchdogTimerFlags in GTDT, and watchdog interrupt in Hi1620 is edge-trigger, so modify watchdog interrupt type for SBSA test case 42.
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:bf0bdef14d5 TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 229216 -> 229248 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index afd3ebe..c9172ff 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ
This issue may cause access usb3.0 device timeout.
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:2a7ee82855a TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 229248 -> 230784 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index c9172ff..8b6d740 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ
PE test case 15 flow: Primary core(cacheable shareable) and slave cores(non-cacheable) access the same memory area for communication. For each slave core{ 1 Turn on slave core; 2 run the payload function; 3 Write result in memory to notify primary core and follow clean and invalid instruction; 4 Slave core turn off itself; } The result in DDR may rewrite by cache data. The essence of this problem is that primary core and slave core access the same area with different cache attribute. Configure L3T register to fix this issue;
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:6e91ea20fda TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 230784 -> 230816 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index 8b6d740..b5aa0aa 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ
On Mon, Oct 29, 2018 at 11:51:10AM +0800, Ming Huang wrote:
This issue may cause access usb3.0 device timeout.
Can you add some more information? Examples of affected hardware? Visible behaviour to user?
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:2a7ee82855a
HwPgk-> HwPkg? (Also in 2/4.)
/ Leif
TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 229248 -> 230784 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index c9172ff..8b6d740 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ -- 2.18.0
+Prasanth
On Mon, Oct 29, 2018 at 11:51:11AM +0800, Ming Huang wrote:
PE test case 15 flow: Primary core(cacheable shareable) and slave cores(non-cacheable) access the same memory area for communication. For each slave core{ 1 Turn on slave core; 2 run the payload function; 3 Write result in memory to notify primary core and follow clean and invalid instruction;
clean and invalidate
4 Slave core turn off itself; } The result in DDR may rewrite by cache data. The essence of this problem is that primary core and slave core access the same area with different cache attribute. Configure L3T register to fix this issue;
Does this change have any performance implications?
Prasanth: would PE test 15 not be _expected_ to fail if primary and secondary cores access the buffers with different cachability attributes?
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:6e91ea20fda
HwPkg.
/ Leif
TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 230784 -> 230816 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index 8b6d740..b5aa0aa 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ -- 2.18.0
On Mon, Oct 29, 2018 at 11:51:09AM +0800, Ming Huang wrote:
As SBSA uefi tool can't configuare interrupt following WatchdogTimerFlags in GTDT, and watchdog interrupt in Hi1620 is edge-trigger, so modify watchdog interrupt type for SBSA test case 42.
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:bf0bdef14d5
HwPkg.
Other than that Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 229216 -> 229248 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index afd3ebe..c9172ff 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ -- 2.18.0
I'm fine with this message, but more changes may be required for PE15 test, so I won't give r-b yet.
On Mon, Oct 29, 2018 at 11:51:08AM +0800, Ming Huang wrote:
Add cpu on/off feature to support SBSA-PE test.
Build commit information: TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/bl1.bin | Bin 12432 -> 12432 bytes Platform/Hisilicon/D06/fip.bin | Bin 113578 -> 113450 bytes 2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/bl1.bin b/Platform/Hisilicon/D06/bl1.bin index d291359..524c7fd 100644 Binary files a/Platform/Hisilicon/D06/bl1.bin and b/Platform/Hisilicon/D06/bl1.bin differ diff --git a/Platform/Hisilicon/D06/fip.bin b/Platform/Hisilicon/D06/fip.bin index a72bef8..078758f 100644 Binary files a/Platform/Hisilicon/D06/fip.bin and b/Platform/Hisilicon/D06/fip.bin differ -- 2.18.0
Hi Leif,
-----Original Message----- From: Leif Lindholm leif.lindholm@linaro.org Sent: Wednesday, November 14, 2018 6:36 AM To: Ming Huang ming.huang@linaro.org Cc: linaro-uefi@lists.linaro.org; edk2-devel@lists.01.org; graeme.gregory@linaro.org; ard.biesheuvel@linaro.org; michael.d.kinney@intel.com; lersek@redhat.com; wanghuiqiang@huawei.com; huangming23@huawei.com; zhangjinsong2@huawei.com; huangdaode@hisilicon.com; john.garry@huawei.com; xinliang.liu@linaro.org; zhangfeng56@huawei.com; Prasanth Pulla Prasanth.Pulla@arm.com Subject: Re: [PATCH edk2-non-osi v1 4/4] Hisilicon/D06: Fix SBSA PE-15 failed issue
+Prasanth
On Mon, Oct 29, 2018 at 11:51:11AM +0800, Ming Huang wrote:
PE test case 15 flow: Primary core(cacheable shareable) and slave cores(non-cacheable) access the same memory area for communication. For each slave core{ 1 Turn on slave core; 2 run the payload function; 3 Write result in memory to notify primary core and follow clean and invalid instruction;
clean and invalidate
4 Slave core turn off itself; } The result in DDR may rewrite by cache data. The essence of this problem is that primary core and slave core access the same area with different cache attribute. Configure L3T register to fix this issue;
Does this change have any performance implications?
Prasanth: would PE test 15 not be _expected_ to fail if primary and secondary cores access the buffers with different cachability attributes?
No this is not expected. I will work with the team and see if we can enhance the ACS code to detect this and work in this scenario.
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:6e91ea20fda
HwPkg.
/ Leif
TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 230784 -> 230816 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index 8b6d740..b5aa0aa 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ -- 2.18.0
-Prasanth IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
On 11/14/2018 9:07 AM, Leif Lindholm wrote:
I'm fine with this message, but more changes may be required for PE15 test, so I won't give r-b yet.
There is another patch for PE15, this one is needed for bug 3996. https://bugs.linaro.org/show_bug.cgi?id=3996
On Mon, Oct 29, 2018 at 11:51:08AM +0800, Ming Huang wrote:
Add cpu on/off feature to support SBSA-PE test.
Build commit information: TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/bl1.bin | Bin 12432 -> 12432 bytes Platform/Hisilicon/D06/fip.bin | Bin 113578 -> 113450 bytes 2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/bl1.bin b/Platform/Hisilicon/D06/bl1.bin index d291359..524c7fd 100644 Binary files a/Platform/Hisilicon/D06/bl1.bin and b/Platform/Hisilicon/D06/bl1.bin differ diff --git a/Platform/Hisilicon/D06/fip.bin b/Platform/Hisilicon/D06/fip.bin index a72bef8..078758f 100644 Binary files a/Platform/Hisilicon/D06/fip.bin and b/Platform/Hisilicon/D06/fip.bin differ -- 2.18.0
On 11/14/2018 8:56 AM, Leif Lindholm wrote:
On Mon, Oct 29, 2018 at 11:51:10AM +0800, Ming Huang wrote:
This issue may cause access usb3.0 device timeout.
Can you add some more information? Examples of affected hardware? Visible behaviour to user?
The default link timeout value of USB 3.0 controller is a bit short for some USB devices, and may cause it timeout in some cases. We have modify the registers in IoInitDxe,but a bug let the modifying not successful.
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:2a7ee82855a
HwPgk-> HwPkg? (Also in 2/4.)
/ Leif
TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 229248 -> 230784 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index c9172ff..8b6d740 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ -- 2.18.0
On 11/14/2018 9:05 AM, Leif Lindholm wrote:
+Prasanth
On Mon, Oct 29, 2018 at 11:51:11AM +0800, Ming Huang wrote:
PE test case 15 flow: Primary core(cacheable shareable) and slave cores(non-cacheable) access the same memory area for communication. For each slave core{ 1 Turn on slave core; 2 run the payload function; 3 Write result in memory to notify primary core and follow clean and invalid instruction;
clean and invalidate
4 Slave core turn off itself; } The result in DDR may rewrite by cache data. The essence of this problem is that primary core and slave core access the same area with different cache attribute. Configure L3T register to fix this issue;
Does this change have any performance implications?
Feedback by chip engineer, performance may be reduced a bit.
Prasanth: would PE test 15 not be _expected_ to fail if primary and secondary cores access the buffers with different cachability attributes?
Build commit informations: edk2:53caffc33b6 edk2-platforms:d4d7e39886a HwPgk:6e91ea20fda
HwPkg.
/ Leif
TrustedFirmware:5888a78d43c
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 230784 -> 230816 bytes 1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi index 8b6d740..b5aa0aa 100644 Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ -- 2.18.0
On Wed, Nov 14, 2018 at 08:53:55AM +0000, Prasanth Pulla wrote:
The result in DDR may rewrite by cache data. The essence of this problem is that primary core and slave core access the same area with different cache attribute. Configure L3T register to fix this issue;
Does this change have any performance implications?
Prasanth: would PE test 15 not be _expected_ to fail if primary and secondary cores access the buffers with different cachability attributes?
No this is not expected. I will work with the team and see if we can enhance the ACS code to detect this and work in this scenario.
But the architecture itself does not guarantee this scenario should work?
/ Leif
-
Leif Lindholm -
Ming Huang -
Prasanth Pulla