From: Fu Wei fu.wei@linaro.org
This patchset update gtdt.asl for VExpress/AcpiTables/rtsm_ve-aemv8a
(1)Fix "Platform Timer Offset" value bug (2)Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model
Changelog: v2: Add "ontributed-under: TianoCore Contribution Agreement 1.0" for all patch Add an explanation for the fix of "Platform Timer Offset" value bug in the commit message.
v1: The first version upstream patchset to linaro mailing listf for OpenPlatformPkg
Fu Wei (2): Platforms/ARM: Fix "Platform Timer Offset" value bug in gtdt.asl Platforms/ARM: update gtdt.asl for VExpress
.../VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 67 +++++++++++++++++----- 1 file changed, 53 insertions(+), 14 deletions(-)
From: Fu Wei fu.wei@linaro.org
The old "Platform Timer Offset" value is miscalculated, it should include the byte length of "Platform Timer Offset". The definition of "Platform Timer Offset" is "Offset to the Platform Timer Structure[] array from the start of this table".
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei fu.wei@linaro.org --- Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..0cb24c5 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -86,7 +86,7 @@ [0008] CntReadBase Physical address : 0000000000000000
[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Offset : 00000060
/* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00
From: Fu Wei fu.wei@linaro.org
Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei fu.wei@linaro.org --- .../VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 65 +++++++++++++++++----- 1 file changed, 52 insertions(+), 13 deletions(-)
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index 0cb24c5..d02b231 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -36,16 +36,16 @@ */
[0004] Signature : "GTDT" -[0004] Table Length : 00000050 +[0004] Table Length : 000000D8 [0001] Revision : 02 [0001] Checksum : F1 [0006] Oem ID : "LINARO" [0008] Oem Table ID : "RTSMVEV8" -[0004] Oem Revision : 00000001 +[0004] Oem Revision : 00000002 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20110623
-[0008] Counter Block Address : 0000000000000000 +[0008] Counter Block Address : 000000002a430000 [0004] Reserved : 00000000
/* In RTSM model's dts file, the last cell of interrupts @@ -83,9 +83,9 @@ Always-on : 0
/* The 64-bit physical address at which the Counter Read block is located */ -[0008] CntReadBase Physical address : 0000000000000000 +[0008] CntReadBase Physical address : 000000002a800000
-[0004] Platform Timer Count : 00000001 +[0004] Platform Timer Count : 00000002 [0004] Platform Timer Offset : 00000060
/* Memory-mapped GT (Generic Timer) structures */ @@ -93,16 +93,25 @@ [0002] Length : 0064 [0001] Reserved : 000000 [0008] Block Address : 000000002a810000 -[0004] Timer Count : 00000001 -[0004] Timer Offset : 00000010 +[0004] Timer Count : 00000002 +[0004] Timer Offset : 00000014
-/* One frame is available */ +/* Two frames are available + * In FVP base model's dts file, the last cell of interrupts + * is 0x04, it means its trigger type is 4 = active high level-sensitive. + * + * So in ACPI the Trigger Mode is 0 - Level triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * Using direct mapping for hwirqs, it means that we using IRQ ID: + * (SPI offset + 32), not SPI offset used in FDT. + */ [0001] Frame Number : 00 [0003] Reserved : 000000 [0008] Base Address : 000000002a820000 -[0008] EL0 Base Address : FFFFFFFFFFFFFFFF -[0004] Timer Interrupt : 00000029 /* 25+16 */ -[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ +[0008] EL0 Base Address : 000000002a820000 +[0004] Timer Interrupt : 00000039 /* 25(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 /* No virtual timer */ @@ -110,7 +119,37 @@ [0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 -[0004] Common Flags (decoded below) : 00000000 - Secure : 0 +/* CNTPSIRQ Secure physical timer event.*/ +[0004] Common Flags (decoded below) : 00000001 + Secure : 1 + Always On : 0 + +[0001] Frame Number : 01 +[0003] Reserved : 000000 +[0008] Base Address : 000000002a830000 +[0008] EL0 Base Address : 000000002a830000 +[0004] Timer Interrupt : 0000003A /* 26(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +/* No virtual timer */ +[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +/* CNTPSIRQ1 Secure physical timer event.*/ +[0004] Common Flags (decoded below) : 00000001 + Secure : 1 Always On : 0
+/* One EL2 SBSA Generic Watchdog timer is available */ +[0001] Subtable Type : 01 [SBSA Generic Watchdog] +[0001] Length : 1C +[0002] Reserved : 0000 +[0008] Refresh Frame Address : 000000002a450000 +[0008] Control Frame Address : 000000002a440000 +[0004] Timer Interrupt : 0000003B /* 27(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Secure : 0
On 8 June 2015 at 08:19, fu.wei@linaro.org wrote:
From: Fu Wei fu.wei@linaro.org
The old "Platform Timer Offset" value is miscalculated, it should include the byte length of "Platform Timer Offset". The definition of "Platform Timer Offset" is "Offset to the Platform Timer Structure[] array from the start of this table".
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei fu.wei@linaro.org
Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..0cb24c5 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -86,7 +86,7 @@ [0008] CntReadBase Physical address : 0000000000000000
[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Offset : 00000060
I will add for info Offset type fields are generated automatically in iasl so this is probably why no-one has seen an issue. It is best practice though to make them correct!
Graeme
/* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00 -- 1.9.1
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