Hi all,
I posted an issue on macchiato@lists.einval.com which is specific to my m acchiato board setup. I just have a more generic question I would like to ask here:
It appears that in my Marvell environment the DT data received through the EFI mechanism may be partially corrupted (to be proven). The uboot boot sequence works perfectly, but the EDKII boot fails in the kernel with stalled CPUs due to PCIe failures and other interrupt handling problems.
Are there known issue receiving an FDT blob from EDKII using EFI?
If no, could you perhaps share the test setup at a high level?
Kind Regards, Fred
On 12 March 2018 at 16:28, Frederik Lotter frederik.lotter@netronome.com wrote:
Hi all,
I posted an issue on macchiato@lists.einval.com which is specific to my macchiato board setup. I just have a more generic question I would like to ask here:
It appears that in my Marvell environment the DT data received through the EFI mechanism may be partially corrupted (to be proven). The uboot boot sequence works perfectly, but the EDKII boot fails in the kernel with stalled CPUs due to PCIe failures and other interrupt handling problems.
Are there known issue receiving an FDT blob from EDKII using EFI?
This is clearly a PCIe problem, not a DT problem. UEFI and U-boot initialize the platform in different ways, and the Synopsys Designware PCIe IP on these chips is not quite PCIe compliant, and so a lot needs to happen under the hood to make it appear sane to the OS.
-
Ard Biesheuvel -
Frederik Lotter