Main Changes since v2 : 1 Move tidy and delete header file patch to the first of the series.
Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: 1902-platforms-v3
Jason Zhang (1): Hisilicon/D06: Fix access variable fail issue
Ming Huang (16): Hisilicon/D0x: Remove and tidy some codes about SerdesLib Hisilicon/D0x: Delete some header files Hisilicon/D0x: Add DriverHealthManagerDxe Hisilicon/D06: Optimize SAS driver for reducing boot time Hisilicon/D06: Drop the leading 0 (0x0 -> 0x) Hisilicon/D06: Add more PCIe port INT-x support Hisilicon/D0x: Rename StartupAp() function Hisilicon/D06: Use HCCS speed with 2.6G Hisilicon/D06: Add PCI_OSC_SUPPORT Hisilicon/D06: Modify for IMP self-Adapte support Hisilicon/D06: Add Setup Item "Support DPC" and delete some PCIe menus Hisilicon/D06: Use new flash layout Hisilicon/D06: Remove SECURE_BOOT_ENABLE definition Hisilicon/D0x: Remove SP805 watchdog pcd Hisilicon/D06: Fix USB crash issue(4079) Hisilicon/D0x: Modify version to 19.02
xingjiang tang (1): Hisilicon/D06: Add OemGetCpuFreq to encapsulate difference
Platform/Hisilicon/D03/D03.dsc | 8 +- Platform/Hisilicon/D05/D05.dsc | 8 +- Platform/Hisilicon/D06/D06.dsc | 19 +- Platform/Hisilicon/D03/D03.fdf | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D06/D06.fdf | 18 +- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf | 1 + Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 1 + Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf | 1 + Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 4 +- Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf | 1 + Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 1 + Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf | 1 - Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 1 + Platform/Hisilicon/D06/Include/Library/CpldD06.h | 4 + Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 131 --------- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 86 ------ Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h | 85 ------ Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110 ------- Silicon/Hisilicon/Include/Library/LpcLib.h | 113 ------- Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 45 --- Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Include/Library/OemMiscLib.h | 75 +++++ Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 112 ------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 4 +- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c | 2 +- Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 1 - Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c | 1 - Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 3 +- Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 2 +- Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 25 +- Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c | 281 ++++-------------- Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 6 +- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 311 +++++++++++++------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 47 files changed, 408 insertions(+), 1271 deletions(-) delete mode 100755 Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h delete mode 100644 Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h delete mode 100644 Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h delete mode 100644 Silicon/Hisilicon/Include/Library/IpmiCmdLib.h delete mode 100755 Silicon/Hisilicon/Include/Library/LpcLib.h delete mode 100644 Silicon/Hisilicon/Include/Library/OemAddressMapLib.h delete mode 100644 Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
As some definitions are about OemMiscLib, so move them from SerdesLib.h to OemMiscLib.h and drop some useless function definitions. After doing this, some unnecessary references can be removed for D03/D05.
SerdesLib is useless for SmbiosMiscDxe and D06, so remove it and delete SerdesLib.h for D06.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/D06.dsc | 2 - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +- Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 109 -------------------- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 64 ------------ Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h | 85 --------------- Silicon/Hisilicon/Include/Library/OemMiscLib.h | 75 ++++++++++++++ Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 1 - Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 1 - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c | 2 +- 11 files changed, 77 insertions(+), 266 deletions(-)
diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 396bd03c9d24..cbbd99e4a659 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -64,8 +64,6 @@ [LibraryClasses.common]
CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
- SerdesLib|Silicon/Hisilicon/Hi1620/Library/Hi1620Serdes/Hi1620SerdesLib.inf - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf index 61cead7779b9..669e6a2d52cc 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -69,6 +69,7 @@ [LibraryClasses] BaseMemoryLib BaseLib DebugLib + OemMiscLib UefiBootServicesTableLib UefiRuntimeServicesTableLib UefiDriverEntryPoint @@ -77,7 +78,6 @@ [LibraryClasses]
IpmiCmdLib
- SerdesLib
[Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 077dd5edc847..b493dd9ac090 100755 --- a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -16,116 +16,7 @@ #ifndef _SERDES_LIB_H_ #define _SERDES_LIB_H_
-typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Sas0X8 = 2, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - -typedef enum { - Em32coreEvbBoard = 0, - Em16coreEvbBoard = 1, - EmV2R1CO5Borad = 2, - EmOtherBorad -} BOARD_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType(UINT8 EthChannel); - EFI_STATUS EfiSerdesInitWrap (VOID);
-void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg); - -//EYE test -UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData); - -UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum); - -//PRBS test -int serdes_prbs_test(UINT8 macro, UINT8 lane, UINT8 prbstype); - -int serdes_prbs_test_cancle(UINT8 macro,UINT8 lane); - -//CTLE/DFE -void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane); - -void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane); - -void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane); - -void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane); - -void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane); -//int serdes_reset(UINT32 macro); -//int serdes_release_reset(UINT32 macro); -void Custom_Wave(UINT32 macro,UINT32 lane,UINT32 mode); -void serdes_ffe_show(UINT32 macro,UINT32 lane); -void serdes_dfe_show(UINT32 macro,UINT32 lane); -int serdes_read_bert(UINT8 macro, UINT8 lane); -void serdes_clean_bert(UINT8 macro, UINT8 lane); -int serdes_get_four_point_eye_diagram(UINT32 macro, UINT32 lane,UINT32 eyemode, UINT32 data_rate); -void serdes_release_mcu(UINT32 macro,UINT32 val); -int hilink_write(UINT32 macro, UINT32 reg, UINT32 value); -int hilink_read(UINT32 macro, UINT32 reg, UINT32 *value); -int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);//TXRXPARLPBKEN -int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val); -int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val); -void serdes_ctle_show(UINT32 macro,UINT32 lane); -int serdes_cs_write(UINT32 macro,UINT32 cs_num,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value); -UINT32 serdes_cs_read(UINT32 macro,UINT32 cs_num,UINT32 reg_num); -int serdes_ds_write(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value); -int serdes_ds_read(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num); -int report_serdes_mux(void); -int serdes_key_reg_show(UINT32 macro); -void serdes_state_show(UINT32 macro); -UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum); - #endif diff --git a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h index 7ff924bd8954..b493dd9ac090 100644 --- a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h +++ b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -16,71 +16,7 @@ #ifndef _SERDES_LIB_H_ #define _SERDES_LIB_H_
-typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType(UINT8 EthChannel); -VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); - EFI_STATUS EfiSerdesInitWrap (VOID); -INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); -VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
#endif diff --git a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h deleted file mode 100644 index 05f0f7020e82..000000000000 --- a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h +++ /dev/null @@ -1,85 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType (UINT8 EthChannel); -VOID SerdesEnableCtleDfe (UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); - -EFI_STATUS EfiSerdesInitWrap (UINT32 RateMode); -INT32 SerdesReset (UINT32 SiclId, UINT32 Macro); -VOID SerdesLoadFirmware (UINT32 SiclId, UINT32 Macro); -INT32 h30_serdes_run_firmware (UINT32 nimbus_id, UINT32 macro, UINT8 DsMask, UINT8 ctle_mode); -#endif diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h index 86ea6a1b3deb..b5a768856484 100644 --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -22,6 +22,67 @@ #include <PlatformArch.h> #include <Library/I2CLib.h>
+#define HCCS_PLL_VALUE_2600 0x52240681 +#define HCCS_PLL_VALUE_2800 0x52240701 +#define HCCS_PLL_VALUE_3000 0x52240781 + +typedef enum { + EmHilink0Hccs1X8 = 0, + EmHilink0Pcie1X8 = 2, + EmHilink0Pcie1X4Pcie2X4 = 3, + EmHilink0Sas2X8 = 4, + EmHilink0Hccs1X8Width16, + EmHilink0Hccs1X8Width32, + EmHilink0Hccs1X8Speed5G, +} HILINK0_MODE_TYPE; + +typedef enum { + EmHilink1Sas2X1 = 0, + EmHilink1Hccs0X8 = 1, + EmHilink1Pcie0X8 = 2, + EmHilink1Hccs0X8Width16, + EmHilink1Hccs0X8Width32, + EmHilink1Hccs0X8Speed5G, +} HILINK1_MODE_TYPE; + +typedef enum { + EmHilink2Pcie2X8 = 0, + EmHilink2Hccs2X8 = 1, + EmHilink2Sas0X8 = 2, + EmHilink2Hccs2X8Width16, + EmHilink2Hccs2X8Width32, + EmHilink2Hccs2X8Speed5G, +} HILINK2_MODE_TYPE; + +typedef enum { + EmHilink5Pcie3X4 = 0, + EmHilink5Pcie2X2Pcie3X2 = 1, + EmHilink5Sas1X4 = 2, +} HILINK5_MODE_TYPE; + + +typedef struct { + HILINK0_MODE_TYPE Hilink0Mode; + HILINK1_MODE_TYPE Hilink1Mode; + HILINK2_MODE_TYPE Hilink2Mode; + UINT32 Hilink3Mode; + UINT32 Hilink4Mode; + HILINK5_MODE_TYPE Hilink5Mode; + UINT32 Hilink6Mode; + UINT32 UseSsc; +} SERDES_PARAM; + +#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF + +typedef struct { + UINT32 MacroId; + UINT32 DsNum; + UINT32 DsCfg; +} SERDES_POLARITY_INVERT; + + #define PCIEDEVICE_REPORT_MAX 8 #define MAX_PROCESSOR_SOCKETS MAX_SOCKET #define MAX_MEMORY_CHANNELS MAX_CHANNEL @@ -53,4 +114,18 @@ BOOLEAN OemIsNeedDisableExpanderBuffer(VOID);
extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; EFI_HII_HANDLE EFIAPI OemGetPackages (); +UINTN OemGetCpuFreq (UINT8 Socket); + +UINTN +OemGetHccsFreq ( + VOID + ); + +EFI_STATUS +OemGetSerdesParam ( + SERDES_PARAM *ParamA, + SERDES_PARAM *ParamB, + UINT32 SocketId + ); + #endif diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 4771cb900c82..218b3540eb7f 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -21,7 +21,6 @@
#include <PlatformArch.h> #include <Library/OemMiscLib.h> -#include <Library/SerdesLib.h> #include <Library/I2CLib.h> #include <Library/HiiLib.h>
diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c index ae4c194070e8..1a9ed620c80c 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -22,7 +22,6 @@ #include <Library/I2CLib.h> #include <Library/IoLib.h> #include <Library/OemMiscLib.h> -#include <Library/SerdesLib.h> #include <Protocol/Smbios.h>
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c index 7e3f2e2a0e7d..c28ac6266fc6 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c @@ -21,7 +21,6 @@ #include <Library/I2CLib.h> #include <Library/IoLib.h> #include <Library/OemMiscLib.h> -#include <Library/SerdesLib.h> #include <Protocol/Smbios.h>
#include <PlatformArch.h> diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index 2a9db46d1ff9..c5cb77696031 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -24,7 +24,6 @@ #include <Library/OemMiscLib.h> #include <Library/PcdLib.h> #include <Library/PlatformSysCtrlLib.h> -#include <Library/SerdesLib.h> #include <Library/SerialPortLib.h> #include <Library/TimerLib.h>
diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index bc33639ac51d..945fd4c6e3c0 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -17,7 +17,7 @@
#include "SmbiosMisc.h"
-#include <Library/SerdesLib.h> +#include <Library/OemMiscLib.h>
extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie0Data; extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie1Data;
As some interfaces exposed only by implementations in edk2-non-osi, so delete corresponding header files and modify code to make build.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf | 1 + Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 1 + Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf | 1 + Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +- Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf | 1 + Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 1 + Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 1 + Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 22 ---- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 22 ---- Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110 ------------------- Silicon/Hisilicon/Include/Library/LpcLib.h | 113 -------------------- Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 45 -------- Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 112 ------------------- 20 files changed, 14 insertions(+), 426 deletions(-)
diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf index c65cf7b6dd9f..90e40ae2b393 100644 --- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf +++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf @@ -30,6 +30,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf index 0fa7fdf80fa8..c0195b2fa9cf 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf @@ -30,7 +30,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec - + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf index 0f6b68d4c88d..e82c9204d5d6 100644 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -29,6 +29,7 @@ [Packages] ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf index 022c3e940a31..7ec577530610 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -30,6 +30,7 @@ [Packages] ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf index 8296ee02de4e..715a4efadde8 100644 --- a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf @@ -29,6 +29,7 @@ [Packages] ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf index 75c5054bbfd1..9bc6eb549c41 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Platform/Hisilicon/D06/D06.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf index 93a2bcac3726..94f6fe404c6d 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf @@ -31,6 +31,7 @@ [Packages] IntelFrameworkPkg/IntelFrameworkPkg.dec IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf index 2275586ff324..808da65cd429 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf @@ -32,6 +32,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec IntelFrameworkPkg/IntelFrameworkPkg.dec
+ Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf index 669e6a2d52cc..0c37b53af987 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -58,7 +58,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec IntelFrameworkPkg/IntelFrameworkPkg.dec IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec - + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf index c07a5b8aa250..5b917fd3fdea 100644 --- a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf +++ b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf @@ -30,6 +30,7 @@ [Sources] [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf index 89447cc52d76..aa8e3c9c0b63 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf @@ -35,6 +35,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf index b603523100ae..d6b5248fcdbf 100644 --- a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf +++ b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf @@ -27,6 +27,7 @@ [Sources.common] [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses] diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf index 9bca88fe8702..e9520b39530e 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf index 1bb4f5c703bb..6211373ce7ba 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec
diff --git a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h deleted file mode 100755 index b493dd9ac090..000000000000 --- a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -EFI_STATUS -EfiSerdesInitWrap (VOID); - -#endif diff --git a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h deleted file mode 100644 index b493dd9ac090..000000000000 --- a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -EFI_STATUS -EfiSerdesInitWrap (VOID); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h deleted file mode 100644 index b956ee6d072a..000000000000 --- a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h +++ /dev/null @@ -1,110 +0,0 @@ -/** @file -* -* Copyright (c) 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _IPMI_CMD_LIB_H_ -#define _IPMI_CMD_LIB_H_ - -#define BOOT_OPTION_BOOT_FLAG_VALID 1 -#define BOOT_OPTION_BOOT_FLAG_INVALID 0 - -typedef enum { - EfiReserved, - EfiBiosFrb2, - EfiBiosPost, - EfiOsLoad, - EfiSmsOs, - EfiOem, - EfiFrbReserved1, - EfiFrbReserved2 -} EFI_WDT_USER_TYPE; - -typedef enum { - NoOverride = 0x0, - ForcePxe, - ForceDefaultHardDisk, - ForceDefaultHardDiskSafeMode, - ForceDefaultDiagnosticPartition, - ForceDefaultCD, - ForceSetupUtility, - ForceRemoteRemovableMedia, - ForceRemoteCD, - ForcePrimaryRemoteMedia, - ForceRemoteHardDisk = 0xB, - ForcePrimaryRemovableMedia = 0xF -} BOOT_DEVICE_SELECTOR; - -// -// Get System Boot Option data structure -// -typedef struct { - UINT8 ParameterVersion :4; - UINT8 Reserved1 :4; - UINT8 ParameterSelector :7; - UINT8 ParameterValid :1; - // - // Boot Flags Data 1 - // - UINT8 Reserved2 :5; - UINT8 BiosBootType :1; - UINT8 Persistent :1; - UINT8 BootFlagsValid :1; - // - // Boot Flags Data 2 - // - UINT8 LockResetBtn :1; - UINT8 ScreenBlank :1; - UINT8 BootDeviceSelector :4; - UINT8 LockKeyboard :1; - UINT8 ClearCmos :1; - // - // Boot Flags Data 3 - // - UINT8 ConsoleRedirectionControl :2; - UINT8 LockSleepBtn :1; - UINT8 UserPasswordByPass :1; - UINT8 Reserved3 :1; - UINT8 FirmwareVerbosity :2; - UINT8 LockPowerBtn :1; - // - // Boot Flags Data 4 - // - UINT8 MuxControlOverride :3; - UINT8 ShareModeOverride :1; - UINT8 Reserved4 :4; - // - // Boot Flags Data 5 - // - UINT8 DeviceInstanceSelector :5; - UINT8 Reserved5 :3; -} IPMI_GET_BOOT_OPTION; - -EFI_STATUS -EFIAPI -IpmiCmdSetSysBootOptions ( - OUT IPMI_GET_BOOT_OPTION *BootOption - ); - -EFI_STATUS -EFIAPI -IpmiCmdGetSysBootOptions ( - IN IPMI_GET_BOOT_OPTION *BootOption - ); - -EFI_STATUS -IpmiCmdStopWatchdogTimer ( - IN EFI_WDT_USER_TYPE UserType - ); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h deleted file mode 100755 index 236a52ba45a7..000000000000 --- a/Silicon/Hisilicon/Include/Library/LpcLib.h +++ /dev/null @@ -1,113 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _LPC_LIB_H_ -#define _LPC_LIB_H_ - -#include <Uefi.h> - -#define PCIE_SUBSYS_IO_MUX 0xA0170000 -#define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) -#define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) -#define PCIE_SUBSYS_IOMG036 (PCIE_SUBSYS_IO_MUX + 0x90) -#define PCIE_SUBSYS_IOMG045 (PCIE_SUBSYS_IO_MUX + 0xB4) -#define PCIE_SUBSYS_IOMG046 (PCIE_SUBSYS_IO_MUX + 0xB8) -#define PCIE_SUBSYS_IOMG047 (PCIE_SUBSYS_IO_MUX + 0xBC) -#define PCIE_SUBSYS_IOMG048 (PCIE_SUBSYS_IO_MUX + 0xC0) -#define PCIE_SUBSYS_IOMG049 (PCIE_SUBSYS_IO_MUX + 0xC4) -#define PCIE_SUBSYS_IOMG050 (PCIE_SUBSYS_IO_MUX + 0xC8) - -#define IO_WRAP_CTRL_BASE 0xA0100000 -#define SC_LPC_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a0) -#define SC_LPC_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03a4) -#define SC_LPC_BUS_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a8) -#define SC_LPC_BUS_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03ac) -#define SC_LPC_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ad8) -#define SC_LPC_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0adc) -#define SC_LPC_BUS_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ae0) -#define SC_LPC_BUS_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0ae4) -#define SC_LPC_CTRL_REG (IO_WRAP_CTRL_BASE + 0x2028) - - -#define LPC_BASE 0xA01B0000 -#define LPC_START_REG (LPC_BASE + 0x00) -#define LPC_OP_STATUS_REG (LPC_BASE + 0x04) -#define LPC_IRQ_ST_REG (LPC_BASE + 0x08) -#define LPC_OP_LEN_REG (LPC_BASE + 0x10) -#define LPC_CMD_REG (LPC_BASE + 0x14) -#define LPC_FWH_ID_MSIZE_REG (LPC_BASE + 0x18) -#define LPC_ADDR_REG (LPC_BASE + 0x20) -#define LPC_WDATA_REG (LPC_BASE + 0x24) -#define LPC_RDATA_REG (LPC_BASE + 0x28) -#define LPC_LONG_CNT_REG (LPC_BASE + 0x30) -#define LPC_TX_FIFO_ST_REG (LPC_BASE + 0x50) -#define LPC_RX_FIFO_ST_REG (LPC_BASE + 0x54) -#define LPC_TIME_OUT_REG (LPC_BASE + 0x58) -#define LPC_SIRQ_CTRL0_REG (LPC_BASE + 0x80) -#define LPC_SIRQ_CTRL1_REG (LPC_BASE + 0x84) -#define LPC_SIRQ_INT_REG (LPC_BASE + 0x90) -#define LPC_SIRQ_INT_MASK_REG (LPC_BASE + 0x94) -#define LPC_SIRQ_STAT_REG (LPC_BASE + 0xA0) - -#define LPC_FIFO_LEN (16) - -typedef enum{ - LPC_ADDR_MODE_INCREASE, - LPC_ADDR_MODE_SINGLE -}LPC_ADDR_MODE; - -typedef enum{ - LPC_TYPE_IO, - LPC_TYPE_MEM, - LPC_TYPE_FWH -}LPC_TYPE; - - -typedef union { - struct{ - UINT32 lpc_wr:1; - UINT32 lpc_type:2; - UINT32 same_addr:1; - UINT32 resv:28; - }bits; - UINT32 u32; -}LPC_CMD_STRUCT; - -typedef union { - struct{ - UINT32 op_len:5; - UINT32 resv:27; - }bits; - UINT32 u32; -}LPC_OP_LEN_STRUCT; - - -VOID LpcInit(VOID); -BOOLEAN LpcIdle(VOID); -EFI_STATUS LpcByteWrite( - IN UINT32 Addr, - IN UINT8 Data); -EFI_STATUS LpcByteRead( - IN UINT32 Addr, - IN OUT UINT8 *Data); - -EFI_STATUS LpcWrite( - IN UINT32 Addr, - IN UINT8 *Data, - IN UINT8 Len); - -#endif - - diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h deleted file mode 100644 index b5de34f5facb..000000000000 --- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h +++ /dev/null @@ -1,45 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _OEM_ADDRESS_MAP_LIB_H_ -#define _OEM_ADDRESS_MAP_LIB_H_ - -#include <PlatformArch.h> - -typedef struct _DDRC_BASE_ID{ - UINTN Base; - UINTN Id; -}DDRC_BASE_ID; - -// Invalid address, will cause exception when accessed by bug code -#define ADDRESS_MAP_INVALID ((UINTN)(-1)) - -UINTN OemGetPoeSubBase (UINT32 NodeId); -UINTN OemGetPeriSubBase (UINT32 NodeId); -UINTN OemGetAlgSubBase (UINT32 NodeId); -UINTN OemGetCfgbusBase (UINT32 NodeId); -UINTN OemGetGicSubBase (UINT32 NodeId); -UINTN OemGetHACSubBase (UINT32 NodeId); -UINTN OemGetIOMGMTSubBase (UINT32 NodeId); -UINTN OemGetNetworkSubBase (UINT32 NodeId); -UINTN OemGetM3SubBase (UINT32 NodeId); -UINTN OemGetPCIeSubBase (UINT32 NodeId); - -VOID OemAddressMapInit(VOID); - -extern DDRC_BASE_ID DdrcBaseId[MAX_SOCKET][MAX_CHANNEL]; - -#endif - diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h deleted file mode 100644 index a232e52ed719..000000000000 --- a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h +++ /dev/null @@ -1,112 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _PLATFORM_SYS_CTRL_LIB_H_ -#define _PLATFORM_SYS_CTRL_LIB_H_ - -#define PACKAGE_16CORE 0 -#define PACKAGE_32CORE 1 -#define PACKAGE_RESERVED 2 -#define PACKAGE_TYPE_NUM 3 - -UINT32 PlatformGetPackageType (VOID); - -VOID DisplayCpuInfo (VOID); -UINT32 CheckChipIsEc(VOID); - -UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll); - -#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF -#define DJTAG_CHAIN_ID_AA 1 -#define DJTAG_CHAIN_ID_LLC 4 - - -#define SC_DJTAG_MSTR_EN_OFFSET 0x6800 -#define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804 -#define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808 -#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C -#define SC_DJTAG_MSTR_WR_OFFSET 0x6810 -#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814 -#define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818 -#define SC_DJTAG_MSTR_DATA_OFFSET 0x681C -#define SC_DJTAG_TMOUT_OFFSET 0x6820 -#define SC_TDRE_OP_ADDR_OFFSET 0x6824 -#define SC_TDRE_WDATA_OFFSET 0x6828 -#define SC_TDRE_REPAIR_EN_OFFSET 0x682C -#define SC_DJTAG_RD_DATA0_OFFSET 0xE800 -#define SC_TDRE_RDATA0_OFFSET 0xE830 - - -UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port); - -VOID PlatformAddressMapCleanUp (VOID); -VOID PlatformDisableDdrWindow (VOID); - -VOID PlatformEnableArchTimer (VOID); - -EFI_STATUS -DawFindFreeWindow (UINTN Socket, UINTN *DawIndex); - -VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value); - -VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair); - -UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair); - -VOID RemoveRoceReset(VOID); - -UINTN PlatformGetDdrChannel (VOID); - -VOID ITSCONFIG (VOID); - -VOID MN_CONFIG (VOID); - -VOID SmmuConfigForOS (VOID); -VOID SmmuConfigForBios (VOID); - -VOID StartupAp (VOID); - -VOID LlcCleanInvalidate (VOID); - -UINTN PlatformGetCpuFreq (UINT8 Socket); -VOID ClearInterruptStatus(VOID); - -UINTN PlatformGetCoreCount (VOID); -VOID DAWConfigEn(UINT32 socket); - -VOID DResetUsb (); -UINT32 PlatformGetEhciBase (); -UINT32 PlatformGetOhciBase (); -VOID PlatformPllInit(); -// PLL initialization for super IO clusters. -VOID SiclPllInit(UINT32 SclId); -VOID PlatformDeviceDReset(); -VOID PlatformGicdInit(); -VOID PlatformLpcInit(); -// Synchronize architecture timer counter between different super computing -// clusters. -VOID PlatformArchTimerSynchronize(VOID); -VOID PlatformEventBroadcastConfig(VOID); -UINTN GetDjtagRegBase(UINT32 NodeId); -VOID LlcCleanInvalidateAsm(VOID); -VOID PlatformMdioInit(VOID); -VOID DisableClusterClock(UINTN CpuClusterBase); -VOID EnableClusterClock(UINTN CpuClusterBase); -VOID DisableSocketClock (UINT8 Skt); - -EFI_STATUS EFIAPI HandleI2CException (UINT32 Socket, UINT32 Port); -EFI_STATUS EFIAPI HandleI2CExceptionBySocket (UINT32 Socket); - -#endif
DriverHealthManagerDxe Collect driver health form of third party drivers to repair no healthy card.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D03/D03.dsc | 1 + Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D06/D06.dsc | 1 + Platform/Hisilicon/D03/D03.fdf | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D06/D06.fdf | 1 + 6 files changed, 6 insertions(+)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 3f59be22ec8e..fe443dd929ad 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -492,6 +492,7 @@ [Components.common]
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 25db1c38d287..0c4f21fbe056 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -638,6 +638,7 @@ [Components.common] MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index cbbd99e4a659..6d581337f199 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -435,6 +435,7 @@ [Components.common] Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index f453f9e46321..3f07b2e57778 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -295,6 +295,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
[FV.FVMAIN_COMPACT] diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 85dd791564a4..9632aea4b00e 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -314,6 +314,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
[FV.FVMAIN_COMPACT] diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index fda29ab322e9..a937660a09e2 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -319,6 +319,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
[FV.FVMAIN_COMPACT]
SAS controller is always existed, so accessing SAS register don't depend on PciBusDxe (pci enumeration). Move the SAS module early in D06.fdf for dispatching SAS driver early. This can avoid wait in BDS normally and reduce boot time.
This change is only valid after the update to SasDriverDxe in edk2-non-osi has been applied.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/D06.fdf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index a937660a09e2..d495ad7f264c 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -165,6 +165,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.inf + INF Platform/Hisilicon/D06/Drivers/Sas/SasDxeDriver.inf # # PI DXE Drivers producing Architectural Protocols (EFI Services) # @@ -296,7 +297,6 @@ [FV.FvMain] # INF Platform/Hisilicon/D06/Drivers/Sm750Dxe/UefiSmi.inf INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - INF Platform/Hisilicon/D06/Drivers/Sas/SasDxeDriver.inf INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
From: Jason Zhang zhangjinsong2@huawei.com
BmcWdtEnable is a field of OemConfigData structure, need have runtime service attribution if use it during exit boot service
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 470e9ace3dcf..08236704fbfe 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -23,7 +23,7 @@ formset help = STRING_TOKEN(STR_OEM_CONFIG), classguid = gEfiIfrFrontPageGuid, // for MdeModule Bds. efivarstore OEM_CONFIG_DATA, - attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS, name = OemConfig, guid = gOemConfigGuid;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 012d45bc0214..6668103af027 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -316,7 +316,7 @@ OemConfigUiLibConstructor ( Status = gRT->SetVariable ( OEM_CONFIG_NAME, &gOemConfigGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, sizeof (OEM_CONFIG_DATA), &Configuration );
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 24 ++++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 27fde2e09bfe..0f2d11bb952b 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -759,20 +759,20 @@ Device (PCI6) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added - Package () {0x04FFFF,0,0,640}, // INT_A - Package () {0x04FFFF,1,0,641}, // INT_B - Package () {0x04FFFF,2,0,642}, // INT_C - Package () {0x04FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A + Package () {0x4FFFF,1,0,641}, // INT_B + Package () {0x4FFFF,2,0,642}, // INT_C + Package () {0x4FFFF,3,0,643}, // INT_D
- Package () {0x08FFFF,0,0,640}, // INT_A - Package () {0x08FFFF,1,0,641}, // INT_B - Package () {0x08FFFF,2,0,642}, // INT_C - Package () {0x08FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A + Package () {0x8FFFF,1,0,641}, // INT_B + Package () {0x8FFFF,2,0,642}, // INT_C + Package () {0x8FFFF,3,0,643}, // INT_D
- Package () {0x0CFFFF,0,0,640}, // INT_A - Package () {0x0CFFFF,1,0,641}, // INT_B - Package () {0x0CFFFF,2,0,642}, // INT_C - Package () {0x0CFFFF,3,0,643}, // INT_D + Package () {0xCFFFF,0,0,640}, // INT_A + Package () {0xCFFFF,1,0,641}, // INT_B + Package () {0xCFFFF,2,0,642}, // INT_C + Package () {0xCFFFF,3,0,643}, // INT_D
Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B
Since NVMe riser width is 6*X4, need add the related port's INT-x support to match OS driver.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 37 +++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 0f2d11bb952b..4d9d9d95be68 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -41,11 +41,21 @@ Scope(_SB) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added + Package () {0x2FFFF,0,0,640}, // INT_A + Package () {0x2FFFF,1,0,641}, // INT_B + Package () {0x2FFFF,2,0,642}, // INT_C + Package () {0x2FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A Package () {0x4FFFF,1,0,641}, // INT_B Package () {0x4FFFF,2,0,642}, // INT_C Package () {0x4FFFF,3,0,643}, // INT_D
+ Package () {0x6FFFF,0,0,640}, // INT_A + Package () {0x6FFFF,1,0,641}, // INT_B + Package () {0x6FFFF,2,0,642}, // INT_C + Package () {0x6FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A Package () {0x8FFFF,1,0,641}, // INT_B Package () {0x8FFFF,2,0,642}, // INT_C @@ -56,6 +66,11 @@ Scope(_SB) Package () {0xCFFFF,2,0,642}, // INT_C Package () {0xCFFFF,3,0,643}, // INT_D
+ Package () {0xEFFFF,0,0,640}, // INT_A + Package () {0xEFFFF,1,0,641}, // INT_B + Package () {0xEFFFF,2,0,642}, // INT_C + Package () {0xEFFFF,3,0,643}, // INT_D + Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B Package () {0x10FFFF,2,0,642}, // INT_C @@ -759,11 +774,21 @@ Device (PCI6) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added + Package () {0x2FFFF,0,0,640}, // INT_A + Package () {0x2FFFF,1,0,641}, // INT_B + Package () {0x2FFFF,2,0,642}, // INT_C + Package () {0x2FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A Package () {0x4FFFF,1,0,641}, // INT_B Package () {0x4FFFF,2,0,642}, // INT_C Package () {0x4FFFF,3,0,643}, // INT_D
+ Package () {0x6FFFF,0,0,640}, // INT_A + Package () {0x6FFFF,1,0,641}, // INT_B + Package () {0x6FFFF,2,0,642}, // INT_C + Package () {0x6FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A Package () {0x8FFFF,1,0,641}, // INT_B Package () {0x8FFFF,2,0,642}, // INT_C @@ -774,11 +799,21 @@ Device (PCI6) Package () {0xCFFFF,2,0,642}, // INT_C Package () {0xCFFFF,3,0,643}, // INT_D
+ Package () {0xEFFFF,0,0,640}, // INT_A + Package () {0xEFFFF,1,0,641}, // INT_B + Package () {0xEFFFF,2,0,642}, // INT_C + Package () {0xEFFFF,3,0,643}, // INT_D + Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B Package () {0x10FFFF,2,0,642}, // INT_C Package () {0x10FFFF,3,0,643}, // INT_D - }) + + Package () {0x12FFFF,0,0,640}, // INT_A + Package () {0x12FFFF,1,0,641}, // INT_B + Package () {0x12FFFF,2,0,642}, // INT_C + Package () {0x12FFFF,3,0,643}, // INT_D + })
Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
From: xingjiang tang tangxingjiang@huawei.com
Implementation OemGetCpuFreq() to get cpu frequency from cpld to encapsulate project difference, for some projects don't support get cpu frequency by this way.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Include/Library/CpldD06.h | 4 ++++ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+)
diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h index ec9b49f4e70d..8eb333de529c 100644 --- a/Platform/Hisilicon/D06/Include/Library/CpldD06.h +++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h @@ -36,4 +36,8 @@ #define CPLD_X8_X8_X8_BOARD_ID 0x92 #define CPLD_X16_X8_BOARD_ID 0x93
+#define CPLD_CLOCK_FLAG 0xFD +#define CPLD_BOM_VER_FLAG 0x0B +#define CPLD_BOARD_REVISION_4TH 0x4 + #endif /* __CPLDD06_H__ */ diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index c5cb77696031..c8f71ecf890a 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -206,3 +206,19 @@ OemIsNeedDisableExpanderBuffer ( { return TRUE; } + +UINTN OemGetCpuFreq (UINT8 Socket) +{ + UINT8 BoardRevision; + + BoardRevision = MmioRead8 (CPLD_BASE_ADDRESS + CPLD_BOM_VER_FLAG); + + // Board revision 4 and higher run at 2.5GHz + // Earlier revisions run at 2GHz + if (BoardRevision >= CPLD_BOARD_REVISION_4TH) { + return 2500000000; + } else { + return 2000000000; + } +} +
As suggestion of community, 'AP' is a bit unfortunate to use in EDK2 context. PI specifies 'BSP' for Boot-strap Processor, as the one executing all of the EDK2 code. It then uses 'AP' to refer to Additional Processors, which can be assigned tasks using the EFI_MP_SERVICES_PROTOCOL. In a TianoCore context, this should be 'BSP'. So, Rename StartupAp() to StartUpBSP.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c | 2 +- Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 3 ++- Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 2 +- 5 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c index 97cf6b8d8757..dacd9e871faf 100644 --- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c +++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c @@ -83,7 +83,7 @@ void QResetAp(VOID) //SCCL A if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp(); + StartUpBSP (); } }
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index b57fdfa68e45..c8a9da73bbca 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -133,7 +133,7 @@ VOID CoreSelectBoot(VOID) { if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); }
return; diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c index 76a055cbe980..b374347e5c4d 100644 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -35,7 +35,7 @@ QResetAp ( (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp(); + StartUpBSP (); } }
diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c index 4c4c944dbead..a1458da7f0a3 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -96,7 +96,7 @@ UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) VOID CoreSelectBoot(VOID) { if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); }
return; @@ -128,3 +128,4 @@ BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) { return TRUE; } + diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c index 0790f7941ae7..a8261d370626 100644 --- a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c @@ -78,7 +78,7 @@ QResetAp (
//SCCL A if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); } }
Follow chip team suggestion, HCCS(Huawei Cache-Coherent System) may be unstable while speed is 3.0G, so use 2.6G to avoid some unstable stress issue.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index c8f71ecf890a..758157525f40 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -222,3 +222,11 @@ UINTN OemGetCpuFreq (UINT8 Socket) } }
+UINTN +OemGetHccsFreq ( + VOID + ) +{ + return HCCS_PLL_VALUE_2600; +} +
Add PCI_OSC_SUPPORT for remaining host bridges to remove fail output in kernel: [ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND);
Add PCI_OSC_SUPPORT_HOTPLUG to rewrite _OSC of PCI0 and PCI6.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 200 +++++++++++--------- 1 file changed, 106 insertions(+), 94 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 4d9d9d95be68..6dc380f27fa2 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -17,6 +17,90 @@ **/
//#include "ArmPlatform.h" + +/* + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 +*/ +#define PCI_OSC_SUPPORT() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Do not allow native PME, AER */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x10,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + +#define PCI_OSC_SUPPORT_HOTPLUG() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Always allow native PME, AER (no dependencies) */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x1D,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + Scope(_SB) { Device (PCI0) @@ -139,53 +223,7 @@ Scope(_SB) Return (RBUF) } // Method(_CRS), this method return RBUF!
- // - // OS Control Handoff - // - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - Method(_OSC,4) { - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - - // Only allow native hot plug control if OS supports: - // ASPM - // Clock PM - // MSI/MSI-X - If(LNotEqual(And(SUPP, 0x16), 0x16)) { - And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) - } - - // Always allow native PME, AER (no dependencies) - - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC + PCI_OSC_SUPPORT_HOTPLUG ()
Method (_HPX, 0) { Return (Package(2) { @@ -270,6 +308,8 @@ Device (PCI1) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -333,6 +373,8 @@ Device (PCI2) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -382,6 +424,8 @@ Device (PCI3) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -431,6 +475,8 @@ Device (PCI4) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -505,6 +551,8 @@ Device (PCI5) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -870,53 +918,7 @@ Device (PCI6) Return (RBUF) } // Method(_CRS), this method return RBUF!
- // - // OS Control Handoff - // - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - Method(_OSC,4) { - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - - // Only allow native hot plug control if OS supports: - // ASPM - // Clock PM - // MSI/MSI-X - If(LNotEqual(And(SUPP, 0x16), 0x16)) { - And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) - } - - // Always allow native PME, AER (no dependencies) - - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC + PCI_OSC_SUPPORT_HOTPLUG ()
Method (_HPX, 0) { Return (Package(2) { @@ -1002,6 +1004,8 @@ Device (PCI7) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1066,6 +1070,8 @@ Device (PCI8) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1115,6 +1121,8 @@ Device (PCI9) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1164,6 +1172,8 @@ Device (PCIA) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -1238,6 +1248,8 @@ Device (PCIB) Return (RBUF) } // Method(_CRS), this method return RBUF!
+ PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf)
As new IMP(Cortex-M7) firmware support self-adapte, so do not need BIOS to implement some function, remove useless funtions and report CPU0/CPU1 Nic NCL offset to IMP.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c | 281 ++++---------------- 1 file changed, 54 insertions(+), 227 deletions(-)
diff --git a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c index aaf990216982..678c2107bdd3 100644 --- a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c +++ b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c @@ -21,44 +21,21 @@ #include <Library/OemNicLib.h>
#define CPU2_SFP2_100G_CARD_OFFSET 0x25 -#define CPU1_SFP1_LOCATE_OFFSET 0x16 -#define CPU1_SFP0_LOCATE_OFFSET 0x12 -#define CPU2_SFP1_LOCATE_OFFSET 0x21 -#define CPU2_SFP0_LOCATE_OFFSET 0x19 -#define CPU2_SFP2_10G_GE_CARD_OFFSET 0x25
-#define SFP_10G_SPEED 10 -#define SFP_25G_SPEED 25 -#define SFP_100G_SPEED 100 -#define SFP_GE_SPEED 1 - -#define SFP_GE_SPEED_VAL_VENDOR_FINISAR 0x0C -#define SFP_GE_SPEED_VAL 0x0D -#define SFP_10G_SPEED_VAL 0x67 -#define SFP_25G_SPEED_VAL 0xFF +#define SOCKET1_NET_PORT_100G 1 +#define SOCKET0_NET_PORT_NUM 4 +#define SOCKET1_NET_PORT_NUM 2
#define CARD_PRESENT_100G (BIT7) -#define CARD_PRESENT_10G (BIT0) -#define SELECT_SFP_BY_INDEX(index) (1 << (index - 1)) -#define SPF_SPEED_OFFSET 12 - -#define SFP_DEVICE_ADDRESS 0x50 -#define CPU1_9545_I2C_ADDR 0x70 -#define CPU2_9545_I2C_ADDR 0x71 - -#define FIBER_PRESENT 0 -#define CARD_PRESENT 1 -#define I2C_PORT_SFP 4 -#define CPU2_I2C_PORT_SFP 5 - -#define SOCKET_0 0 -#define SOCKET_1 1 #define EEPROM_I2C_PORT 4 #define EEPROM_PAGE_SIZE 0x40 #define MAC_ADDR_LEN 6 #define I2C_OFFSET_EEPROM_ETH0 (0xc00) #define I2C_SLAVEADDR_EEPROM (0x52)
+#define SRAM_NIC_NCL1_OFFSET_ADDRESS 0xA0E87FE0 +#define SRAM_NIC_NCL2_OFFSET_ADDRESS 0xA0E87FE4 + #pragma pack(1) typedef struct { UINT16 Crc16; @@ -114,204 +91,6 @@ UINT16 CrcTable16[256] = { 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0, };
-EFI_STATUS -GetSfpSpeed ( - UINT16 Socket, - UINT16 SfpNum, - UINT8* FiberSpeed - ) -{ - EFI_STATUS Status; - I2C_DEVICE SpdDev; - UINT8 SfpSelect; - UINT8 SfpSpeed; - UINT32 RegAddr; - UINT16 I2cAddr; - UINT32 SfpPort; - - SfpSpeed = 0x0; - if (Socket == SOCKET_1) { - I2cAddr = CPU2_9545_I2C_ADDR; - SfpPort = CPU2_I2C_PORT_SFP; - } else { - I2cAddr = CPU1_9545_I2C_ADDR; - SfpPort = I2C_PORT_SFP; - } - - Status = I2CInit (Socket, SfpPort, Normal); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Socket%d Call I2CInit failed! p1=0x%x.\n", - __FUNCTION__, __LINE__, Socket, Status)); - return Status; - } - - SpdDev.Socket = Socket; - SpdDev.DeviceType = DEVICE_TYPE_SPD; - SpdDev.Port = SfpPort; - SpdDev.SlaveDeviceAddress = I2cAddr; - RegAddr = 0x0; - SfpSelect = SELECT_SFP_BY_INDEX (SfpNum); - - Status = I2CWrite (&SpdDev, RegAddr, 1, &SfpSelect); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "I2CWrite Error =%r.\n", Status)); - return Status; - } - - SpdDev.Socket = Socket; - SpdDev.DeviceType = DEVICE_TYPE_SPD; - SpdDev.Port = SfpPort; - SpdDev.SlaveDeviceAddress = SFP_DEVICE_ADDRESS; - - RegAddr = SPF_SPEED_OFFSET; - Status = I2CRead (&SpdDev, RegAddr, 1, &SfpSpeed); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "I2CRead Error =%r.\n", Status)); - return Status; - } - - DEBUG ((DEBUG_INFO, "BR, Nominal, Nominal signalling rate, SfpSpeed: 0x%x\n", - SfpSpeed)); - - if (SfpSpeed == SFP_10G_SPEED_VAL) { - *FiberSpeed = SFP_10G_SPEED; - } else if (SfpSpeed == SFP_25G_SPEED_VAL) { - *FiberSpeed = SFP_25G_SPEED; - } else if ((SfpSpeed == SFP_GE_SPEED_VAL) || - (SfpSpeed == SFP_GE_SPEED_VAL_VENDOR_FINISAR)) { - *FiberSpeed = SFP_GE_SPEED; - } - - return EFI_SUCCESS; -} - -//Fiber1Type/Fiber2Type/Fiber3Type return: SFP_10G_SPEED, SFP_100G_SPEED, SFP_GE_SPEED -UINT32 -GetCpu2FiberType ( - UINT8* Fiber1Type, - UINT8* Fiber2Type, - UINT8* Fiber100Ge - ) -{ - EFI_STATUS Status; - UINT16 SfpNum1; - UINT8 SfpSpeed1; - UINT16 SfpNum2; - UINT8 SfpSpeed2; - - SfpNum1 = 0x1; - SfpSpeed1 = SFP_10G_SPEED; - SfpNum2 = 0x2; - SfpSpeed2 = SFP_10G_SPEED; - *Fiber100Ge = 0x0; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - - if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { - // 100 Ge card - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - *Fiber100Ge = SFP_100G_SPEED; - DEBUG ((DEBUG_ERROR,"Detect Fiber SFP_100G is Present, Set 100Ge\n")); - } else if ((ReadCpldReg (CPU2_SFP2_10G_GE_CARD_OFFSET) & CARD_PRESENT_10G) != 0) { - *Fiber100Ge = 0x0; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - if (ReadCpldReg (CPU2_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) { - // Fiber detected in CPU2 slot0, read speed via i2c - Status = GetSfpSpeed (SOCKET_1, SfpNum1, &SfpSpeed1); - if (EFI_ERROR (Status)) { - DEBUG((DEBUG_ERROR, - "Get Socket1 Sfp%d Speed Error: %r.\n", - SfpNum1, - Status)); - return Status; - } - if (SfpSpeed1 == SFP_25G_SPEED) { - // P1 don't support 25G, so set speed to 10G - *Fiber1Type = SFP_10G_SPEED; - } else { - *Fiber1Type = SfpSpeed1; - } - } else { - // No fiber, set speed to 10G - *Fiber1Type = SFP_10G_SPEED; - } - - if (ReadCpldReg (CPU2_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) { - // Fiber detected in CPU2 slot1, read speed via i2c - Status = GetSfpSpeed (SOCKET_1, SfpNum2, &SfpSpeed2); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status)); - return Status; - } - if (SfpSpeed2 == SFP_25G_SPEED) { - *Fiber2Type = SFP_10G_SPEED; - } else { - *Fiber2Type = SfpSpeed2; - } - } else { - // No fiber, set speed to 10G - *Fiber2Type = SFP_10G_SPEED; - } - } else { - // 100Ge/10Ge/Ge Fiber is not found. - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - *Fiber100Ge = 0x0; - } - - return EFI_SUCCESS; -} - -//Fiber1Type/Fiber2Type return: SFP_10G_SPEED, SFP_25G_SPEED, SFP_GE_SPEED -UINT32 -GetCpu1FiberType ( - UINT8* Fiber1Type, - UINT8* Fiber2Type - ) -{ - EFI_STATUS Status; - UINT16 SfpNum1; - UINT8 SfpSpeed1; - UINT16 SfpNum2; - UINT8 SfpSpeed2; - - SfpNum1 = 0x1; - SfpSpeed1 = SFP_10G_SPEED; - SfpNum2 = 0x2; - SfpSpeed2 = SFP_10G_SPEED; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - // Fiber detected in CPU1 slot0, read speed via i2c - if (ReadCpldReg (CPU1_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) { - Status = GetSfpSpeed (SOCKET_0, SfpNum1, &SfpSpeed1); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get Socket0 Sfp%d Speed Error: %r.\n", - SfpNum1, Status)); - return Status; - } - *Fiber1Type = SfpSpeed1; - } else { - *Fiber1Type = SFP_10G_SPEED; - } - - // Fiber detected in CPU1 slot1, read speed via i2c - if (ReadCpldReg (CPU1_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) { - Status = GetSfpSpeed (SOCKET_0, SfpNum2, &SfpSpeed2); - if (EFI_ERROR (Status)) { - *Fiber2Type = SFP_10G_SPEED; - DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status)); - return Status; - } - *Fiber2Type = SfpSpeed2; - } else { - *Fiber2Type = SFP_10G_SPEED; - } - - return EFI_SUCCESS; -} - UINT16 MakeCrcCheckSum ( UINT8 *Buffer, UINT32 Length @@ -567,3 +346,51 @@ OemIsInitEth ( { return TRUE; } + +EFI_STATUS +ConfigCDR ( + UINT32 Socket + ) +{ + return EFI_SUCCESS; +} + +UINT32 +OemGetNclConfOffset ( + UINT32 Socket + ) +{ + UINT32 ConfigurationOffset; + + if (Socket == 0) { + // For 1st socket, the NCL configuration offset is 0 + ConfigurationOffset = 0; + MmioWrite32 (SRAM_NIC_NCL1_OFFSET_ADDRESS, ConfigurationOffset); + return ConfigurationOffset; + } + + // For 2nd Socket + if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { + ConfigurationOffset = SIZE_128KB; + } else { + ConfigurationOffset = SIZE_64KB; + } + MmioWrite32 (SRAM_NIC_NCL2_OFFSET_ADDRESS, ConfigurationOffset); + return ConfigurationOffset; +} + +UINT32 +OemGetNetPortNum ( + UINT32 Socket + ) +{ + if (Socket == 0){ + return SOCKET0_NET_PORT_NUM; + } + + if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { + return SOCKET1_NET_PORT_100G; + } else { + return SOCKET1_NET_PORT_NUM; + } +}
Add setup item "Support DPC" to enable or disable PCIe DPC (Downstream Port Containment).
The pcie menu is suppressed for original code as these menus are not ready. This patch remove the suppression for pcie menu, so delete these menus for now.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 5 files changed, 10 insertions(+), 197 deletions(-)
diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h index f120e3123c83..c0097d0829f0 100644 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h @@ -49,6 +49,7 @@ typedef struct { UINT8 OSWdtAction; /*PCIe Config*/ UINT8 PcieSRIOVSupport; + UINT8 PcieDPCSupport; UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 08236704fbfe..93ccb99bdc67 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -62,11 +62,9 @@ formset prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP);
- suppressif TRUE; goto PCIE_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); - endif;
goto MISC_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 6668103af027..be4ce8820f73 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( Configuration.OSWdtTimeout = 5; Configuration.OSWdtAction = 1; // + //Set the default value of the PCIe option + // + Configuration.PcieDPCSupport = 0; + // //Set the default value of the Misc option // Configuration.EnableSmmu = 1; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr index 7cf7cdd29ba2..c65907fe846e 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr @@ -17,203 +17,12 @@ form formid = PCIE_CONFIG_FORM_ID, title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE);
- goto VFR_FORMID_PCIE_SOCKET0, - prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - goto VFR_FORMID_PCIE_SOCKET1, - prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport, - prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT), - help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP), + oneof varid = OEM_CONFIG_DATA.PcieDPCSupport, + prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT), + help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; endoneof;
endform;
-form formid = VFR_FORMID_PCIE_SOCKET0, - title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT); - - goto VFR_FORMID_PCIE_PORT2, - prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT4, - prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT5, - prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT6, - prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT7, - prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - -endform; - -form formid = VFR_FORMID_PCIE_SOCKET1, - title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT); - goto VFR_FORMID_PCIE_PORT10, - prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT12, - prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT13, - prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); -endform; - -form formid = VFR_FORMID_PCIE_PORT0, - title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT); - #undef INDEX - #define INDEX 0 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT1, - title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT); - - #undef INDEX - #define INDEX 1 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT2, - title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT); - - #undef INDEX - #define INDEX 2 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT3, - title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT); - - #undef INDEX - #define INDEX 3 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT4, - title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT); - - #undef INDEX - #define INDEX 4 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT5, - title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT); - - #undef INDEX - #define INDEX 5 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT6, - title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT); - - #undef INDEX - #define INDEX 6 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT7, - title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT); - - #undef INDEX - #define INDEX 7 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT8, - title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT); - - #undef INDEX - #define INDEX 8 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT9, - title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT); - - #undef INDEX - #define INDEX 9 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT10, - title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT); - - #undef INDEX - #define INDEX 10 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT11, - title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT); - - #undef INDEX - #define INDEX 11 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT12, - title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT); - - #undef INDEX - #define INDEX 12 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT13, - title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT); - - #undef INDEX - #define INDEX 13 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT14, - title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT); - - #undef INDEX - #define INDEX 14 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT15, - title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT); - - #undef INDEX - #define INDEX 15 - #include "PciePortConfig.hfr" - -endform; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni index d87d30f975b8..0127ea952dee 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni @@ -26,7 +26,8 @@ #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" - +#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press <Enter> to config this port." #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" #string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0"
In new flash layout, BIOS fd change from offset 1M to 8M in 16M spi flash.
Use the new CustomData.Fv which indicate the offset of fd and which flash area can be updated for BMC.
This patch is relative with patch "Use new flash layout" in edk2-non-osi.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Platform/Hisilicon/D06/D06.fdf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index d495ad7f264c..f72b513352fb 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -29,7 +29,7 @@ [DEFINES] ################################################################################ [FD.D06]
-BaseAddress = 0x204100000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +BaseAddress = 0x204800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
Size = 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device ErasePolarity = 1 @@ -124,7 +124,7 @@ [FD.D06] 0x003E0000|0x00010000
0x003F0000|0x00010000 -FILE = Platform/Hisilicon/D0x-CustomData.Fv +FILE = Platform/Hisilicon/D06/CustomData.Fv
################################################################################ #
As secure boot is not ready, remove SECURE_BOOT_ENABLE and relative code.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D06/D06.dsc | 12 ------------ Platform/Hisilicon/D06/D06.fdf | 11 ----------- 2 files changed, 23 deletions(-)
diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 6d581337f199..a3a01bfb1e23 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -30,7 +30,6 @@ [Defines] FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf DEFINE NETWORK_IP6_ENABLE = FALSE DEFINE HTTP_BOOT_ENABLE = FALSE - DEFINE SECURE_BOOT_ENABLE = FALSE
!include Silicon/Hisilicon/Hisilicon.dsc.inc
@@ -87,9 +86,6 @@ [LibraryClasses.common] LpcLib|Silicon/Hisilicon/Hi1620/Library/LpcLibHi1620/LpcLib.inf SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf OemNicLib|Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf -!endif PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf PciPlatformLib|Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf
@@ -290,15 +286,7 @@ [Components.common] MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf
-!if $(SECURE_BOOT_ENABLE) == TRUE - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { - <LibraryClasses> - NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf - } - SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!else MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf -!endif Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index f72b513352fb..e402628a1b35 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -88,17 +88,10 @@ [FD.D06] #Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER -!if $(SECURE_BOOT_ENABLE) == TRUE - #Signature: gEfiAuthenticatedVariableGuid = - # { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} - 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, - 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, -!else #Signature: gEfiVariableGuid = # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, -!endif #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 0xB8, 0xdF, 0x00, 0x00, #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 @@ -183,10 +176,6 @@ [FV.FvMain] INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-!if $(SECURE_BOOT_ENABLE) == TRUE - INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!endif - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
SP805 watchdog is no used for D0x, so remove it.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D03/D03.dsc | 3 --- Platform/Hisilicon/D05/D05.dsc | 3 --- Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf | 1 - 3 files changed, 7 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index fe443dd929ad..35b54f8c83be 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -149,9 +149,6 @@ [PcdsFixedAtBuild.common]
gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x7 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3
- ## SP805 Watchdog - Motherboard Watchdog - gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000 - ## Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2F8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 0c4f21fbe056..49bd5b37ea34 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -163,9 +163,6 @@ [PcdsFixedAtBuild.common] gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
- ## SP805 Watchdog - Motherboard Watchdog - gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000 - ## Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf index 3563df6e10d1..4ce5f5fea1f3 100644 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf +++ b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf @@ -61,5 +61,4 @@ [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gHisiTokenSpaceGuid.PcdSysControlBaseAddress gHisiTokenSpaceGuid.PcdPeriSubctrlAddress - gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase
Last patch "Modify IORT" change revision id of node type 2 to 1, and 4.19 later kernel will judge the revision id to get root pci bridge DMA informations from IORT. As Hi1620 USB 2.0 don't support 64 bit DMA, but the DMA attribute get from IORT node type 2 is 64 bit. So add _DMA method in USB pci bridge 3 and pci bridge 8 to fix usb crash when usb device is present issue.
https://bugs.linaro.org/show_bug.cgi?id=4079
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 6dc380f27fa2..c1083dc16a2a 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -375,6 +375,29 @@ Device (PCI2)
PCI_OSC_SUPPORT ()
+ Method(_DMA, 0, Serialized) + { + Return (ResourceTemplate() + { + QWORDMemory( + ResourceConsumer, + PosDecode, // _DEC + MinFixed, // _MIF + MaxFixed, // _MAF + Prefetchable, // _MEM + ReadWrite, // _RW + 0, // _GRA + 0x00000000, // _MIN + 0xFFFFFFFF, // _MAX + 0x00000000, // _TRA + 0x100000000, // _LEN + , + , + , + ) + }) + } + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1077,6 +1100,29 @@ Device (PCI8) Return (0xf) }
+ Method(_DMA, 0, Serialized) + { + Return (ResourceTemplate() + { + QWORDMemory( + ResourceConsumer, + PosDecode, // _DEC + MinFixed, // _MIF + MaxFixed, // _MAF + Prefetchable, // _MEM + ReadWrite, // _RW + 0, // _GRA + 0x00000000, // _MIN + 0xFFFFFFFF, // _MAX + 0x00000000, // _TRA + 0x100000000, // _LEN + , + , + , + ) + }) + } + Method (_PXM, 0, NotSerialized) { Return(0x02)
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D03/D03.dsc | 4 ++-- Platform/Hisilicon/D05/D05.dsc | 4 ++-- Platform/Hisilicon/D06/D06.dsc | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 35b54f8c83be..07ff461277df 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -171,12 +171,12 @@ [PcdsFixedAtBuild.common] !ifdef $(FIRMWARE_VER) gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" !else - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.08 for Hisilicon D03" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 19.02 for Hisilicon D03" !endif
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12" + gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"19.02"
gHisiTokenSpaceGuid.PcdSystemProductName|L"D03" gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 49bd5b37ea34..70b044c7e33a 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -187,12 +187,12 @@ [PcdsFixedAtBuild.common] !ifdef $(FIRMWARE_VER) gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" !else - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.08 for Hisilicon D05" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 19.02 for Hisilicon D05" !endif
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12" + gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"19.02"
gHisiTokenSpaceGuid.PcdSystemProductName|L"D05" gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index a3a01bfb1e23..73bea728b0f6 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -156,12 +156,12 @@ [PcdsFixedAtBuild.common] !ifdef $(FIRMWARE_VER) gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" !else - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.08 for Hisilicon D06" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 19.02 for Hisilicon D06" !endif
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"0.42" + gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"19.02"
gHisiTokenSpaceGuid.PcdSystemProductName|L"D06" gHisiTokenSpaceGuid.PcdSystemVersion|L"VER.A"
Hi Ming,
On Wed, Mar 20, 2019 at 04:08:24PM +0800, Ming Huang wrote:
Add setup item "Support DPC" to enable or disable PCIe DPC (Downstream Port Containment).
The pcie menu is suppressed for original code as these menus are not ready. This patch remove the suppression for pcie menu, so delete these menus for now.
As the commit message shows, this patch does two unrelated things. Could you break this patch up into two separate ones and resubmit just those?
I will cherry-pick this patch manually in order to have it included in RPF 2019.03 -rc1, but I would prefer what goes in upstream to be cleaner.
Best Regards,
Leif
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 5 files changed, 10 insertions(+), 197 deletions(-)
diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h index f120e3123c83..c0097d0829f0 100644 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h @@ -49,6 +49,7 @@ typedef struct { UINT8 OSWdtAction; /*PCIe Config*/ UINT8 PcieSRIOVSupport;
- UINT8 PcieDPCSupport; UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS];
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 08236704fbfe..93ccb99bdc67 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -62,11 +62,9 @@ formset prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP);
- suppressif TRUE; goto PCIE_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP);
- endif;
goto MISC_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 6668103af027..be4ce8820f73 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( Configuration.OSWdtTimeout = 5; Configuration.OSWdtAction = 1; //
//Set the default value of the PCIe option//Configuration.PcieDPCSupport = 0;// //Set the default value of the Misc option // Configuration.EnableSmmu = 1;diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr index 7cf7cdd29ba2..c65907fe846e 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr @@ -17,203 +17,12 @@ form formid = PCIE_CONFIG_FORM_ID, title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE);
- goto VFR_FORMID_PCIE_SOCKET0,
- prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT),
- help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP);
- goto VFR_FORMID_PCIE_SOCKET1,
- prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT),
- help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP);
- oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport,
prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT),help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP),
- oneof varid = OEM_CONFIG_DATA.PcieDPCSupport,
prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT),help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED;endform; -form formid = VFR_FORMID_PCIE_SOCKET0,
- title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT);
- goto VFR_FORMID_PCIE_PORT2,
- prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT4,
- prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT5,
- prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT6,
- prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT7,
- prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-endform;
-form formid = VFR_FORMID_PCIE_SOCKET1,
- title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT);
- goto VFR_FORMID_PCIE_PORT10,
- prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT12,
- prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT13,
- prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-endform;
-form formid = VFR_FORMID_PCIE_PORT0,
- title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT);
- #undef INDEX
- #define INDEX 0
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT1,
- title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT);
- #undef INDEX
- #define INDEX 1
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT2,
- title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT);
- #undef INDEX
- #define INDEX 2
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT3,
- title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT);
- #undef INDEX
- #define INDEX 3
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT4,
- title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT);
- #undef INDEX
- #define INDEX 4
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT5,
- title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT);
- #undef INDEX
- #define INDEX 5
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT6,
- title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT);
- #undef INDEX
- #define INDEX 6
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT7,
- title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT);
- #undef INDEX
- #define INDEX 7
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT8,
- title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT);
- #undef INDEX
- #define INDEX 8
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT9,
- title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT);
- #undef INDEX
- #define INDEX 9
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT10,
- title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT);
- #undef INDEX
- #define INDEX 10
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT11,
- title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT);
- #undef INDEX
- #define INDEX 11
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT12,
- title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT);
- #undef INDEX
- #define INDEX 12
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT13,
- title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT);
- #undef INDEX
- #define INDEX 13
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT14,
- title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT);
- #undef INDEX
- #define INDEX 14
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT15,
- title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT);
- #undef INDEX
- #define INDEX 15
- #include "PciePortConfig.hfr"
-endform;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni index d87d30f975b8..0127ea952dee 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni @@ -26,7 +26,8 @@ #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function"
+#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press <Enter> to config this port." #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US ""
#string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0"
2.9.5
I will update the subject line to reflect what is actually being changed.
Other than that, Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
On Wed, Mar 20, 2019 at 04:08:16PM +0800, Ming Huang wrote:
From: Jason Zhang zhangjinsong2@huawei.com
BmcWdtEnable is a field of OemConfigData structure, need have runtime service attribution if use it during exit boot service
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 470e9ace3dcf..08236704fbfe 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -23,7 +23,7 @@ formset help = STRING_TOKEN(STR_OEM_CONFIG), classguid = gEfiIfrFrontPageGuid, // for MdeModule Bds. efivarstore OEM_CONFIG_DATA,
- attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
- attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS, name = OemConfig, guid = gOemConfigGuid;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 012d45bc0214..6668103af027 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -316,7 +316,7 @@ OemConfigUiLibConstructor ( Status = gRT->SetVariable ( OEM_CONFIG_NAME, &gOemConfigGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, sizeof (OEM_CONFIG_DATA), &Configuration );-- 2.9.5
Urgh, this was an unfortunate off-by-one post: I am deferring this patch until after Linaro's 2019.03 firmware release and cherry-picking it into that. There must be a better way to solve this.
My comment referred to "Hisilicon/D06: Drop the leading 0 (0x0 -> 0x)", which will be pushed with an improved subject.
/ Leif
On Thu, Mar 21, 2019 at 05:52:18PM +0000, Leif Lindholm wrote:
I will update the subject line to reflect what is actually being changed.
Other than that, Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
On Wed, Mar 20, 2019 at 04:08:16PM +0800, Ming Huang wrote:
From: Jason Zhang zhangjinsong2@huawei.com
BmcWdtEnable is a field of OemConfigData structure, need have runtime service attribution if use it during exit boot service
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 470e9ace3dcf..08236704fbfe 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -23,7 +23,7 @@ formset help = STRING_TOKEN(STR_OEM_CONFIG), classguid = gEfiIfrFrontPageGuid, // for MdeModule Bds. efivarstore OEM_CONFIG_DATA,
- attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
- attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS, name = OemConfig, guid = gOemConfigGuid;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 012d45bc0214..6668103af027 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -316,7 +316,7 @@ OemConfigUiLibConstructor ( Status = gRT->SetVariable ( OEM_CONFIG_NAME, &gOemConfigGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, sizeof (OEM_CONFIG_DATA), &Configuration );-- 2.9.5
On Wed, Mar 20, 2019 at 04:08:23PM +0800, Ming Huang wrote:
As new IMP(Cortex-M7) firmware support self-adapte, so do not need BIOS to implement some function, remove useless funtions
I will reword/correct the above to "unused functions". With that: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
and report CPU0/CPU1 Nic NCL offset to IMP.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c | 281 ++++---------------- 1 file changed, 54 insertions(+), 227 deletions(-)
diff --git a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c index aaf990216982..678c2107bdd3 100644 --- a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c +++ b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c @@ -21,44 +21,21 @@ #include <Library/OemNicLib.h> #define CPU2_SFP2_100G_CARD_OFFSET 0x25 -#define CPU1_SFP1_LOCATE_OFFSET 0x16 -#define CPU1_SFP0_LOCATE_OFFSET 0x12 -#define CPU2_SFP1_LOCATE_OFFSET 0x21 -#define CPU2_SFP0_LOCATE_OFFSET 0x19 -#define CPU2_SFP2_10G_GE_CARD_OFFSET 0x25 -#define SFP_10G_SPEED 10 -#define SFP_25G_SPEED 25 -#define SFP_100G_SPEED 100 -#define SFP_GE_SPEED 1
-#define SFP_GE_SPEED_VAL_VENDOR_FINISAR 0x0C -#define SFP_GE_SPEED_VAL 0x0D -#define SFP_10G_SPEED_VAL 0x67 -#define SFP_25G_SPEED_VAL 0xFF +#define SOCKET1_NET_PORT_100G 1 +#define SOCKET0_NET_PORT_NUM 4 +#define SOCKET1_NET_PORT_NUM 2 #define CARD_PRESENT_100G (BIT7) -#define CARD_PRESENT_10G (BIT0) -#define SELECT_SFP_BY_INDEX(index) (1 << (index - 1)) -#define SPF_SPEED_OFFSET 12
-#define SFP_DEVICE_ADDRESS 0x50 -#define CPU1_9545_I2C_ADDR 0x70 -#define CPU2_9545_I2C_ADDR 0x71
-#define FIBER_PRESENT 0 -#define CARD_PRESENT 1 -#define I2C_PORT_SFP 4 -#define CPU2_I2C_PORT_SFP 5
-#define SOCKET_0 0 -#define SOCKET_1 1 #define EEPROM_I2C_PORT 4 #define EEPROM_PAGE_SIZE 0x40 #define MAC_ADDR_LEN 6 #define I2C_OFFSET_EEPROM_ETH0 (0xc00) #define I2C_SLAVEADDR_EEPROM (0x52) +#define SRAM_NIC_NCL1_OFFSET_ADDRESS 0xA0E87FE0 +#define SRAM_NIC_NCL2_OFFSET_ADDRESS 0xA0E87FE4
#pragma pack(1) typedef struct { UINT16 Crc16; @@ -114,204 +91,6 @@ UINT16 CrcTable16[256] = { 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0, }; -EFI_STATUS -GetSfpSpeed (
- UINT16 Socket,
- UINT16 SfpNum,
- UINT8* FiberSpeed
- )
-{
- EFI_STATUS Status;
- I2C_DEVICE SpdDev;
- UINT8 SfpSelect;
- UINT8 SfpSpeed;
- UINT32 RegAddr;
- UINT16 I2cAddr;
- UINT32 SfpPort;
- SfpSpeed = 0x0;
- if (Socket == SOCKET_1) {
- I2cAddr = CPU2_9545_I2C_ADDR;
- SfpPort = CPU2_I2C_PORT_SFP;
- } else {
- I2cAddr = CPU1_9545_I2C_ADDR;
- SfpPort = I2C_PORT_SFP;
- }
- Status = I2CInit (Socket, SfpPort, Normal);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Socket%d Call I2CInit failed! p1=0x%x.\n",
__FUNCTION__, __LINE__, Socket, Status));- return Status;
- }
- SpdDev.Socket = Socket;
- SpdDev.DeviceType = DEVICE_TYPE_SPD;
- SpdDev.Port = SfpPort;
- SpdDev.SlaveDeviceAddress = I2cAddr;
- RegAddr = 0x0;
- SfpSelect = SELECT_SFP_BY_INDEX (SfpNum);
- Status = I2CWrite (&SpdDev, RegAddr, 1, &SfpSelect);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "I2CWrite Error =%r.\n", Status));
- return Status;
- }
- SpdDev.Socket = Socket;
- SpdDev.DeviceType = DEVICE_TYPE_SPD;
- SpdDev.Port = SfpPort;
- SpdDev.SlaveDeviceAddress = SFP_DEVICE_ADDRESS;
- RegAddr = SPF_SPEED_OFFSET;
- Status = I2CRead (&SpdDev, RegAddr, 1, &SfpSpeed);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "I2CRead Error =%r.\n", Status));
- return Status;
- }
- DEBUG ((DEBUG_INFO, "BR, Nominal, Nominal signalling rate, SfpSpeed: 0x%x\n",
SfpSpeed));- if (SfpSpeed == SFP_10G_SPEED_VAL) {
- *FiberSpeed = SFP_10G_SPEED;
- } else if (SfpSpeed == SFP_25G_SPEED_VAL) {
- *FiberSpeed = SFP_25G_SPEED;
- } else if ((SfpSpeed == SFP_GE_SPEED_VAL) ||
(SfpSpeed == SFP_GE_SPEED_VAL_VENDOR_FINISAR)) {- *FiberSpeed = SFP_GE_SPEED;
- }
- return EFI_SUCCESS;
-}
-//Fiber1Type/Fiber2Type/Fiber3Type return: SFP_10G_SPEED, SFP_100G_SPEED, SFP_GE_SPEED -UINT32 -GetCpu2FiberType (
- UINT8* Fiber1Type,
- UINT8* Fiber2Type,
- UINT8* Fiber100Ge
- )
-{
- EFI_STATUS Status;
- UINT16 SfpNum1;
- UINT8 SfpSpeed1;
- UINT16 SfpNum2;
- UINT8 SfpSpeed2;
- SfpNum1 = 0x1;
- SfpSpeed1 = SFP_10G_SPEED;
- SfpNum2 = 0x2;
- SfpSpeed2 = SFP_10G_SPEED;
- *Fiber100Ge = 0x0;
- *Fiber1Type = SFP_10G_SPEED;
- *Fiber2Type = SFP_10G_SPEED;
- if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) {
- // 100 Ge card
- *Fiber1Type = SFP_10G_SPEED;
- *Fiber2Type = SFP_10G_SPEED;
- *Fiber100Ge = SFP_100G_SPEED;
- DEBUG ((DEBUG_ERROR,"Detect Fiber SFP_100G is Present, Set 100Ge\n"));
- } else if ((ReadCpldReg (CPU2_SFP2_10G_GE_CARD_OFFSET) & CARD_PRESENT_10G) != 0) {
- *Fiber100Ge = 0x0;
- *Fiber1Type = SFP_10G_SPEED;
- *Fiber2Type = SFP_10G_SPEED;
- if (ReadCpldReg (CPU2_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) {
// Fiber detected in CPU2 slot0, read speed via i2cStatus = GetSfpSpeed (SOCKET_1, SfpNum1, &SfpSpeed1);if (EFI_ERROR (Status)) {DEBUG((DEBUG_ERROR,"Get Socket1 Sfp%d Speed Error: %r.\n",SfpNum1,Status));return Status;}if (SfpSpeed1 == SFP_25G_SPEED) {// P1 don't support 25G, so set speed to 10G*Fiber1Type = SFP_10G_SPEED;} else {*Fiber1Type = SfpSpeed1;}- } else {
// No fiber, set speed to 10G*Fiber1Type = SFP_10G_SPEED;- }
- if (ReadCpldReg (CPU2_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) {
// Fiber detected in CPU2 slot1, read speed via i2cStatus = GetSfpSpeed (SOCKET_1, SfpNum2, &SfpSpeed2);if (EFI_ERROR (Status)) {DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status));return Status;}if (SfpSpeed2 == SFP_25G_SPEED) {*Fiber2Type = SFP_10G_SPEED;} else {*Fiber2Type = SfpSpeed2;}- } else {
// No fiber, set speed to 10G*Fiber2Type = SFP_10G_SPEED;- }
- } else {
- // 100Ge/10Ge/Ge Fiber is not found.
- *Fiber1Type = SFP_10G_SPEED;
- *Fiber2Type = SFP_10G_SPEED;
- *Fiber100Ge = 0x0;
- }
- return EFI_SUCCESS;
-}
-//Fiber1Type/Fiber2Type return: SFP_10G_SPEED, SFP_25G_SPEED, SFP_GE_SPEED -UINT32 -GetCpu1FiberType (
- UINT8* Fiber1Type,
- UINT8* Fiber2Type
- )
-{
- EFI_STATUS Status;
- UINT16 SfpNum1;
- UINT8 SfpSpeed1;
- UINT16 SfpNum2;
- UINT8 SfpSpeed2;
- SfpNum1 = 0x1;
- SfpSpeed1 = SFP_10G_SPEED;
- SfpNum2 = 0x2;
- SfpSpeed2 = SFP_10G_SPEED;
- *Fiber1Type = SFP_10G_SPEED;
- *Fiber2Type = SFP_10G_SPEED;
- // Fiber detected in CPU1 slot0, read speed via i2c
- if (ReadCpldReg (CPU1_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) {
- Status = GetSfpSpeed (SOCKET_0, SfpNum1, &SfpSpeed1);
- if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Get Socket0 Sfp%d Speed Error: %r.\n",SfpNum1, Status));return Status;- }
- *Fiber1Type = SfpSpeed1;
- } else {
- *Fiber1Type = SFP_10G_SPEED;
- }
- // Fiber detected in CPU1 slot1, read speed via i2c
- if (ReadCpldReg (CPU1_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) {
- Status = GetSfpSpeed (SOCKET_0, SfpNum2, &SfpSpeed2);
- if (EFI_ERROR (Status)) {
*Fiber2Type = SFP_10G_SPEED;DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status));return Status;- }
- *Fiber2Type = SfpSpeed2;
- } else {
- *Fiber2Type = SFP_10G_SPEED;
- }
- return EFI_SUCCESS;
-}
UINT16 MakeCrcCheckSum ( UINT8 *Buffer, UINT32 Length @@ -567,3 +346,51 @@ OemIsInitEth ( { return TRUE; }
+EFI_STATUS +ConfigCDR (
- UINT32 Socket
- )
+{
- return EFI_SUCCESS;
+}
+UINT32 +OemGetNclConfOffset (
- UINT32 Socket
- )
+{
- UINT32 ConfigurationOffset;
- if (Socket == 0) {
- // For 1st socket, the NCL configuration offset is 0
- ConfigurationOffset = 0;
- MmioWrite32 (SRAM_NIC_NCL1_OFFSET_ADDRESS, ConfigurationOffset);
- return ConfigurationOffset;
- }
- // For 2nd Socket
- if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) {
- ConfigurationOffset = SIZE_128KB;
- } else {
- ConfigurationOffset = SIZE_64KB;
- }
- MmioWrite32 (SRAM_NIC_NCL2_OFFSET_ADDRESS, ConfigurationOffset);
- return ConfigurationOffset;
+}
+UINT32 +OemGetNetPortNum (
- UINT32 Socket
- )
+{
- if (Socket == 0){
- return SOCKET0_NET_PORT_NUM;
- }
- if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) {
- return SOCKET1_NET_PORT_100G;
- } else {
- return SOCKET1_NET_PORT_NUM;
- }
+}
2.9.5
On Wed, Mar 20, 2019 at 04:08:11PM +0800, Ming Huang wrote:
Main Changes since v2 : 1 Move tidy and delete header file patch to the first of the series.
Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: 1902-platforms-v3
Apart from the patches I've called out separately: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org Pushed as a8f34e0658..89f6901df0.
Thanks!
Jason Zhang (1): Hisilicon/D06: Fix access variable fail issue
Ming Huang (16): Hisilicon/D0x: Remove and tidy some codes about SerdesLib Hisilicon/D0x: Delete some header files Hisilicon/D0x: Add DriverHealthManagerDxe Hisilicon/D06: Optimize SAS driver for reducing boot time Hisilicon/D06: Drop the leading 0 (0x0 -> 0x) Hisilicon/D06: Add more PCIe port INT-x support Hisilicon/D0x: Rename StartupAp() function Hisilicon/D06: Use HCCS speed with 2.6G Hisilicon/D06: Add PCI_OSC_SUPPORT Hisilicon/D06: Modify for IMP self-Adapte support Hisilicon/D06: Add Setup Item "Support DPC" and delete some PCIe menus Hisilicon/D06: Use new flash layout Hisilicon/D06: Remove SECURE_BOOT_ENABLE definition Hisilicon/D0x: Remove SP805 watchdog pcd Hisilicon/D06: Fix USB crash issue(4079) Hisilicon/D0x: Modify version to 19.02
xingjiang tang (1): Hisilicon/D06: Add OemGetCpuFreq to encapsulate difference
Platform/Hisilicon/D03/D03.dsc | 8 +- Platform/Hisilicon/D05/D05.dsc | 8 +- Platform/Hisilicon/D06/D06.dsc | 19 +- Platform/Hisilicon/D03/D03.fdf | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D06/D06.fdf | 18 +- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf | 1 + Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 1 + Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf | 1 + Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 4 +- Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf | 1 + Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 1 + Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf | 1 - Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 1 + Platform/Hisilicon/D06/Include/Library/CpldD06.h | 4 + Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 131 --------- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 86 ------ Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h | 85 ------ Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110 ------- Silicon/Hisilicon/Include/Library/LpcLib.h | 113 ------- Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 45 --- Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Include/Library/OemMiscLib.h | 75 +++++ Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 112 ------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 4 +- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c | 2 +- Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 1 - Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c | 1 - Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 3 +- Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 2 +- Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 25 +- Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c | 281 ++++-------------- Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 6 +- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 311 +++++++++++++------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 47 files changed, 408 insertions(+), 1271 deletions(-) delete mode 100755 Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h delete mode 100644 Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h delete mode 100644 Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h delete mode 100644 Silicon/Hisilicon/Include/Library/IpmiCmdLib.h delete mode 100755 Silicon/Hisilicon/Include/Library/LpcLib.h delete mode 100644 Silicon/Hisilicon/Include/Library/OemAddressMapLib.h delete mode 100644 Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
-- 2.9.5
On 3/22/2019 1:56 AM, Leif Lindholm wrote:
Urgh, this was an unfortunate off-by-one post: I am deferring this patch until after Linaro's 2019.03 firmware release and cherry-picking it into that. There must be a better way to solve this.
My comment referred to "Hisilicon/D06: Drop the leading 0 (0x0 -> 0x)", which will be pushed with an improved subject.
I will change subject to: Add runtime attribution to OemConfig variable Should I change author to me to remove the "From: Jason Zhang"?
Thanks
/ Leif
On Thu, Mar 21, 2019 at 05:52:18PM +0000, Leif Lindholm wrote:
I will update the subject line to reflect what is actually being changed.
Other than that, Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
On Wed, Mar 20, 2019 at 04:08:16PM +0800, Ming Huang wrote:
From: Jason Zhang zhangjinsong2@huawei.com
BmcWdtEnable is a field of OemConfigData structure, need have runtime service attribution if use it during exit boot service
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 +- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 470e9ace3dcf..08236704fbfe 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -23,7 +23,7 @@ formset help = STRING_TOKEN(STR_OEM_CONFIG), classguid = gEfiIfrFrontPageGuid, // for MdeModule Bds. efivarstore OEM_CONFIG_DATA,
- attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
- attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS, name = OemConfig, guid = gOemConfigGuid;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 012d45bc0214..6668103af027 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -316,7 +316,7 @@ OemConfigUiLibConstructor ( Status = gRT->SetVariable ( OEM_CONFIG_NAME, &gOemConfigGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, sizeof (OEM_CONFIG_DATA), &Configuration );-- 2.9.5
On 3/21/2019 8:32 PM, Leif Lindholm wrote:
Hi Ming,
On Wed, Mar 20, 2019 at 04:08:24PM +0800, Ming Huang wrote:
Add setup item "Support DPC" to enable or disable PCIe DPC (Downstream Port Containment).
The pcie menu is suppressed for original code as these menus are not ready. This patch remove the suppression for pcie menu, so delete these menus for now.
As the commit message shows, this patch does two unrelated things. Could you break this patch up into two separate ones and resubmit just those?
I will break this patch up into two seperate ones soon.
Thanks
I will cherry-pick this patch manually in order to have it included in RPF 2019.03 -rc1, but I would prefer what goes in upstream to be cleaner.
Best Regards,
Leif
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org
Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 5 files changed, 10 insertions(+), 197 deletions(-)
diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h index f120e3123c83..c0097d0829f0 100644 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h @@ -49,6 +49,7 @@ typedef struct { UINT8 OSWdtAction; /*PCIe Config*/ UINT8 PcieSRIOVSupport;
- UINT8 PcieDPCSupport; UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS];
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 08236704fbfe..93ccb99bdc67 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -62,11 +62,9 @@ formset prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP);
- suppressif TRUE; goto PCIE_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP);
- endif;
goto MISC_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 6668103af027..be4ce8820f73 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( Configuration.OSWdtTimeout = 5; Configuration.OSWdtAction = 1; //
//Set the default value of the PCIe option//Configuration.PcieDPCSupport = 0;// //Set the default value of the Misc option // Configuration.EnableSmmu = 1;diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr index 7cf7cdd29ba2..c65907fe846e 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr @@ -17,203 +17,12 @@ form formid = PCIE_CONFIG_FORM_ID, title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE);
- goto VFR_FORMID_PCIE_SOCKET0,
- prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT),
- help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP);
- goto VFR_FORMID_PCIE_SOCKET1,
- prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT),
- help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP);
- oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport,
prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT),help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP),
- oneof varid = OEM_CONFIG_DATA.PcieDPCSupport,
prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT),help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED;endform; -form formid = VFR_FORMID_PCIE_SOCKET0,
- title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT);
- goto VFR_FORMID_PCIE_PORT2,
- prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT4,
- prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT5,
- prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT6,
- prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT7,
- prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-endform;
-form formid = VFR_FORMID_PCIE_SOCKET1,
- title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT);
- goto VFR_FORMID_PCIE_PORT10,
- prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT12,
- prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
- goto VFR_FORMID_PCIE_PORT13,
- prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT),
- help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
-endform;
-form formid = VFR_FORMID_PCIE_PORT0,
- title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT);
- #undef INDEX
- #define INDEX 0
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT1,
- title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT);
- #undef INDEX
- #define INDEX 1
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT2,
- title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT);
- #undef INDEX
- #define INDEX 2
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT3,
- title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT);
- #undef INDEX
- #define INDEX 3
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT4,
- title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT);
- #undef INDEX
- #define INDEX 4
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT5,
- title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT);
- #undef INDEX
- #define INDEX 5
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT6,
- title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT);
- #undef INDEX
- #define INDEX 6
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT7,
- title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT);
- #undef INDEX
- #define INDEX 7
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT8,
- title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT);
- #undef INDEX
- #define INDEX 8
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT9,
- title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT);
- #undef INDEX
- #define INDEX 9
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT10,
- title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT);
- #undef INDEX
- #define INDEX 10
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT11,
- title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT);
- #undef INDEX
- #define INDEX 11
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT12,
- title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT);
- #undef INDEX
- #define INDEX 12
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT13,
- title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT);
- #undef INDEX
- #define INDEX 13
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT14,
- title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT);
- #undef INDEX
- #define INDEX 14
- #include "PciePortConfig.hfr"
-endform;
-form formid = VFR_FORMID_PCIE_PORT15,
- title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT);
- #undef INDEX
- #define INDEX 15
- #include "PciePortConfig.hfr"
-endform;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni index d87d30f975b8..0127ea952dee 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni @@ -26,7 +26,8 @@ #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function"
+#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press <Enter> to config this port." #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US ""
#string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0"
2.9.5
-
Leif Lindholm -
Ming Huang