https://bugs.linaro.org/show_bug.cgi?id=3061 For fix this bug,the function PciIoPciRead of NonDiscoverablePciDeviceDxe should be modified also.
Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: rp-osi-bug-v2
Ming Huang (1): Hisilicon D0x: Remove uncacheable attribute from memory resource HOB
Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi | Bin 90272 -> 90336 bytes Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi | Bin 152576 -> 152480 bytes 2 files changed, 0 insertions(+), 0 deletions(-)
If uncacheable attribute is included in memory resource HOB, GCD spaces will also have EFI_MEMORY_UC capability, then NonCoherentPciIoAllocateBuffer of NonDiscoverablePciDeviceDxe module will allocate DMA buffer of EFI_MEMORY_UC type, which will cause alignment fault exception with BaseMemoryLibOptDxe.
This not only affects NonDiscoverablePciDeviceDxe, it removes the UC attribute from all DRAM regions in the UEFI memory map, which makes much more sense on ARM
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liu Yi liuyi86@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi | Bin 90272 -> 90336 bytes Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi | Bin 152576 -> 152480 bytes 2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi b/Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi index 354abcc..31e2903 100644 Binary files a/Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi and b/Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi differ diff --git a/Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi b/Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi index b94e0cb..eb71c44 100644 Binary files a/Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi and b/Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi differ
On 10 November 2017 at 07:31, Ming Huang heyi.guo@linaro.org wrote:
Please do something about the name/email address. These should be in sync.
If uncacheable attribute is included in memory resource HOB, GCD spaces will also have EFI_MEMORY_UC capability, then NonCoherentPciIoAllocateBuffer of NonDiscoverablePciDeviceDxe module will allocate DMA buffer of EFI_MEMORY_UC type, which will cause alignment fault exception with BaseMemoryLibOptDxe.
This not only affects NonDiscoverablePciDeviceDxe, it removes the UC attribute from all DRAM regions in the UEFI memory map, which makes much more sense on ARM
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liu Yi liuyi86@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
And here.
The contents look fine.
Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi | Bin 90272 -> 90336 bytes Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi | Bin 152576 -> 152480 bytes 2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi b/Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi index 354abcc..31e2903 100644 Binary files a/Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi and b/Platform/Hisilicon/D03/MemoryInitPei/MemoryInit.efi differ diff --git a/Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi b/Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi index b94e0cb..eb71c44 100644 Binary files a/Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi and b/Platform/Hisilicon/D05/MemoryInitPei/MemoryInit.efi differ -- 1.9.1
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Ard Biesheuvel -
Ming Huang