Hi,
On top of latest NonDiscoverable PciEmulation support I submit the last significant part of the platform support, which is SD/MMC driver. It is based on SDHCI, but requires a lot of quirks, not supported in EDK2. This is why SdMmcPciHcDxe driver had to be imported and modified.
Details can be found in commit logs and comments inside code. Due to some reasons operation with DMA enabled didn't succeed, hence the PassThru had to be reworked in order to support PIO mode.
Code is also available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp-...
We are looking forward to any comments or remarks.
Best regards, Marcin
Jan Dąbroś (3): Drivers/SdMmc: Import SdMmcPciHcDxe driver Drivers/SdMmc: Adjust SdMmcPciHcDxe to fulfill Xenon controller demands Platforms/Marvell: Enable SD/MMC stack for Armada70x0 platforms
Marcin Wojtas (1): Platforms/Marvell: Enable SD/MMC for Armada70x0 board
Drivers/SdMmc/MvSdMmcPciHcDxe.c | 1780 +++++++++++++++++++++++++++++++ Drivers/SdMmc/MvSdMmcPciHcDxe.inf | 75 ++ Drivers/SdMmc/XenonSdhci.c | 661 ++++++++++++ Drivers/SdMmc/XenonSdhci.h | 278 +++++ Platforms/Marvell/Armada/Armada.dsc.inc | 5 + Platforms/Marvell/Armada/Armada70x0.dsc | 1 + Platforms/Marvell/Armada/Armada70x0.fdf | 7 +- 7 files changed, 2806 insertions(+), 1 deletion(-) create mode 100755 Drivers/SdMmc/MvSdMmcPciHcDxe.c create mode 100644 Drivers/SdMmc/MvSdMmcPciHcDxe.inf create mode 100755 Drivers/SdMmc/XenonSdhci.c create mode 100644 Drivers/SdMmc/XenonSdhci.h
From: Jan Dąbroś jsd@semihalf.com
Import SdMmcPciHcDxe.c from tianocore/edk2 tree at revision a5991c8832c5: "IntelSiliconPkg: Add PCD for Graphics VBT FFS GUID" and rename it as MvSdMmcPciHcDxe.c
Because Marvell Xenon SD/MMC controller isn't fully compatible with SDHCI specification, it demands some quirks on generic driver during initialization and command processing. In order to achieve that, MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c is imported and adjusted correctly in following commit. Also in next patch's commit message necessary changes to generic driver are listed.
Xenon SD/MMC controller is present on Marvell Armada70x0 SoCs.
EFI_D_INFO, EFI_D_VERBOSE, EFI_D_WARN and EFI_D_ERROR are replaced with currently recommended values.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Drivers/SdMmc/MvSdMmcPciHcDxe.c | 1316 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 1316 insertions(+) create mode 100644 Drivers/SdMmc/MvSdMmcPciHcDxe.c
diff --git a/Drivers/SdMmc/MvSdMmcPciHcDxe.c b/Drivers/SdMmc/MvSdMmcPciHcDxe.c new file mode 100644 index 0000000..5adbbcd --- /dev/null +++ b/Drivers/SdMmc/MvSdMmcPciHcDxe.c @@ -0,0 +1,1316 @@ +/** @file + This driver is used to manage SD/MMC PCI host controllers which are compliance + with SD Host Controller Simplified Specification version 3.00. + + It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "SdMmcPciHcDxe.h" + +// +// Driver Global Variables +// +EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = { + SdMmcPciHcDriverBindingSupported, + SdMmcPciHcDriverBindingStart, + SdMmcPciHcDriverBindingStop, + 0x10, + NULL, + NULL +}; + +// +// Template for SD/MMC host controller private data. +// +SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = { + SD_MMC_HC_PRIVATE_SIGNATURE, // Signature + NULL, // ControllerHandle + NULL, // PciIo + { // PassThru + sizeof (UINT32), + SdMmcPassThruPassThru, + SdMmcPassThruGetNextSlot, + SdMmcPassThruBuildDevicePath, + SdMmcPassThruGetSlotNumber, + SdMmcPassThruResetDevice + }, + 0, // PciAttributes + 0, // PreviousSlot + NULL, // TimerEvent + NULL, // ConnectEvent + // Queue + INITIALIZE_LIST_HEAD_VARIABLE (gSdMmcPciHcTemplate.Queue), + { // Slot + {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, + {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0} + }, + { // Capability + {0}, + }, + { // MaxCurrent + 0, + }, + 0 // ControllerVersion +}; + +SD_DEVICE_PATH mSdDpTemplate = { + { + MESSAGING_DEVICE_PATH, + MSG_SD_DP, + { + (UINT8) (sizeof (SD_DEVICE_PATH)), + (UINT8) ((sizeof (SD_DEVICE_PATH)) >> 8) + } + }, + 0 +}; + +EMMC_DEVICE_PATH mEmmcDpTemplate = { + { + MESSAGING_DEVICE_PATH, + MSG_EMMC_DP, + { + (UINT8) (sizeof (EMMC_DEVICE_PATH)), + (UINT8) ((sizeof (EMMC_DEVICE_PATH)) >> 8) + } + }, + 0 +}; + +// +// Prioritized function list to detect card type. +// User could add other card detection logic here. +// +CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = { + EmmcIdentification, + SdCardIdentification, + NULL +}; + +/** + The entry point for SD host controller driver, used to install this driver on the ImageHandle. + + @param[in] ImageHandle The firmware allocated handle for this driver image. + @param[in] SystemTable Pointer to the EFI system table. + + @retval EFI_SUCCESS Driver loaded. + @retval other Driver not loaded. + +**/ +EFI_STATUS +EFIAPI +InitializeSdMmcPciHcDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, + SystemTable, + &gSdMmcPciHcDriverBinding, + ImageHandle, + &gSdMmcPciHcComponentName, + &gSdMmcPciHcComponentName2 + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Call back function when the timer event is signaled. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the + Event. + +**/ +VOID +EFIAPI +ProcessAsyncTaskList ( + IN EFI_EVENT Event, + IN VOID* Context + ) +{ + SD_MMC_HC_PRIVATE_DATA *Private; + LIST_ENTRY *Link; + SD_MMC_HC_TRB *Trb; + EFI_STATUS Status; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + BOOLEAN InfiniteWait; + EFI_EVENT TrbEvent; + + Private = (SD_MMC_HC_PRIVATE_DATA*)Context; + + // + // Check if the first entry in the async I/O queue is done or not. + // + Status = EFI_SUCCESS; + Trb = NULL; + Link = GetFirstNode (&Private->Queue); + if (!IsNull (&Private->Queue, Link)) { + Trb = SD_MMC_HC_TRB_FROM_THIS (Link); + if (!Private->Slot[Trb->Slot].MediaPresent) { + Status = EFI_NO_MEDIA; + goto Done; + } + if (!Trb->Started) { + // + // Check whether the cmd/data line is ready for transfer. + // + Status = SdMmcCheckTrbEnv (Private, Trb); + if (!EFI_ERROR (Status)) { + Trb->Started = TRUE; + Status = SdMmcExecTrb (Private, Trb); + if (EFI_ERROR (Status)) { + goto Done; + } + } else { + goto Done; + } + } + Status = SdMmcCheckTrbResult (Private, Trb); + } + +Done: + if ((Trb != NULL) && (Status == EFI_NOT_READY)) { + Packet = Trb->Packet; + if (Packet->Timeout == 0) { + InfiniteWait = TRUE; + } else { + InfiniteWait = FALSE; + } + if ((!InfiniteWait) && (Trb->Timeout-- == 0)) { + RemoveEntryList (Link); + Trb->Packet->TransactionStatus = EFI_TIMEOUT; + TrbEvent = Trb->Event; + SdMmcFreeTrb (Trb); + DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p EFI_TIMEOUT\n", TrbEvent)); + gBS->SignalEvent (TrbEvent); + return; + } + } + if ((Trb != NULL) && (Status != EFI_NOT_READY)) { + RemoveEntryList (Link); + Trb->Packet->TransactionStatus = Status; + TrbEvent = Trb->Event; + SdMmcFreeTrb (Trb); + DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p with %r\n", TrbEvent, Status)); + gBS->SignalEvent (TrbEvent); + } + return; +} + +/** + Sd removable device enumeration callback function when the timer event is signaled. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the + Event. + +**/ +VOID +EFIAPI +SdMmcPciHcEnumerateDevice ( + IN EFI_EVENT Event, + IN VOID* Context + ) +{ + SD_MMC_HC_PRIVATE_DATA *Private; + EFI_STATUS Status; + UINT8 Slot; + BOOLEAN MediaPresent; + UINT32 RoutineNum; + CARD_TYPE_DETECT_ROUTINE *Routine; + UINTN Index; + LIST_ENTRY *Link; + LIST_ENTRY *NextLink; + SD_MMC_HC_TRB *Trb; + EFI_TPL OldTpl; + + Private = (SD_MMC_HC_PRIVATE_DATA*)Context; + + for (Slot = 0; Slot < SD_MMC_HC_MAX_SLOT; Slot++) { + if ((Private->Slot[Slot].Enable) && (Private->Slot[Slot].SlotType == RemovableSlot)) { + Status = SdMmcHcCardDetect (Private->PciIo, Slot, &MediaPresent); + if ((Status == EFI_MEDIA_CHANGED) && !MediaPresent) { + DEBUG ((DEBUG_INFO, "SdMmcPciHcEnumerateDevice: device disconnected at slot %d of pci %p\n", Slot, Private->PciIo)); + Private->Slot[Slot].MediaPresent = FALSE; + Private->Slot[Slot].Initialized = FALSE; + // + // Signal all async task events at the slot with EFI_NO_MEDIA status. + // + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + for (Link = GetFirstNode (&Private->Queue); + !IsNull (&Private->Queue, Link); + Link = NextLink) { + NextLink = GetNextNode (&Private->Queue, Link); + Trb = SD_MMC_HC_TRB_FROM_THIS (Link); + if (Trb->Slot == Slot) { + RemoveEntryList (Link); + Trb->Packet->TransactionStatus = EFI_NO_MEDIA; + gBS->SignalEvent (Trb->Event); + SdMmcFreeTrb (Trb); + } + } + gBS->RestoreTPL (OldTpl); + // + // Notify the upper layer the connect state change through ReinstallProtocolInterface. + // + gBS->ReinstallProtocolInterface ( + Private->ControllerHandle, + &gEfiSdMmcPassThruProtocolGuid, + &Private->PassThru, + &Private->PassThru + ); + } + if ((Status == EFI_MEDIA_CHANGED) && MediaPresent) { + DEBUG ((DEBUG_INFO, "SdMmcPciHcEnumerateDevice: device connected at slot %d of pci %p\n", Slot, Private->PciIo)); + // + // Reset the specified slot of the SD/MMC Pci Host Controller + // + Status = SdMmcHcReset (Private->PciIo, Slot); + if (EFI_ERROR (Status)) { + continue; + } + // + // Reinitialize slot and restart identification process for the new attached device + // + Status = SdMmcHcInitHost (Private->PciIo, Slot, Private->Capability[Slot]); + if (EFI_ERROR (Status)) { + continue; + } + + Private->Slot[Slot].MediaPresent = TRUE; + Private->Slot[Slot].Initialized = TRUE; + RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE); + for (Index = 0; Index < RoutineNum; Index++) { + Routine = &mCardTypeDetectRoutineTable[Index]; + if (*Routine != NULL) { + Status = (*Routine) (Private, Slot); + if (!EFI_ERROR (Status)) { + break; + } + } + } + // + // This card doesn't get initialized correctly. + // + if (Index == RoutineNum) { + Private->Slot[Slot].Initialized = FALSE; + } + + // + // Notify the upper layer the connect state change through ReinstallProtocolInterface. + // + gBS->ReinstallProtocolInterface ( + Private->ControllerHandle, + &gEfiSdMmcPassThruProtocolGuid, + &Private->PassThru, + &Private->PassThru + ); + } + } + } + + return; +} +/** + Tests to see if this driver supports a given controller. If a child device is provided, + it further tests to see if this driver supports creating a handle for the specified child device. + + This function checks to see if the driver specified by This supports the device specified by + ControllerHandle. Drivers will typically use the device path attached to + ControllerHandle and/or the services from the bus I/O abstraction attached to + ControllerHandle to determine if the driver supports ControllerHandle. This function + may be called many times during platform initialization. In order to reduce boot times, the tests + performed by this function must be very small, and take as little time as possible to execute. This + function must not change the state of any hardware devices, and this function must be aware that the + device specified by ControllerHandle may already be managed by the same driver or a + different driver. This function must match its calls to AllocatePages() with FreePages(), + AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol(). + Since ControllerHandle may have been previously started by the same driver, if a protocol is + already in the opened state, then it must not be closed with CloseProtocol(). This is required + to guarantee the state of ControllerHandle is not modified by this function. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param[in] ControllerHandle The handle of the controller to test. This handle + must support a protocol interface that supplies + an I/O abstraction to the driver. + @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This + parameter is ignored by device drivers, and is optional for bus + drivers. For bus drivers, if this parameter is not NULL, then + the bus driver must determine if the bus controller specified + by ControllerHandle and the child controller specified + by RemainingDevicePath are both supported by this + bus driver. + + @retval EFI_SUCCESS The device specified by ControllerHandle and + RemainingDevicePath is supported by the driver specified by This. + @retval EFI_ALREADY_STARTED The device specified by ControllerHandle and + RemainingDevicePath is already being managed by the driver + specified by This. + @retval EFI_ACCESS_DENIED The device specified by ControllerHandle and + RemainingDevicePath is already being managed by a different + driver or an application that requires exclusive access. + Currently not implemented. + @retval EFI_UNSUPPORTED The device specified by ControllerHandle and + RemainingDevicePath is not supported by the driver specified by This. +**/ +EFI_STATUS +EFIAPI +SdMmcPciHcDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 PciData; + + PciIo = NULL; + ParentDevicePath = NULL; + + // + // SdPciHcDxe is a device driver, and should ingore the + // "RemainingDevicePath" according to EFI spec. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + (VOID *) &ParentDevicePath, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + // + // EFI_ALREADY_STARTED is also an error. + // + return Status; + } + // + // Close the protocol because we don't use it here. + // + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + // + // Now test the EfiPciIoProtocol. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Now further check the PCI header: Base class (offset 0x08) and + // Sub Class (offset 0x05). This controller should be an SD/MMC PCI + // Host Controller. + // + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint8, + 0, + sizeof (PciData), + &PciData + ); + if (EFI_ERROR (Status)) { + gBS->CloseProtocol ( + Controller, + &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + return EFI_UNSUPPORTED; + } + // + // Since we already got the PciData, we can close protocol to avoid to carry it + // on for multiple exit points. + // + gBS->CloseProtocol ( + Controller, + &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + // + // Examine SD PCI Host Controller PCI Configuration table fields. + // + if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) && + (PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) && + ((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) { + return EFI_SUCCESS; + } + + return EFI_UNSUPPORTED; +} + +/** + Starts a device controller or a bus controller. + + The Start() function is designed to be invoked from the EFI boot service ConnectController(). + As a result, much of the error checking on the parameters to Start() has been moved into this + common boot service. It is legal to call Start() from other locations, + but the following calling restrictions must be followed or the system behavior will not be deterministic. + 1. ControllerHandle must be a valid EFI_HANDLE. + 2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned + EFI_DEVICE_PATH_PROTOCOL. + 3. Prior to calling Start(), the Supported() function for the driver specified by This must + have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param[in] ControllerHandle The handle of the controller to start. This handle + must support a protocol interface that supplies + an I/O abstraction to the driver. + @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This + parameter is ignored by device drivers, and is optional for bus + drivers. For a bus driver, if this parameter is NULL, then handles + for all the children of Controller are created by this driver. + If this parameter is not NULL and the first Device Path Node is + not the End of Device Path Node, then only the handle for the + child device specified by the first Device Path Node of + RemainingDevicePath is created by this driver. + If the first Device Path Node of RemainingDevicePath is + the End of Device Path Node, no child handle is created by this + driver. + + @retval EFI_SUCCESS The device was started. + @retval EFI_DEVICE_ERROR The device could not be started due to a device error.Currently not implemented. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval Others The driver failded to start the device. + +**/ +EFI_STATUS +EFIAPI +SdMmcPciHcDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_STATUS Status; + SD_MMC_HC_PRIVATE_DATA *Private; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT64 Supports; + UINT64 PciAttributes; + UINT8 SlotNum; + UINT8 FirstBar; + UINT8 Slot; + UINT8 Index; + CARD_TYPE_DETECT_ROUTINE *Routine; + UINT32 RoutineNum; + BOOLEAN MediaPresent; + BOOLEAN Support64BitDma; + + DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); + + // + // Open PCI I/O Protocol and save pointer to open protocol + // in private data area. + // + PciIo = NULL; + Status = gBS->OpenProtocol ( + Controller, + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Enable the SD Host Controller MMIO space + // + Private = NULL; + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationGet, + 0, + &PciAttributes + ); + + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationSupported, + 0, + &Supports + ); + + if (!EFI_ERROR (Status)) { + Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE; + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationEnable, + Supports, + NULL + ); + } else { + goto Done; + } + + Private = AllocateCopyPool (sizeof (SD_MMC_HC_PRIVATE_DATA), &gSdMmcPciHcTemplate); + if (Private == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Private->ControllerHandle = Controller; + Private->PciIo = PciIo; + Private->PciAttributes = PciAttributes; + InitializeListHead (&Private->Queue); + + // + // Get SD/MMC Pci Host Controller Slot info + // + Status = SdMmcHcGetSlotInfo (PciIo, &FirstBar, &SlotNum); + if (EFI_ERROR (Status)) { + goto Done; + } + + Support64BitDma = TRUE; + for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) { + Private->Slot[Slot].Enable = TRUE; + + Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]); + if (EFI_ERROR (Status)) { + continue; + } + DumpCapabilityReg (Slot, &Private->Capability[Slot]); + + Support64BitDma &= Private->Capability[Slot].SysBus64; + + Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); + if (EFI_ERROR (Status)) { + continue; + } + + Private->Slot[Slot].SlotType = Private->Capability[Slot].SlotType; + if ((Private->Slot[Slot].SlotType != RemovableSlot) && (Private->Slot[Slot].SlotType != EmbeddedSlot)) { + DEBUG ((DEBUG_INFO, "SdMmcPciHcDxe doesn't support the slot type [%d]!!!\n", Private->Slot[Slot].SlotType)); + continue; + } + + // + // Reset the specified slot of the SD/MMC Pci Host Controller + // + Status = SdMmcHcReset (PciIo, Slot); + if (EFI_ERROR (Status)) { + continue; + } + // + // Check whether there is a SD/MMC card attached + // + Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent); + if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) { + continue; + } else if (!MediaPresent) { + DEBUG ((DEBUG_ERROR, "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n", Slot)); + continue; + } + + Status = SdMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]); + if (EFI_ERROR (Status)) { + continue; + } + + Private->Slot[Slot].MediaPresent = TRUE; + Private->Slot[Slot].Initialized = TRUE; + RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE); + for (Index = 0; Index < RoutineNum; Index++) { + Routine = &mCardTypeDetectRoutineTable[Index]; + if (*Routine != NULL) { + Status = (*Routine) (Private, Slot); + if (!EFI_ERROR (Status)) { + break; + } + } + } + // + // This card doesn't get initialized correctly. + // + if (Index == RoutineNum) { + Private->Slot[Slot].Initialized = FALSE; + } + } + + // + // Enable 64-bit DMA support in the PCI layer if this controller + // supports it. + // + if (Support64BitDma) { + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationEnable, + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "SdMmcPciHcDriverBindingStart: failed to enable 64-bit DMA (%r)\n", Status)); + } + } + + // + // Start the asynchronous I/O monitor + // + Status = gBS->CreateEvent ( + EVT_TIMER | EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + ProcessAsyncTaskList, + Private, + &Private->TimerEvent + ); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, SD_MMC_HC_ASYNC_TIMER); + if (EFI_ERROR (Status)) { + goto Done; + } + + // + // Start the Sd removable device connection enumeration + // + Status = gBS->CreateEvent ( + EVT_TIMER | EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SdMmcPciHcEnumerateDevice, + Private, + &Private->ConnectEvent + ); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = gBS->SetTimer (Private->ConnectEvent, TimerPeriodic, SD_MMC_HC_ENUM_TIMER); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Controller, + &gEfiSdMmcPassThruProtocolGuid, + &(Private->PassThru), + NULL + ); + + DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: %r End on %x\n", Status, Controller)); + +Done: + if (EFI_ERROR (Status)) { + if ((Private != NULL) && (Private->PciAttributes != 0)) { + // + // Restore original PCI attributes + // + PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationSet, + Private->PciAttributes, + NULL + ); + } + gBS->CloseProtocol ( + Controller, + &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + if ((Private != NULL) && (Private->TimerEvent != NULL)) { + gBS->CloseEvent (Private->TimerEvent); + } + + if ((Private != NULL) && (Private->ConnectEvent != NULL)) { + gBS->CloseEvent (Private->ConnectEvent); + } + + if (Private != NULL) { + FreePool (Private); + } + } + + return Status; +} + +/** + Stops a device controller or a bus controller. + + The Stop() function is designed to be invoked from the EFI boot service DisconnectController(). + As a result, much of the error checking on the parameters to Stop() has been moved + into this common boot service. It is legal to call Stop() from other locations, + but the following calling restrictions must be followed or the system behavior will not be deterministic. + 1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this + same driver's Start() function. + 2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid + EFI_HANDLE. In addition, all of these handles must have been created in this driver's + Start() function, and the Start() function must have called OpenProtocol() on + ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param[in] ControllerHandle A handle to the device being stopped. The handle must + support a bus specific I/O protocol for the driver + to use to stop the device. + @param[in] NumberOfChildren The number of child device handles in ChildHandleBuffer. + @param[in] ChildHandleBuffer An array of child handles to be freed. May be NULL + if NumberOfChildren is 0. + + @retval EFI_SUCCESS The device was stopped. + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error. + +**/ +EFI_STATUS +EFIAPI +SdMmcPciHcDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ) +{ + EFI_STATUS Status; + EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru; + SD_MMC_HC_PRIVATE_DATA *Private; + EFI_PCI_IO_PROTOCOL *PciIo; + LIST_ENTRY *Link; + LIST_ENTRY *NextLink; + SD_MMC_HC_TRB *Trb; + + DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStop: Start\n")); + + Status = gBS->OpenProtocol ( + Controller, + &gEfiSdMmcPassThruProtocolGuid, + (VOID**) &PassThru, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); + // + // Close Non-Blocking timer and free Task list. + // + if (Private->TimerEvent != NULL) { + gBS->CloseEvent (Private->TimerEvent); + Private->TimerEvent = NULL; + } + if (Private->ConnectEvent != NULL) { + gBS->CloseEvent (Private->ConnectEvent); + Private->ConnectEvent = NULL; + } + // + // As the timer is closed, there is no needs to use TPL lock to + // protect the critical region "queue". + // + for (Link = GetFirstNode (&Private->Queue); + !IsNull (&Private->Queue, Link); + Link = NextLink) { + NextLink = GetNextNode (&Private->Queue, Link); + RemoveEntryList (Link); + Trb = SD_MMC_HC_TRB_FROM_THIS (Link); + Trb->Packet->TransactionStatus = EFI_ABORTED; + gBS->SignalEvent (Trb->Event); + SdMmcFreeTrb (Trb); + } + + // + // Uninstall Block I/O protocol from the device handle + // + Status = gBS->UninstallProtocolInterface ( + Controller, + &gEfiSdMmcPassThruProtocolGuid, + &(Private->PassThru) + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + gBS->CloseProtocol ( + Controller, + &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + // + // Restore original PCI attributes + // + PciIo = Private->PciIo; + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationSet, + Private->PciAttributes, + NULL + ); + ASSERT_EFI_ERROR (Status); + + FreePool (Private); + + DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStop: End with %r\n", Status)); + + return Status; +} + +/** + Sends SD command to an SD card that is attached to the SD controller. + + The PassThru() function sends the SD command specified by Packet to the SD card + specified by Slot. + + If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned. + + If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned. + + If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER + is returned. + + If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL, + EFI_INVALID_PARAMETER is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[in,out] Packet A pointer to the SD command data structure. + @param[in] Event If Event is NULL, blocking I/O is performed. If Event is + not NULL, then nonblocking I/O is performed, and Event + will be signaled when the Packet completes. + + @retval EFI_SUCCESS The SD Command Packet was sent by the host. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD + command Packet. + @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid. + @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and + OutDataBuffer are NULL. + @retval EFI_NO_MEDIA SD Device not present in the Slot. + @retval EFI_UNSUPPORTED The command described by the SD Command Packet is not + supported by the host controller. + @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the + limit supported by SD card ( i.e. if the number of bytes + exceed the Last LBA). + +**/ +EFI_STATUS +EFIAPI +SdMmcPassThruPassThru ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ) +{ + EFI_STATUS Status; + SD_MMC_HC_PRIVATE_DATA *Private; + SD_MMC_HC_TRB *Trb; + EFI_TPL OldTpl; + + if ((This == NULL) || (Packet == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) { + return EFI_INVALID_PARAMETER; + } + + Private = SD_MMC_HC_PRIVATE_FROM_THIS (This); + + if (!Private->Slot[Slot].Enable) { + return EFI_INVALID_PARAMETER; + } + + if (!Private->Slot[Slot].MediaPresent) { + return EFI_NO_MEDIA; + } + + if (!Private->Slot[Slot].Initialized) { + return EFI_DEVICE_ERROR; + } + + Trb = SdMmcCreateTrb (Private, Slot, Packet, Event); + if (Trb == NULL) { + return EFI_OUT_OF_RESOURCES; + } + // + // Immediately return for async I/O. + // + if (Event != NULL) { + return EFI_SUCCESS; + } + + // + // Wait async I/O list is empty before execute sync I/O operation. + // + while (TRUE) { + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + if (IsListEmpty (&Private->Queue)) { + gBS->RestoreTPL (OldTpl); + break; + } + gBS->RestoreTPL (OldTpl); + } + + Status = SdMmcWaitTrbEnv (Private, Trb); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = SdMmcExecTrb (Private, Trb); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = SdMmcWaitTrbResult (Private, Trb); + if (EFI_ERROR (Status)) { + goto Done; + } + +Done: + if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) { + FreePages (Trb->AdmaDesc, Trb->AdmaPages); + } + + if (Trb != NULL) { + FreePool (Trb); + } + + return Status; +} + +/** + Used to retrieve next slot numbers supported by the SD controller. The function + returns information about all available slots (populated or not-populated). + + The GetNextSlot() function retrieves the next slot number on an SD controller. + If on input Slot is 0xFF, then the slot number of the first slot on the SD controller + is returned. + + If Slot is a slot number that was returned on a previous call to GetNextSlot(), then + the slot number of the next slot on the SD controller is returned. + + If Slot is not 0xFF and Slot was not returned on a previous call to GetNextSlot(), + EFI_INVALID_PARAMETER is returned. + + If Slot is the slot number of the last slot on the SD controller, then EFI_NOT_FOUND + is returned. + + @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance. + @param[in,out] Slot On input, a pointer to a slot number on the SD controller. + On output, a pointer to the next slot number on the SD controller. + An input value of 0xFF retrieves the first slot number on the SD + controller. + + @retval EFI_SUCCESS The next slot number on the SD controller was returned in Slot. + @retval EFI_NOT_FOUND There are no more slots on this SD controller. + @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a previous call + to GetNextSlot(). + +**/ +EFI_STATUS +EFIAPI +SdMmcPassThruGetNextSlot ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN OUT UINT8 *Slot + ) +{ + SD_MMC_HC_PRIVATE_DATA *Private; + UINT8 Index; + + if ((This == NULL) || (Slot == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Private = SD_MMC_HC_PRIVATE_FROM_THIS (This); + + if (*Slot == 0xFF) { + for (Index = 0; Index < SD_MMC_HC_MAX_SLOT; Index++) { + if (Private->Slot[Index].Enable) { + *Slot = Index; + Private->PreviousSlot = Index; + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; + } else if (*Slot == Private->PreviousSlot) { + for (Index = *Slot + 1; Index < SD_MMC_HC_MAX_SLOT; Index++) { + if (Private->Slot[Index].Enable) { + *Slot = Index; + Private->PreviousSlot = Index; + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; + } else { + return EFI_INVALID_PARAMETER; + } +} + +/** + Used to allocate and build a device path node for an SD card on the SD controller. + + The BuildDevicePath() function allocates and builds a single device node for the SD + card specified by Slot. + + If the SD card specified by Slot is not present on the SD controller, then EFI_NOT_FOUND + is returned. + + If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. + + If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES + is returned. + + Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of + DevicePath are initialized to describe the SD card specified by Slot, and EFI_SUCCESS is + returned. + + @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance. + @param[in] Slot Specifies the slot number of the SD card for which a device + path node is to be allocated and built. + @param[in,out] DevicePath A pointer to a single device path node that describes the SD + card specified by Slot. This function is responsible for + allocating the buffer DevicePath with the boot service + AllocatePool(). It is the caller's responsibility to free + DevicePath when the caller is finished with DevicePath. + + @retval EFI_SUCCESS The device path node that describes the SD card specified by + Slot was allocated and returned in DevicePath. + @retval EFI_NOT_FOUND The SD card specified by Slot does not exist on the SD controller. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath. + +**/ +EFI_STATUS +EFIAPI +SdMmcPassThruBuildDevicePath ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ) +{ + SD_MMC_HC_PRIVATE_DATA *Private; + SD_DEVICE_PATH *SdNode; + EMMC_DEVICE_PATH *EmmcNode; + + if ((This == NULL) || (DevicePath == NULL) || (Slot >= SD_MMC_HC_MAX_SLOT)) { + return EFI_INVALID_PARAMETER; + } + + Private = SD_MMC_HC_PRIVATE_FROM_THIS (This); + + if ((!Private->Slot[Slot].Enable) || (!Private->Slot[Slot].MediaPresent)) { + return EFI_NOT_FOUND; + } + + if (Private->Slot[Slot].CardType == SdCardType) { + SdNode = AllocateCopyPool (sizeof (SD_DEVICE_PATH), &mSdDpTemplate); + if (SdNode == NULL) { + return EFI_OUT_OF_RESOURCES; + } + SdNode->SlotNumber = Slot; + + *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) SdNode; + } else if (Private->Slot[Slot].CardType == EmmcCardType) { + EmmcNode = AllocateCopyPool (sizeof (EMMC_DEVICE_PATH), &mEmmcDpTemplate); + if (EmmcNode == NULL) { + return EFI_OUT_OF_RESOURCES; + } + EmmcNode->SlotNumber = Slot; + + *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) EmmcNode; + } else { + // + // Currently we only support SD and EMMC two device nodes. + // + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + This function retrieves an SD card slot number based on the input device path. + + The GetSlotNumber() function retrieves slot number for the SD card specified by + the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is returned. + + If DevicePath is not a device path node type that the SD Pass Thru driver supports, + EFI_UNSUPPORTED is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance. + @param[in] DevicePath A pointer to the device path node that describes a SD + card on the SD controller. + @param[out] Slot On return, points to the slot number of an SD card on + the SD controller. + + @retval EFI_SUCCESS SD card slot number is returned in Slot. + @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL. + @retval EFI_UNSUPPORTED DevicePath is not a device path node type that the SD + Pass Thru driver supports. + +**/ +EFI_STATUS +EFIAPI +SdMmcPassThruGetSlotNumber ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT8 *Slot + ) +{ + SD_MMC_HC_PRIVATE_DATA *Private; + SD_DEVICE_PATH *SdNode; + EMMC_DEVICE_PATH *EmmcNode; + UINT8 SlotNumber; + + if ((This == NULL) || (DevicePath == NULL) || (Slot == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Private = SD_MMC_HC_PRIVATE_FROM_THIS (This); + + // + // Check whether the DevicePath belongs to SD_DEVICE_PATH or EMMC_DEVICE_PATH + // + if ((DevicePath->Type != MESSAGING_DEVICE_PATH) || + ((DevicePath->SubType != MSG_SD_DP) && + (DevicePath->SubType != MSG_EMMC_DP)) || + (DevicePathNodeLength(DevicePath) != sizeof(SD_DEVICE_PATH)) || + (DevicePathNodeLength(DevicePath) != sizeof(EMMC_DEVICE_PATH))) { + return EFI_UNSUPPORTED; + } + + if (DevicePath->SubType == MSG_SD_DP) { + SdNode = (SD_DEVICE_PATH *) DevicePath; + SlotNumber = SdNode->SlotNumber; + } else { + EmmcNode = (EMMC_DEVICE_PATH *) DevicePath; + SlotNumber = EmmcNode->SlotNumber; + } + + if (SlotNumber >= SD_MMC_HC_MAX_SLOT) { + return EFI_NOT_FOUND; + } + + if (Private->Slot[SlotNumber].Enable) { + *Slot = SlotNumber; + return EFI_SUCCESS; + } else { + return EFI_NOT_FOUND; + } +} + +/** + Resets an SD card that is connected to the SD controller. + + The ResetDevice() function resets the SD card specified by Slot. + + If this SD controller does not support a device reset operation, EFI_UNSUPPORTED is + returned. + + If Slot is not in a valid slot number for this SD controller, EFI_INVALID_PARAMETER + is returned. + + If the device reset operation is completed, EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance. + @param[in] Slot Specifies the slot number of the SD card to be reset. + + @retval EFI_SUCCESS The SD card specified by Slot was reset. + @retval EFI_UNSUPPORTED The SD controller does not support a device reset operation. + @retval EFI_INVALID_PARAMETER Slot number is invalid. + @retval EFI_NO_MEDIA SD Device not present in the Slot. + @retval EFI_DEVICE_ERROR The reset command failed due to a device error + +**/ +EFI_STATUS +EFIAPI +SdMmcPassThruResetDevice ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot + ) +{ + SD_MMC_HC_PRIVATE_DATA *Private; + LIST_ENTRY *Link; + LIST_ENTRY *NextLink; + SD_MMC_HC_TRB *Trb; + EFI_TPL OldTpl; + + if (This == NULL) { + return EFI_INVALID_PARAMETER; + } + + Private = SD_MMC_HC_PRIVATE_FROM_THIS (This); + + if (!Private->Slot[Slot].Enable) { + return EFI_INVALID_PARAMETER; + } + + if (!Private->Slot[Slot].MediaPresent) { + return EFI_NO_MEDIA; + } + + if (!Private->Slot[Slot].Initialized) { + return EFI_DEVICE_ERROR; + } + // + // Free all async I/O requests in the queue + // + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + + for (Link = GetFirstNode (&Private->Queue); + !IsNull (&Private->Queue, Link); + Link = NextLink) { + NextLink = GetNextNode (&Private->Queue, Link); + RemoveEntryList (Link); + Trb = SD_MMC_HC_TRB_FROM_THIS (Link); + Trb->Packet->TransactionStatus = EFI_ABORTED; + gBS->SignalEvent (Trb->Event); + SdMmcFreeTrb (Trb); + } + + gBS->RestoreTPL (OldTpl); + + return EFI_SUCCESS; +} +
On Thu, Nov 17, 2016 at 12:05:23PM +0100, Marcin Wojtas wrote:
From: Jan Dąbroś jsd@semihalf.com
Import SdMmcPciHcDxe.c from tianocore/edk2 tree at revision a5991c8832c5: "IntelSiliconPkg: Add PCD for Graphics VBT FFS GUID" and rename it as MvSdMmcPciHcDxe.c
Because Marvell Xenon SD/MMC controller isn't fully compatible with SDHCI specification, it demands some quirks on generic driver during initialization and command processing. In order to achieve that, MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c is imported and adjusted correctly in following commit. Also in next patch's commit message necessary changes to generic driver are listed.
Xenon SD/MMC controller is present on Marvell Armada70x0 SoCs.
EFI_D_INFO, EFI_D_VERBOSE, EFI_D_WARN and EFI_D_ERROR are replaced with currently recommended values.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com
Drivers/SdMmc/MvSdMmcPciHcDxe.c | 1316 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 1316 insertions(+) create mode 100644 Drivers/SdMmc/MvSdMmcPciHcDxe.c
If you're forking the SdMmc driver to reimplement it, you need to copy the whole driver across, not just select pieces of it. If you don't want the maintenance cost of keeping a full forked driver alive, please look into whether your required changes could be conditionally incorporated either within the existing MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ driver or the EmbeddedPkg/Universal/MmcDxe/ one.
Regards,
Leif
diff --git a/Drivers/SdMmc/MvSdMmcPciHcDxe.c b/Drivers/SdMmc/MvSdMmcPciHcDxe.c new file mode 100644 index 0000000..5adbbcd --- /dev/null +++ b/Drivers/SdMmc/MvSdMmcPciHcDxe.c @@ -0,0 +1,1316 @@ +/** @file
- This driver is used to manage SD/MMC PCI host controllers which are compliance
- with SD Host Controller Simplified Specification version 3.00.
- It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include "SdMmcPciHcDxe.h"
+// +// Driver Global Variables +// +EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
- SdMmcPciHcDriverBindingSupported,
- SdMmcPciHcDriverBindingStart,
- SdMmcPciHcDriverBindingStop,
- 0x10,
- NULL,
- NULL
+};
+// +// Template for SD/MMC host controller private data. +// +SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
- SD_MMC_HC_PRIVATE_SIGNATURE, // Signature
- NULL, // ControllerHandle
- NULL, // PciIo
- { // PassThru
- sizeof (UINT32),
- SdMmcPassThruPassThru,
- SdMmcPassThruGetNextSlot,
- SdMmcPassThruBuildDevicePath,
- SdMmcPassThruGetSlotNumber,
- SdMmcPassThruResetDevice
- },
- 0, // PciAttributes
- 0, // PreviousSlot
- NULL, // TimerEvent
- NULL, // ConnectEvent
// Queue- INITIALIZE_LIST_HEAD_VARIABLE (gSdMmcPciHcTemplate.Queue),
- { // Slot
- {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0},
- {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}
- },
- { // Capability
- {0},
- },
- { // MaxCurrent
- 0,
- },
- 0 // ControllerVersion
+};
+SD_DEVICE_PATH mSdDpTemplate = {
- {
- MESSAGING_DEVICE_PATH,
- MSG_SD_DP,
- {
(UINT8) (sizeof (SD_DEVICE_PATH)),(UINT8) ((sizeof (SD_DEVICE_PATH)) >> 8)- }
- },
- 0
+};
+EMMC_DEVICE_PATH mEmmcDpTemplate = {
- {
- MESSAGING_DEVICE_PATH,
- MSG_EMMC_DP,
- {
(UINT8) (sizeof (EMMC_DEVICE_PATH)),(UINT8) ((sizeof (EMMC_DEVICE_PATH)) >> 8)- }
- },
- 0
+};
+// +// Prioritized function list to detect card type. +// User could add other card detection logic here. +// +CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = {
- EmmcIdentification,
- SdCardIdentification,
- NULL
+};
+/**
- The entry point for SD host controller driver, used to install this driver on the ImageHandle.
- @param[in] ImageHandle The firmware allocated handle for this driver image.
- @param[in] SystemTable Pointer to the EFI system table.
- @retval EFI_SUCCESS Driver loaded.
- @retval other Driver not loaded.
+**/ +EFI_STATUS +EFIAPI +InitializeSdMmcPciHcDxe (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
+{
- EFI_STATUS Status;
- Status = EfiLibInstallDriverBindingComponentName2 (
ImageHandle,SystemTable,&gSdMmcPciHcDriverBinding,ImageHandle,&gSdMmcPciHcComponentName,&gSdMmcPciHcComponentName2);- ASSERT_EFI_ERROR (Status);
- return Status;
+}
+/**
- Call back function when the timer event is signaled.
- @param[in] Event The Event this notify function registered to.
- @param[in] Context Pointer to the context data registered to the
Event.+**/ +VOID +EFIAPI +ProcessAsyncTaskList (
- IN EFI_EVENT Event,
- IN VOID* Context
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- LIST_ENTRY *Link;
- SD_MMC_HC_TRB *Trb;
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
- BOOLEAN InfiniteWait;
- EFI_EVENT TrbEvent;
- Private = (SD_MMC_HC_PRIVATE_DATA*)Context;
- //
- // Check if the first entry in the async I/O queue is done or not.
- //
- Status = EFI_SUCCESS;
- Trb = NULL;
- Link = GetFirstNode (&Private->Queue);
- if (!IsNull (&Private->Queue, Link)) {
- Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
- if (!Private->Slot[Trb->Slot].MediaPresent) {
Status = EFI_NO_MEDIA;goto Done;- }
- if (!Trb->Started) {
//// Check whether the cmd/data line is ready for transfer.//Status = SdMmcCheckTrbEnv (Private, Trb);if (!EFI_ERROR (Status)) {Trb->Started = TRUE;Status = SdMmcExecTrb (Private, Trb);if (EFI_ERROR (Status)) {goto Done;}} else {goto Done;}- }
- Status = SdMmcCheckTrbResult (Private, Trb);
- }
+Done:
- if ((Trb != NULL) && (Status == EFI_NOT_READY)) {
- Packet = Trb->Packet;
- if (Packet->Timeout == 0) {
InfiniteWait = TRUE;- } else {
InfiniteWait = FALSE;- }
- if ((!InfiniteWait) && (Trb->Timeout-- == 0)) {
RemoveEntryList (Link);Trb->Packet->TransactionStatus = EFI_TIMEOUT;TrbEvent = Trb->Event;SdMmcFreeTrb (Trb);DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p EFI_TIMEOUT\n", TrbEvent));gBS->SignalEvent (TrbEvent);return;- }
- }
- if ((Trb != NULL) && (Status != EFI_NOT_READY)) {
- RemoveEntryList (Link);
- Trb->Packet->TransactionStatus = Status;
- TrbEvent = Trb->Event;
- SdMmcFreeTrb (Trb);
- DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p with %r\n", TrbEvent, Status));
- gBS->SignalEvent (TrbEvent);
- }
- return;
+}
+/**
- Sd removable device enumeration callback function when the timer event is signaled.
- @param[in] Event The Event this notify function registered to.
- @param[in] Context Pointer to the context data registered to the
Event.+**/ +VOID +EFIAPI +SdMmcPciHcEnumerateDevice (
- IN EFI_EVENT Event,
- IN VOID* Context
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- EFI_STATUS Status;
- UINT8 Slot;
- BOOLEAN MediaPresent;
- UINT32 RoutineNum;
- CARD_TYPE_DETECT_ROUTINE *Routine;
- UINTN Index;
- LIST_ENTRY *Link;
- LIST_ENTRY *NextLink;
- SD_MMC_HC_TRB *Trb;
- EFI_TPL OldTpl;
- Private = (SD_MMC_HC_PRIVATE_DATA*)Context;
- for (Slot = 0; Slot < SD_MMC_HC_MAX_SLOT; Slot++) {
- if ((Private->Slot[Slot].Enable) && (Private->Slot[Slot].SlotType == RemovableSlot)) {
Status = SdMmcHcCardDetect (Private->PciIo, Slot, &MediaPresent);if ((Status == EFI_MEDIA_CHANGED) && !MediaPresent) {DEBUG ((DEBUG_INFO, "SdMmcPciHcEnumerateDevice: device disconnected at slot %d of pci %p\n", Slot, Private->PciIo));Private->Slot[Slot].MediaPresent = FALSE;Private->Slot[Slot].Initialized = FALSE;//// Signal all async task events at the slot with EFI_NO_MEDIA status.//OldTpl = gBS->RaiseTPL (TPL_NOTIFY);for (Link = GetFirstNode (&Private->Queue);!IsNull (&Private->Queue, Link);Link = NextLink) {NextLink = GetNextNode (&Private->Queue, Link);Trb = SD_MMC_HC_TRB_FROM_THIS (Link);if (Trb->Slot == Slot) {RemoveEntryList (Link);Trb->Packet->TransactionStatus = EFI_NO_MEDIA;gBS->SignalEvent (Trb->Event);SdMmcFreeTrb (Trb);}}gBS->RestoreTPL (OldTpl);//// Notify the upper layer the connect state change through ReinstallProtocolInterface.//gBS->ReinstallProtocolInterface (Private->ControllerHandle,&gEfiSdMmcPassThruProtocolGuid,&Private->PassThru,&Private->PassThru);}if ((Status == EFI_MEDIA_CHANGED) && MediaPresent) {DEBUG ((DEBUG_INFO, "SdMmcPciHcEnumerateDevice: device connected at slot %d of pci %p\n", Slot, Private->PciIo));//// Reset the specified slot of the SD/MMC Pci Host Controller//Status = SdMmcHcReset (Private->PciIo, Slot);if (EFI_ERROR (Status)) {continue;}//// Reinitialize slot and restart identification process for the new attached device//Status = SdMmcHcInitHost (Private->PciIo, Slot, Private->Capability[Slot]);if (EFI_ERROR (Status)) {continue;}Private->Slot[Slot].MediaPresent = TRUE;Private->Slot[Slot].Initialized = TRUE;RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);for (Index = 0; Index < RoutineNum; Index++) {Routine = &mCardTypeDetectRoutineTable[Index];if (*Routine != NULL) {Status = (*Routine) (Private, Slot);if (!EFI_ERROR (Status)) {break;}}}//// This card doesn't get initialized correctly.//if (Index == RoutineNum) {Private->Slot[Slot].Initialized = FALSE;}//// Notify the upper layer the connect state change through ReinstallProtocolInterface.//gBS->ReinstallProtocolInterface (Private->ControllerHandle,&gEfiSdMmcPassThruProtocolGuid,&Private->PassThru,&Private->PassThru);}- }
- }
- return;
+} +/**
- Tests to see if this driver supports a given controller. If a child device is provided,
- it further tests to see if this driver supports creating a handle for the specified child device.
- This function checks to see if the driver specified by This supports the device specified by
- ControllerHandle. Drivers will typically use the device path attached to
- ControllerHandle and/or the services from the bus I/O abstraction attached to
- ControllerHandle to determine if the driver supports ControllerHandle. This function
- may be called many times during platform initialization. In order to reduce boot times, the tests
- performed by this function must be very small, and take as little time as possible to execute. This
- function must not change the state of any hardware devices, and this function must be aware that the
- device specified by ControllerHandle may already be managed by the same driver or a
- different driver. This function must match its calls to AllocatePages() with FreePages(),
- AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
- Since ControllerHandle may have been previously started by the same driver, if a protocol is
- already in the opened state, then it must not be closed with CloseProtocol(). This is required
- to guarantee the state of ControllerHandle is not modified by this function.
- @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
- @param[in] ControllerHandle The handle of the controller to test. This handle
must support a protocol interface that suppliesan I/O abstraction to the driver.- @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This
parameter is ignored by device drivers, and is optional for busdrivers. For bus drivers, if this parameter is not NULL, thenthe bus driver must determine if the bus controller specifiedby ControllerHandle and the child controller specifiedby RemainingDevicePath are both supported by thisbus driver.- @retval EFI_SUCCESS The device specified by ControllerHandle and
RemainingDevicePath is supported by the driver specified by This.- @retval EFI_ALREADY_STARTED The device specified by ControllerHandle and
RemainingDevicePath is already being managed by the driverspecified by This.- @retval EFI_ACCESS_DENIED The device specified by ControllerHandle and
RemainingDevicePath is already being managed by a differentdriver or an application that requires exclusive access.Currently not implemented.- @retval EFI_UNSUPPORTED The device specified by ControllerHandle and
RemainingDevicePath is not supported by the driver specified by This.+**/ +EFI_STATUS +EFIAPI +SdMmcPciHcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
- )
+{
- EFI_STATUS Status;
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;
- EFI_PCI_IO_PROTOCOL *PciIo;
- PCI_TYPE00 PciData;
- PciIo = NULL;
- ParentDevicePath = NULL;
- //
- // SdPciHcDxe is a device driver, and should ingore the
- // "RemainingDevicePath" according to EFI spec.
- //
- Status = gBS->OpenProtocol (
Controller,&gEfiDevicePathProtocolGuid,(VOID *) &ParentDevicePath,This->DriverBindingHandle,Controller,EFI_OPEN_PROTOCOL_BY_DRIVER);- if (EFI_ERROR (Status)) {
- //
- // EFI_ALREADY_STARTED is also an error.
- //
- return Status;
- }
- //
- // Close the protocol because we don't use it here.
- //
- gBS->CloseProtocol (
Controller,&gEfiDevicePathProtocolGuid,This->DriverBindingHandle,Controller);- //
- // Now test the EfiPciIoProtocol.
- //
- Status = gBS->OpenProtocol (
Controller,&gEfiPciIoProtocolGuid,(VOID **) &PciIo,This->DriverBindingHandle,Controller,EFI_OPEN_PROTOCOL_BY_DRIVER);- if (EFI_ERROR (Status)) {
- return Status;
- }
- //
- // Now further check the PCI header: Base class (offset 0x08) and
- // Sub Class (offset 0x05). This controller should be an SD/MMC PCI
- // Host Controller.
- //
- Status = PciIo->Pci.Read (
PciIo,EfiPciIoWidthUint8,0,sizeof (PciData),&PciData);- if (EFI_ERROR (Status)) {
- gBS->CloseProtocol (
Controller,&gEfiPciIoProtocolGuid,This->DriverBindingHandle,Controller);- return EFI_UNSUPPORTED;
- }
- //
- // Since we already got the PciData, we can close protocol to avoid to carry it
- // on for multiple exit points.
- //
- gBS->CloseProtocol (
Controller,&gEfiPciIoProtocolGuid,This->DriverBindingHandle,Controller);- //
- // Examine SD PCI Host Controller PCI Configuration table fields.
- //
- if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) &&
(PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) &&((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) {- return EFI_SUCCESS;
- }
- return EFI_UNSUPPORTED;
+}
+/**
- Starts a device controller or a bus controller.
- The Start() function is designed to be invoked from the EFI boot service ConnectController().
- As a result, much of the error checking on the parameters to Start() has been moved into this
- common boot service. It is legal to call Start() from other locations,
- but the following calling restrictions must be followed or the system behavior will not be deterministic.
- ControllerHandle must be a valid EFI_HANDLE.
- If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
EFI_DEVICE_PATH_PROTOCOL.
- Prior to calling Start(), the Supported() function for the driver specified by This must
have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.- @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
- @param[in] ControllerHandle The handle of the controller to start. This handle
must support a protocol interface that suppliesan I/O abstraction to the driver.- @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This
parameter is ignored by device drivers, and is optional for busdrivers. For a bus driver, if this parameter is NULL, then handlesfor all the children of Controller are created by this driver.If this parameter is not NULL and the first Device Path Node isnot the End of Device Path Node, then only the handle for thechild device specified by the first Device Path Node ofRemainingDevicePath is created by this driver.If the first Device Path Node of RemainingDevicePath isthe End of Device Path Node, no child handle is created by thisdriver.- @retval EFI_SUCCESS The device was started.
- @retval EFI_DEVICE_ERROR The device could not be started due to a device error.Currently not implemented.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
- @retval Others The driver failded to start the device.
+**/ +EFI_STATUS +EFIAPI +SdMmcPciHcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
- )
+{
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Supports;
- UINT64 PciAttributes;
- UINT8 SlotNum;
- UINT8 FirstBar;
- UINT8 Slot;
- UINT8 Index;
- CARD_TYPE_DETECT_ROUTINE *Routine;
- UINT32 RoutineNum;
- BOOLEAN MediaPresent;
- BOOLEAN Support64BitDma;
- DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
- //
- // Open PCI I/O Protocol and save pointer to open protocol
- // in private data area.
- //
- PciIo = NULL;
- Status = gBS->OpenProtocol (
Controller,&gEfiPciIoProtocolGuid,(VOID **) &PciIo,This->DriverBindingHandle,Controller,EFI_OPEN_PROTOCOL_BY_DRIVER);- if (EFI_ERROR (Status)) {
- return Status;
- }
- //
- // Enable the SD Host Controller MMIO space
- //
- Private = NULL;
- Status = PciIo->Attributes (
PciIo,EfiPciIoAttributeOperationGet,0,&PciAttributes);- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Status = PciIo->Attributes (
PciIo,EfiPciIoAttributeOperationSupported,0,&Supports);- if (!EFI_ERROR (Status)) {
- Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
- Status = PciIo->Attributes (
PciIo,EfiPciIoAttributeOperationEnable,Supports,NULL);- } else {
- goto Done;
- }
- Private = AllocateCopyPool (sizeof (SD_MMC_HC_PRIVATE_DATA), &gSdMmcPciHcTemplate);
- if (Private == NULL) {
- Status = EFI_OUT_OF_RESOURCES;
- goto Done;
- }
- Private->ControllerHandle = Controller;
- Private->PciIo = PciIo;
- Private->PciAttributes = PciAttributes;
- InitializeListHead (&Private->Queue);
- //
- // Get SD/MMC Pci Host Controller Slot info
- //
- Status = SdMmcHcGetSlotInfo (PciIo, &FirstBar, &SlotNum);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Support64BitDma = TRUE;
- for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) {
- Private->Slot[Slot].Enable = TRUE;
- Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]);
- if (EFI_ERROR (Status)) {
continue;- }
- DumpCapabilityReg (Slot, &Private->Capability[Slot]);
- Support64BitDma &= Private->Capability[Slot].SysBus64;
- Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]);
- if (EFI_ERROR (Status)) {
continue;- }
- Private->Slot[Slot].SlotType = Private->Capability[Slot].SlotType;
- if ((Private->Slot[Slot].SlotType != RemovableSlot) && (Private->Slot[Slot].SlotType != EmbeddedSlot)) {
DEBUG ((DEBUG_INFO, "SdMmcPciHcDxe doesn't support the slot type [%d]!!!\n", Private->Slot[Slot].SlotType));continue;- }
- //
- // Reset the specified slot of the SD/MMC Pci Host Controller
- //
- Status = SdMmcHcReset (PciIo, Slot);
- if (EFI_ERROR (Status)) {
continue;- }
- //
- // Check whether there is a SD/MMC card attached
- //
- Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent);
- if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) {
continue;- } else if (!MediaPresent) {
DEBUG ((DEBUG_ERROR, "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n", Slot));continue;- }
- Status = SdMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]);
- if (EFI_ERROR (Status)) {
continue;- }
- Private->Slot[Slot].MediaPresent = TRUE;
- Private->Slot[Slot].Initialized = TRUE;
- RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
- for (Index = 0; Index < RoutineNum; Index++) {
Routine = &mCardTypeDetectRoutineTable[Index];if (*Routine != NULL) {Status = (*Routine) (Private, Slot);if (!EFI_ERROR (Status)) {break;}}- }
- //
- // This card doesn't get initialized correctly.
- //
- if (Index == RoutineNum) {
Private->Slot[Slot].Initialized = FALSE;- }
- }
- //
- // Enable 64-bit DMA support in the PCI layer if this controller
- // supports it.
- //
- if (Support64BitDma) {
- Status = PciIo->Attributes (
PciIo,EfiPciIoAttributeOperationEnable,EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,NULL);- if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "SdMmcPciHcDriverBindingStart: failed to enable 64-bit DMA (%r)\n", Status));- }
- }
- //
- // Start the asynchronous I/O monitor
- //
- Status = gBS->CreateEvent (
EVT_TIMER | EVT_NOTIFY_SIGNAL,TPL_NOTIFY,ProcessAsyncTaskList,Private,&Private->TimerEvent);- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, SD_MMC_HC_ASYNC_TIMER);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- //
- // Start the Sd removable device connection enumeration
- //
- Status = gBS->CreateEvent (
EVT_TIMER | EVT_NOTIFY_SIGNAL,TPL_CALLBACK,SdMmcPciHcEnumerateDevice,Private,&Private->ConnectEvent);- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Status = gBS->SetTimer (Private->ConnectEvent, TimerPeriodic, SD_MMC_HC_ENUM_TIMER);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Status = gBS->InstallMultipleProtocolInterfaces (
&Controller,&gEfiSdMmcPassThruProtocolGuid,&(Private->PassThru),NULL);- DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: %r End on %x\n", Status, Controller));
+Done:
- if (EFI_ERROR (Status)) {
- if ((Private != NULL) && (Private->PciAttributes != 0)) {
//// Restore original PCI attributes//PciIo->Attributes (PciIo,EfiPciIoAttributeOperationSet,Private->PciAttributes,NULL);- }
- gBS->CloseProtocol (
Controller,&gEfiPciIoProtocolGuid,This->DriverBindingHandle,Controller);- if ((Private != NULL) && (Private->TimerEvent != NULL)) {
gBS->CloseEvent (Private->TimerEvent);- }
- if ((Private != NULL) && (Private->ConnectEvent != NULL)) {
gBS->CloseEvent (Private->ConnectEvent);- }
- if (Private != NULL) {
FreePool (Private);- }
- }
- return Status;
+}
+/**
- Stops a device controller or a bus controller.
- The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
- As a result, much of the error checking on the parameters to Stop() has been moved
- into this common boot service. It is legal to call Stop() from other locations,
- but the following calling restrictions must be followed or the system behavior will not be deterministic.
- ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
same driver's Start() function.
- The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
EFI_HANDLE. In addition, all of these handles must have been created in this driver'sStart() function, and the Start() function must have called OpenProtocol() onControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.- @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
- @param[in] ControllerHandle A handle to the device being stopped. The handle must
support a bus specific I/O protocol for the driverto use to stop the device.- @param[in] NumberOfChildren The number of child device handles in ChildHandleBuffer.
- @param[in] ChildHandleBuffer An array of child handles to be freed. May be NULL
if NumberOfChildren is 0.- @retval EFI_SUCCESS The device was stopped.
- @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error.
+**/ +EFI_STATUS +EFIAPI +SdMmcPciHcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
- )
+{
- EFI_STATUS Status;
- EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru;
- SD_MMC_HC_PRIVATE_DATA *Private;
- EFI_PCI_IO_PROTOCOL *PciIo;
- LIST_ENTRY *Link;
- LIST_ENTRY *NextLink;
- SD_MMC_HC_TRB *Trb;
- DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStop: Start\n"));
- Status = gBS->OpenProtocol (
Controller,&gEfiSdMmcPassThruProtocolGuid,(VOID**) &PassThru,This->DriverBindingHandle,Controller,EFI_OPEN_PROTOCOL_GET_PROTOCOL);- if (EFI_ERROR (Status)) {
- return Status;
- }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
- //
- // Close Non-Blocking timer and free Task list.
- //
- if (Private->TimerEvent != NULL) {
- gBS->CloseEvent (Private->TimerEvent);
- Private->TimerEvent = NULL;
- }
- if (Private->ConnectEvent != NULL) {
- gBS->CloseEvent (Private->ConnectEvent);
- Private->ConnectEvent = NULL;
- }
- //
- // As the timer is closed, there is no needs to use TPL lock to
- // protect the critical region "queue".
- //
- for (Link = GetFirstNode (&Private->Queue);
!IsNull (&Private->Queue, Link);Link = NextLink) {- NextLink = GetNextNode (&Private->Queue, Link);
- RemoveEntryList (Link);
- Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
- Trb->Packet->TransactionStatus = EFI_ABORTED;
- gBS->SignalEvent (Trb->Event);
- SdMmcFreeTrb (Trb);
- }
- //
- // Uninstall Block I/O protocol from the device handle
- //
- Status = gBS->UninstallProtocolInterface (
Controller,&gEfiSdMmcPassThruProtocolGuid,&(Private->PassThru));- if (EFI_ERROR (Status)) {
- return Status;
- }
- gBS->CloseProtocol (
Controller,&gEfiPciIoProtocolGuid,This->DriverBindingHandle,Controller);- //
- // Restore original PCI attributes
- //
- PciIo = Private->PciIo;
- Status = PciIo->Attributes (
PciIo,EfiPciIoAttributeOperationSet,Private->PciAttributes,NULL);- ASSERT_EFI_ERROR (Status);
- FreePool (Private);
- DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStop: End with %r\n", Status));
- return Status;
+}
+/**
- Sends SD command to an SD card that is attached to the SD controller.
- The PassThru() function sends the SD command specified by Packet to the SD card
- specified by Slot.
- If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.
- If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
- If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER
- is returned.
- If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
- EFI_INVALID_PARAMETER is returned.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot The slot number of the SD card to send the command to.
- @param[in,out] Packet A pointer to the SD command data structure.
- @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
not NULL, then nonblocking I/O is performed, and Eventwill be signaled when the Packet completes.- @retval EFI_SUCCESS The SD Command Packet was sent by the host.
- @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD
command Packet.- @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
- @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
OutDataBuffer are NULL.- @retval EFI_NO_MEDIA SD Device not present in the Slot.
- @retval EFI_UNSUPPORTED The command described by the SD Command Packet is not
supported by the host controller.- @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the
limit supported by SD card ( i.e. if the number of bytesexceed the Last LBA).+**/ +EFI_STATUS +EFIAPI +SdMmcPassThruPassThru (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN EFI_EVENT Event OPTIONAL
- )
+{
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_MMC_HC_TRB *Trb;
- EFI_TPL OldTpl;
- if ((This == NULL) || (Packet == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if (!Private->Slot[Slot].Enable) {
- return EFI_INVALID_PARAMETER;
- }
- if (!Private->Slot[Slot].MediaPresent) {
- return EFI_NO_MEDIA;
- }
- if (!Private->Slot[Slot].Initialized) {
- return EFI_DEVICE_ERROR;
- }
- Trb = SdMmcCreateTrb (Private, Slot, Packet, Event);
- if (Trb == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
- //
- // Immediately return for async I/O.
- //
- if (Event != NULL) {
- return EFI_SUCCESS;
- }
- //
- // Wait async I/O list is empty before execute sync I/O operation.
- //
- while (TRUE) {
- OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
- if (IsListEmpty (&Private->Queue)) {
gBS->RestoreTPL (OldTpl);break;- }
- gBS->RestoreTPL (OldTpl);
- }
- Status = SdMmcWaitTrbEnv (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Status = SdMmcExecTrb (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Status = SdMmcWaitTrbResult (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
+Done:
- if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
- FreePages (Trb->AdmaDesc, Trb->AdmaPages);
- }
- if (Trb != NULL) {
- FreePool (Trb);
- }
- return Status;
+}
+/**
- Used to retrieve next slot numbers supported by the SD controller. The function
- returns information about all available slots (populated or not-populated).
- The GetNextSlot() function retrieves the next slot number on an SD controller.
- If on input Slot is 0xFF, then the slot number of the first slot on the SD controller
- is returned.
- If Slot is a slot number that was returned on a previous call to GetNextSlot(), then
- the slot number of the next slot on the SD controller is returned.
- If Slot is not 0xFF and Slot was not returned on a previous call to GetNextSlot(),
- EFI_INVALID_PARAMETER is returned.
- If Slot is the slot number of the last slot on the SD controller, then EFI_NOT_FOUND
- is returned.
- @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
- @param[in,out] Slot On input, a pointer to a slot number on the SD controller.
On output, a pointer to the next slot number on the SD controller.An input value of 0xFF retrieves the first slot number on the SDcontroller.- @retval EFI_SUCCESS The next slot number on the SD controller was returned in Slot.
- @retval EFI_NOT_FOUND There are no more slots on this SD controller.
- @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a previous call
to GetNextSlot().+**/ +EFI_STATUS +EFIAPI +SdMmcPassThruGetNextSlot (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN OUT UINT8 *Slot
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- UINT8 Index;
- if ((This == NULL) || (Slot == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if (*Slot == 0xFF) {
- for (Index = 0; Index < SD_MMC_HC_MAX_SLOT; Index++) {
if (Private->Slot[Index].Enable) {*Slot = Index;Private->PreviousSlot = Index;return EFI_SUCCESS;}- }
- return EFI_NOT_FOUND;
- } else if (*Slot == Private->PreviousSlot) {
- for (Index = *Slot + 1; Index < SD_MMC_HC_MAX_SLOT; Index++) {
if (Private->Slot[Index].Enable) {*Slot = Index;Private->PreviousSlot = Index;return EFI_SUCCESS;}- }
- return EFI_NOT_FOUND;
- } else {
- return EFI_INVALID_PARAMETER;
- }
+}
+/**
- Used to allocate and build a device path node for an SD card on the SD controller.
- The BuildDevicePath() function allocates and builds a single device node for the SD
- card specified by Slot.
- If the SD card specified by Slot is not present on the SD controller, then EFI_NOT_FOUND
- is returned.
- If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
- If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES
- is returned.
- Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of
- DevicePath are initialized to describe the SD card specified by Slot, and EFI_SUCCESS is
- returned.
- @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot Specifies the slot number of the SD card for which a device
path node is to be allocated and built.- @param[in,out] DevicePath A pointer to a single device path node that describes the SD
card specified by Slot. This function is responsible forallocating the buffer DevicePath with the boot serviceAllocatePool(). It is the caller's responsibility to freeDevicePath when the caller is finished with DevicePath.- @retval EFI_SUCCESS The device path node that describes the SD card specified by
Slot was allocated and returned in DevicePath.- @retval EFI_NOT_FOUND The SD card specified by Slot does not exist on the SD controller.
- @retval EFI_INVALID_PARAMETER DevicePath is NULL.
- @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath.
+**/ +EFI_STATUS +EFIAPI +SdMmcPassThruBuildDevicePath (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_DEVICE_PATH *SdNode;
- EMMC_DEVICE_PATH *EmmcNode;
- if ((This == NULL) || (DevicePath == NULL) || (Slot >= SD_MMC_HC_MAX_SLOT)) {
- return EFI_INVALID_PARAMETER;
- }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if ((!Private->Slot[Slot].Enable) || (!Private->Slot[Slot].MediaPresent)) {
- return EFI_NOT_FOUND;
- }
- if (Private->Slot[Slot].CardType == SdCardType) {
- SdNode = AllocateCopyPool (sizeof (SD_DEVICE_PATH), &mSdDpTemplate);
- if (SdNode == NULL) {
return EFI_OUT_OF_RESOURCES;- }
- SdNode->SlotNumber = Slot;
- *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) SdNode;
- } else if (Private->Slot[Slot].CardType == EmmcCardType) {
- EmmcNode = AllocateCopyPool (sizeof (EMMC_DEVICE_PATH), &mEmmcDpTemplate);
- if (EmmcNode == NULL) {
return EFI_OUT_OF_RESOURCES;- }
- EmmcNode->SlotNumber = Slot;
- *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) EmmcNode;
- } else {
- //
- // Currently we only support SD and EMMC two device nodes.
- //
- return EFI_NOT_FOUND;
- }
- return EFI_SUCCESS;
+}
+/**
- This function retrieves an SD card slot number based on the input device path.
- The GetSlotNumber() function retrieves slot number for the SD card specified by
- the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is returned.
- If DevicePath is not a device path node type that the SD Pass Thru driver supports,
- EFI_UNSUPPORTED is returned.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] DevicePath A pointer to the device path node that describes a SD
card on the SD controller.- @param[out] Slot On return, points to the slot number of an SD card on
the SD controller.- @retval EFI_SUCCESS SD card slot number is returned in Slot.
- @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL.
- @retval EFI_UNSUPPORTED DevicePath is not a device path node type that the SD
Pass Thru driver supports.+**/ +EFI_STATUS +EFIAPI +SdMmcPassThruGetSlotNumber (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
- OUT UINT8 *Slot
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_DEVICE_PATH *SdNode;
- EMMC_DEVICE_PATH *EmmcNode;
- UINT8 SlotNumber;
- if ((This == NULL) || (DevicePath == NULL) || (Slot == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- //
- // Check whether the DevicePath belongs to SD_DEVICE_PATH or EMMC_DEVICE_PATH
- //
- if ((DevicePath->Type != MESSAGING_DEVICE_PATH) ||
((DevicePath->SubType != MSG_SD_DP) &&(DevicePath->SubType != MSG_EMMC_DP)) ||(DevicePathNodeLength(DevicePath) != sizeof(SD_DEVICE_PATH)) ||(DevicePathNodeLength(DevicePath) != sizeof(EMMC_DEVICE_PATH))) {- return EFI_UNSUPPORTED;
- }
- if (DevicePath->SubType == MSG_SD_DP) {
- SdNode = (SD_DEVICE_PATH *) DevicePath;
- SlotNumber = SdNode->SlotNumber;
- } else {
- EmmcNode = (EMMC_DEVICE_PATH *) DevicePath;
- SlotNumber = EmmcNode->SlotNumber;
- }
- if (SlotNumber >= SD_MMC_HC_MAX_SLOT) {
- return EFI_NOT_FOUND;
- }
- if (Private->Slot[SlotNumber].Enable) {
- *Slot = SlotNumber;
- return EFI_SUCCESS;
- } else {
- return EFI_NOT_FOUND;
- }
+}
+/**
- Resets an SD card that is connected to the SD controller.
- The ResetDevice() function resets the SD card specified by Slot.
- If this SD controller does not support a device reset operation, EFI_UNSUPPORTED is
- returned.
- If Slot is not in a valid slot number for this SD controller, EFI_INVALID_PARAMETER
- is returned.
- If the device reset operation is completed, EFI_SUCCESS is returned.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot Specifies the slot number of the SD card to be reset.
- @retval EFI_SUCCESS The SD card specified by Slot was reset.
- @retval EFI_UNSUPPORTED The SD controller does not support a device reset operation.
- @retval EFI_INVALID_PARAMETER Slot number is invalid.
- @retval EFI_NO_MEDIA SD Device not present in the Slot.
- @retval EFI_DEVICE_ERROR The reset command failed due to a device error
+**/ +EFI_STATUS +EFIAPI +SdMmcPassThruResetDevice (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- LIST_ENTRY *Link;
- LIST_ENTRY *NextLink;
- SD_MMC_HC_TRB *Trb;
- EFI_TPL OldTpl;
- if (This == NULL) {
- return EFI_INVALID_PARAMETER;
- }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if (!Private->Slot[Slot].Enable) {
- return EFI_INVALID_PARAMETER;
- }
- if (!Private->Slot[Slot].MediaPresent) {
- return EFI_NO_MEDIA;
- }
- if (!Private->Slot[Slot].Initialized) {
- return EFI_DEVICE_ERROR;
- }
- //
- // Free all async I/O requests in the queue
- //
- OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
- for (Link = GetFirstNode (&Private->Queue);
!IsNull (&Private->Queue, Link);Link = NextLink) {- NextLink = GetNextNode (&Private->Queue, Link);
- RemoveEntryList (Link);
- Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
- Trb->Packet->TransactionStatus = EFI_ABORTED;
- gBS->SignalEvent (Trb->Event);
- SdMmcFreeTrb (Trb);
- }
- gBS->RestoreTPL (OldTpl);
- return EFI_SUCCESS;
+}
-- 1.8.3.1
Hi Leif,
2016-11-17 12:45 GMT+01:00 Leif Lindholm leif.lindholm@linaro.org:
On Thu, Nov 17, 2016 at 12:05:23PM +0100, Marcin Wojtas wrote:
From: Jan Dąbroś jsd@semihalf.com
Import SdMmcPciHcDxe.c from tianocore/edk2 tree at revision a5991c8832c5: "IntelSiliconPkg: Add PCD for Graphics VBT FFS GUID" and rename it as MvSdMmcPciHcDxe.c
Because Marvell Xenon SD/MMC controller isn't fully compatible with SDHCI specification, it demands some quirks on generic driver during initialization and command processing. In order to achieve that, MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c is imported and adjusted correctly in following commit. Also in next patch's commit message necessary changes to generic driver are listed.
Xenon SD/MMC controller is present on Marvell Armada70x0 SoCs.
EFI_D_INFO, EFI_D_VERBOSE, EFI_D_WARN and EFI_D_ERROR are replaced with currently recommended values.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com
Drivers/SdMmc/MvSdMmcPciHcDxe.c | 1316 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 1316 insertions(+) create mode 100644 Drivers/SdMmc/MvSdMmcPciHcDxe.c
If you're forking the SdMmc driver to reimplement it, you need to copy the whole driver across, not just select pieces of it. If you don't want the maintenance cost of keeping a full forked driver alive, please look into whether your required changes could be conditionally incorporated either within the existing MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ driver or the EmbeddedPkg/Universal/MmcDxe/ one.
Ok, sure. We tried various ways for submission of the quirks to the block layer (Bus/Sd/SdDxe/SdBlockIo.c / MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c), but all were rejected. Forking entire Pci/SdMmcPciHcDxe/ and not touching upper layers is IMO easier and cleaner, so if you don't mind, the import will be done in next spin.
Best regards, Marcin
From: Jan Dąbroś jsd@semihalf.com
Because Xenon SD/MMC controller isn't fully compatible with SDHC, it demands some quirks on generic driver during initialization and command processing. Below are listed necessary changes:
- Add Xenon-specific init sequence - registers related to PHY - Add Xenon-specific command processing sequence: * Because DMA isn't yet supported, we use PIO mode for DATA transfers. It brings necessity of sending SD_STOP_TRANSMISSION for multiple-block transfers and polling for card status after write data transfers, which aren't implemented in edk2's SdMmc stack * Command processing sequence for Xenon controller have also other quirks regarding flow of operation (please see comments in code) and TRB-oriented method isn't applicable in this case.
Beside above, MvSdMmcPciHcDxe driver is compatible with SdMmcPciHcDxe.
Two files containing Xenon-specific functions and defines were added.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Drivers/SdMmc/MvSdMmcPciHcDxe.c | 636 +++++++++++++++++++++++++++++++----- Drivers/SdMmc/MvSdMmcPciHcDxe.inf | 75 +++++ Drivers/SdMmc/XenonSdhci.c | 661 ++++++++++++++++++++++++++++++++++++++ Drivers/SdMmc/XenonSdhci.h | 278 ++++++++++++++++ 4 files changed, 1564 insertions(+), 86 deletions(-) mode change 100644 => 100755 Drivers/SdMmc/MvSdMmcPciHcDxe.c create mode 100644 Drivers/SdMmc/MvSdMmcPciHcDxe.inf create mode 100755 Drivers/SdMmc/XenonSdhci.c create mode 100644 Drivers/SdMmc/XenonSdhci.h
diff --git a/Drivers/SdMmc/MvSdMmcPciHcDxe.c b/Drivers/SdMmc/MvSdMmcPciHcDxe.c old mode 100644 new mode 100755 index 5adbbcd..ef771bb --- a/Drivers/SdMmc/MvSdMmcPciHcDxe.c +++ b/Drivers/SdMmc/MvSdMmcPciHcDxe.c @@ -5,6 +5,8 @@ It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2016, Marvell. All rights reserved.<BR> + This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -15,7 +17,7 @@
**/
-#include "SdMmcPciHcDxe.h" +#include "XenonSdhci.h"
// // Driver Global Variables @@ -520,13 +522,10 @@ SdMmcPciHcDriverBindingStart ( EFI_PCI_IO_PROTOCOL *PciIo; UINT64 Supports; UINT64 PciAttributes; - UINT8 SlotNum; - UINT8 FirstBar; UINT8 Slot; UINT8 Index; CARD_TYPE_DETECT_ROUTINE *Routine; UINT32 RoutineNum; - BOOLEAN MediaPresent; BOOLEAN Support64BitDma;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); @@ -593,26 +592,32 @@ SdMmcPciHcDriverBindingStart ( Private->PciAttributes = PciAttributes; InitializeListHead (&Private->Queue);
- // - // Get SD/MMC Pci Host Controller Slot info - // - Status = SdMmcHcGetSlotInfo (PciIo, &FirstBar, &SlotNum); - if (EFI_ERROR (Status)) { - goto Done; - } - Support64BitDma = TRUE; - for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) { + for (Slot = 0; Slot < (XENON_MMC_SLOT_ID_HYPERION + 1); Slot++) { Private->Slot[Slot].Enable = TRUE;
Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]); if (EFI_ERROR (Status)) { continue; } - DumpCapabilityReg (Slot, &Private->Capability[Slot]);
Support64BitDma &= Private->Capability[Slot].SysBus64;
+ // + // Override capabilities structure - only 4 Bit width bus is supported + // by HW and also force using SDR25 mode + // + Private->Capability[Slot].Sdr104 = 0; + Private->Capability[Slot].Ddr50 = 0; + Private->Capability[Slot].Sdr50 = 0; + Private->Capability[Slot].BusWidth8 = 0; + + if (Private->Capability[Slot].BaseClkFreq == 0) { + Private->Capability[Slot].BaseClkFreq = 0xff; + } + + DumpCapabilityReg (Slot, &Private->Capability[Slot]); + Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); if (EFI_ERROR (Status)) { continue; @@ -624,28 +629,8 @@ SdMmcPciHcDriverBindingStart ( continue; }
- // - // Reset the specified slot of the SD/MMC Pci Host Controller - // - Status = SdMmcHcReset (PciIo, Slot); - if (EFI_ERROR (Status)) { - continue; - } - // - // Check whether there is a SD/MMC card attached - // - Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent); - if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) { - continue; - } else if (!MediaPresent) { - DEBUG ((DEBUG_ERROR, "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n", Slot)); - continue; - } - - Status = SdMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]); - if (EFI_ERROR (Status)) { - continue; - } + // Perform Xenon-specific init sequence + XenonInit (Private);
Private->Slot[Slot].MediaPresent = TRUE; Private->Slot[Slot].Initialized = TRUE; @@ -889,6 +874,220 @@ SdMmcPciHcDriverBindingStop ( }
/** + Check if card is ready for next data transfer by reading its status. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance. + @param[in] Slot The slot number of the device to send the command to. + @param[in] Rca The relative device address of addressed device. + @param[in] Timeout The timeout in miliseconds. + + @retval EFI_SUCCESS Card is ready for next data transfer. + @retval EFI_DEVICE_ERROR Card status is erroneous. + @retval EFI_TIMEOUT Card is busy. + +**/ +STATIC +EFI_STATUS +SdMmcIsReady ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + IN UINT16 Rca, + IN UINTN Timeout + ) +{ + EFI_STATUS Status; + UINT32 DevStatus; + + do { + Status = SdCardSendStatus (This, Slot, Rca, &DevStatus); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Cannot read SD status\n")); + return Status; + } + + // Check device status + if ((DevStatus & (1 << 8)) && (DevStatus & (0xf << 9)) != (7 << 9)) { + break; + } else if (DevStatus & ~0x0206BF7F) { + DEBUG ((DEBUG_ERROR, "SD Status error\n")); + return EFI_DEVICE_ERROR; + } + + gBS->Stall (1000); + } while (Timeout--); + + if (Timeout <= 0) { + DEBUG ((DEBUG_ERROR, "SD Status timeout\n")); + return EFI_TIMEOUT; + } + + if (DevStatus & (1 << 7)) { + DEBUG ((DEBUG_ERROR, "SD switch error\n")); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +CheckParameters ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet, + IN UINT8 Slot + ) +{ + SD_MMC_HC_PRIVATE_DATA *Private; + + Private = SD_MMC_HC_PRIVATE_FROM_THIS (This); + + if ((This == NULL) || (Packet == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) { + return EFI_INVALID_PARAMETER; + } + + if (!Private->Slot[Slot].Enable) { + return EFI_INVALID_PARAMETER; + } + + if (!Private->Slot[Slot].MediaPresent) { + return EFI_NO_MEDIA; + } + + // Currently we don't support SDIO + if (Packet->SdMmcCmdBlk->CommandIndex == SDIO_SEND_OP_COND) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** + Send command SD_STOP_TRANSMISSION to stop multiple block transfer. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance. + @param[in] Slot The slot number of the device to send the command to. + + @retval EFI_SUCCESS The request is executed successfully. + @retval Others The request could not be executed successfully. + +**/ +STATIC +EFI_STATUS +SdMmcSendStopTransmission ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot + ) +{ + EFI_STATUS Status; + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = 2500 * 1000; // SD generic timeout + + SdMmcCmdBlk.CommandIndex = SD_STOP_TRANSMISSION; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b; + SdMmcCmdBlk.CommandArgument = 0; + + Status = This->PassThru (This, Slot, &Packet, NULL); + + return Status; +} + +STATIC +EFI_STATUS +WaitForInhibit ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet, + IN UINT8 Slot, + IN BOOLEAN DataTransfer + ) +{ + UINT32 Mask, PresentState, Time = 0; + UINT32 CmdTimeout = XENON_MMC_CMD_DEFAULT_TIMEOUT; + + if (Packet->SdMmcCmdBlk != NULL) { + Mask = BIT0; // SDHCI_CMD_INHIBIT + } + + if (DataTransfer != FALSE) { + Mask = BIT1; // SDHCI_DATA_INHIBIT + } + + // + // We shouldn't wait for data inhibit for stop commands, even + // though they might use busy signaling + // + if (Packet->SdMmcCmdBlk->CommandIndex == SD_STOP_TRANSMISSION) + Mask &= ~BIT1; + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_PRESENT_STATE, + TRUE, + sizeof (PresentState), + &PresentState + ); + + while (PresentState & Mask) { + if (Time >= CmdTimeout) { + if (2 * CmdTimeout <= XENON_MMC_CMD_MAX_TIMEOUT) { + CmdTimeout += CmdTimeout; + } else { + if (Packet->SdMmcCmdBlk != NULL) { + XenonReset (Private, Slot, 0x02); // CMD reset + } + + if (DataTransfer) { + XenonReset (Private, Slot, 0x04); // DATA reset + } + + DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Timeout...\n")); + + return EFI_TIMEOUT; + } + } + + Time++; + gBS->Stall (1000); + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_PRESENT_STATE, + TRUE, + sizeof (PresentState), + &PresentState + ); + } + + return EFI_SUCCESS; +} + +// Variable to store current card's Rca - used in polling card status +STATIC UINT16 CurrRca = 0; + +/** Sends SD command to an SD card that is attached to the SD controller.
The PassThru() function sends the SD command specified by Packet to the SD card @@ -934,86 +1133,351 @@ SdMmcPassThruPassThru ( IN EFI_EVENT Event OPTIONAL ) { - EFI_STATUS Status; - SD_MMC_HC_PRIVATE_DATA *Private; - SD_MMC_HC_TRB *Trb; - EFI_TPL OldTpl; + EFI_STATUS Status; + SD_MMC_HC_PRIVATE_DATA *Private; + INTN Ret; + UINTN *Data, DataLen, Index; + UINT32 Argument, Response[4], Retry, Stat, Mask; + UINT16 BlockSize, BlkCount; + UINT16 Cmd, IntStatus, TimeoutCtrl, Mode, BlkSizeReg; + BOOLEAN MultiFlag = FALSE, SetRcaFlag = FALSE, Read = FALSE; + BOOLEAN DataTransfer; + + + Data = NULL; + DataLen = 0; + Retry = 1000; + Stat = 0; + Ret = 0; + BlockSize = 0x200; + BlkCount = 0; + + Status = CheckParameters (This, Packet, Slot); + if (EFI_ERROR(Status)) { + return Status; + }
- if ((This == NULL) || (Packet == NULL)) { - return EFI_INVALID_PARAMETER; + Private = SD_MMC_HC_PRIVATE_FROM_THIS (This); + + // + // Mark if this is multiblock data transfer since some special + // acctions must be taken in such circumstances, i.e. it's necessary + // to send SD_STOP_TRANSMISSION command. + // + if (Packet->SdMmcCmdBlk->CommandIndex == SD_WRITE_MULTIPLE_BLOCK || + Packet->SdMmcCmdBlk->CommandIndex == SD_READ_MULTIPLE_BLOCK) { + MultiFlag = TRUE; }
- if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) { - return EFI_INVALID_PARAMETER; + // + // Mark if this is command to set new relative card address (RCA), + // since it's necessary to have updated copy of current RCA in this + // layer - used in checking card status. + // + if (Packet->SdMmcCmdBlk->CommandIndex == SD_SET_RELATIVE_ADDR) { + SetRcaFlag = TRUE; }
- if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) { - return EFI_INVALID_PARAMETER; + // Prepare data transfer's flags + if (((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) || + ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL))) { + DataTransfer = FALSE; }
- if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) { - return EFI_INVALID_PARAMETER; + if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) { + DataLen = Packet->InTransferLength; + Data = Packet->InDataBuffer; + Read = TRUE; + DataTransfer = TRUE; }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This); + if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) { + DataLen = Packet->OutTransferLength; + Data = Packet->OutDataBuffer; + DataTransfer = TRUE; + }
- if (!Private->Slot[Slot].Enable) { - return EFI_INVALID_PARAMETER; + // Clear ERROR_IRQ status + IntStatus = 0xFFFF; + Status = SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_ERR_INT_STS, + FALSE, + sizeof (IntStatus), + &IntStatus + ); + + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Cannot clear ERROR_IRQ status\n")); + return Status; }
- if (!Private->Slot[Slot].MediaPresent) { - return EFI_NO_MEDIA; + // Clear IRQ status + Status = SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + FALSE, + sizeof (IntStatus), + &IntStatus + ); + + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Cannot clear IRQ status\n")); + return Status; }
- if (!Private->Slot[Slot].Initialized) { - return EFI_DEVICE_ERROR; + WaitForInhibit (Private, Packet, Slot, DataTransfer); + + Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8); + if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) { + Cmd |= BIT5; }
- Trb = SdMmcCreateTrb (Private, Slot, Packet, Event); - if (Trb == NULL) { - return EFI_OUT_OF_RESOURCES; + if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) { + switch (Packet->SdMmcCmdBlk->ResponseType) { + case SdMmcResponseTypeR1: + case SdMmcResponseTypeR5: + case SdMmcResponseTypeR6: + case SdMmcResponseTypeR7: + Cmd |= (BIT1 | BIT3 | BIT4); + break; + case SdMmcResponseTypeR2: + Cmd |= (BIT0 | BIT3); + break; + case SdMmcResponseTypeR3: + case SdMmcResponseTypeR4: + Cmd |= BIT1; + break; + case SdMmcResponseTypeR1b: + case SdMmcResponseTypeR5b: + Cmd |= (BIT0 | BIT1 | BIT3 | BIT4); + break; + default: + ASSERT (FALSE); + break; + } } - // - // Immediately return for async I/O. - // - if (Event != NULL) { - return EFI_SUCCESS; + + if ((DataLen % BlockSize) != 0) { + if (DataLen < BlockSize) { + BlockSize = (UINT16)DataLen; + } } + BlkCount = (UINT16) (DataLen / BlockSize); + + if (DataTransfer) { + + // Set default timeout value + TimeoutCtrl = 0xE; + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_TIMEOUT_CTRL, + FALSE, + sizeof (TimeoutCtrl), + &TimeoutCtrl + ); + + Mode = 0x02; // SDHCI_TRNS_BLK_CNT_EN + if (BlkCount > 1) { + Mode |= 0x20; // SDHCI_TRNS_MULTI + } + if (Read) { + Mode |= 0x10; // SDHCI_TRNS_READ + }
- // - // Wait async I/O list is empty before execute sync I/O operation. - // - while (TRUE) { - OldTpl = gBS->RaiseTPL (TPL_NOTIFY); - if (IsListEmpty (&Private->Queue)) { - gBS->RestoreTPL (OldTpl); + // Fill BlockSize register + BlkSizeReg = (0x7 << 12) | (BlockSize & 0xFFF); + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_BLK_SIZE, + FALSE, + sizeof (BlkSizeReg), + &BlkSizeReg + ); + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_BLK_COUNT, + FALSE, + sizeof (BlkCount), + &BlkCount + ); + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_TRANS_MOD, + FALSE, + sizeof (Mode), + &Mode + ); + } + + Argument = Packet->SdMmcCmdBlk->CommandArgument; + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_ARG1, + FALSE, + sizeof (Argument), + &Argument + ); + + // Execute cmd + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_COMMAND, + FALSE, + sizeof (Cmd), + &Cmd + ); + + Mask = BIT0; // SDHCI_INT_RESPONSE + if (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b || + Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b) { + Mask |= BIT1; + } + + do { + Status = SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + TRUE, + sizeof (IntStatus), + &IntStatus + ); + + if (EFI_ERROR (Status)) { + return EFI_INVALID_PARAMETER; + } + + if (IntStatus & BIT15) { // SDHCI_INT_STATUS + DEBUG((DEBUG_INFO, "MvSdMmcPassThru: SDHCI_INT_ERROR stat:%x\n", + IntStatus)); break; } - gBS->RestoreTPL (OldTpl); - }
- Status = SdMmcWaitTrbEnv (Private, Trb); - if (EFI_ERROR (Status)) { - goto Done; + // Stall for 100 microseconds + gBS->Stall (100); + if (--Retry == 0) { + break; + } + } while ((IntStatus & Mask) != Mask); + + if (Retry == 0) { + DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Rx timeout\n")); + return EFI_TIMEOUT; }
- Status = SdMmcExecTrb (Private, Trb); - if (EFI_ERROR (Status)) { - goto Done; + if ((IntStatus & (BIT15 | Mask)) == Mask) { + if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) { + for (Index = 0; Index < 4; Index++) { + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_RESPONSE + Index * 4, + TRUE, + sizeof (UINT32), + &Response[Index] + ); + } + + CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response)); + + // + // Update RCA of current card in order to use it later + // for polling card status + // + if (SetRcaFlag) + CurrRca = Packet->SdMmcStatusBlk->Resp0 >> 16; + } + + IntStatus = Mask; + Status = SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + FALSE, + sizeof (IntStatus), + &IntStatus + ); + + } else { + Ret = -1; }
- Status = SdMmcWaitTrbResult (Private, Trb); - if (EFI_ERROR (Status)) { - goto Done; + if (!Ret && DataTransfer) { + Status = XenonTransferData (Private, Slot, Data, DataLen, BlockSize, BlkCount, Read); }
-Done: - if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) { - FreePages (Trb->AdmaDesc, Trb->AdmaPages); + // SDHCI_QUIRK_WAIT_SEND_CMD - 1 milisecond delay + gBS->Stall (1000); + + // Save current IRQ status + Status = SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + TRUE, + sizeof (IntStatus), + &IntStatus + ); + + // Clear IRQ + Stat = 0xFFFFFFFFULL; + Status = SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + FALSE, + sizeof (Stat), + &Stat + ); + + // + // There are two quirks for DataTransfer commands: + // 1. For multipleblock write/read it's necessary to issue + // SD_STOP_TRANSMISSION command + // 2. For every write data comand, it's necessary to poll for + // card status before issuing next data transfer + // + if (!Ret && DataTransfer) { + if (MultiFlag) { + SdMmcSendStopTransmission(This, Slot); + } + + if (!Read) { + return SdMmcIsReady (This, Slot, CurrRca, 1000); + } + + return EFI_SUCCESS; }
- if (Trb != NULL) { - FreePool (Trb); + // Check previously saved IRQ status for non-data commands + if (IntStatus & BIT15) { + if (Packet->SdMmcCmdBlk != NULL) { + XenonReset (Private, Slot, 0x02); // CMD + } + + if (DataTransfer) { + XenonReset (Private, Slot, 0x04); // DATA + } + + if (IntStatus & (0x10000 | 0x100000)) { // SDHCI_INT_TIMEOUT + DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Timeout!\n")); + return EFI_TIMEOUT; + } else { + return EFI_DEVICE_ERROR; + } + } else { + return EFI_SUCCESS; }
return Status; diff --git a/Drivers/SdMmc/MvSdMmcPciHcDxe.inf b/Drivers/SdMmc/MvSdMmcPciHcDxe.inf new file mode 100644 index 0000000..a4f66e9 --- /dev/null +++ b/Drivers/SdMmc/MvSdMmcPciHcDxe.inf @@ -0,0 +1,75 @@ +#/******************************************************************************* +#Copyright (C) 2016 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modification, +#are permitted provided that the following conditions are met: +# +#* Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +#* Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +#* Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#*******************************************************************************/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MvSdMmcPciHcDxe + MODULE_UNI_FILE = ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.uni + FILE_GUID = 5b5b83b8-52b8-4d02-b92b-c84a4dfb539d + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeSdMmcPciHcDxe + +[Sources] + ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c + ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c + ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c + ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h + ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c + ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h + MvSdMmcPciHcDxe.c + XenonSdhci.c + XenonSdhci.h + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Protocols] + gEfiDevicePathProtocolGuid ## TO_START + gEfiPciIoProtocolGuid ## TO_START + gEfiSdMmcPassThruProtocolGuid ## BY_START + +[UserExtensions.TianoCore."ExtraFiles"] + SdMmcPciHcDxeExtra.uni diff --git a/Drivers/SdMmc/XenonSdhci.c b/Drivers/SdMmc/XenonSdhci.c new file mode 100755 index 0000000..6a20105 --- /dev/null +++ b/Drivers/SdMmc/XenonSdhci.c @@ -0,0 +1,661 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "XenonSdhci.h" + +STATIC +VOID +XenonSetMpp ( + VOID + ) +{ + UINT32 Reg; + + // Set eMMC/SD PHY output instead of MPPs + Reg = MmioRead32 (MVEBU_IP_CONFIG_REG); + Reg &= ~(1 << 0); + MmioWrite32 (MVEBU_IP_CONFIG_REG, Reg); +} + +STATIC +VOID +XenonReadVersion ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + OUT UINT32 *ControllerVersion + ) +{ + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_CTRL_VER, TRUE, 2, ControllerVersion); +} + +STATIC +VOID +XenonSetFifo ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINTN Data = 0x315; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, 4, &Data); +} + +// Auto Clock Gating +STATIC +VOID +XenonSetAcg ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN BOOLEAN Enable + ) +{ + UINT32 Var; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, 4, &Var); + + if (Enable) { + Var &= ~AUTO_CLKGATE_DISABLE_MASK; + } else { + Var |= AUTO_CLKGATE_DISABLE_MASK; + } + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, 4, &Var); +} + +STATIC +VOID +XenonSetSlot ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN BOOLEAN Enable + ) +{ + UINT32 Var; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, 4, &Var); + if (Enable) { + Var |= ((0x1 << Slot) << SLOT_ENABLE_SHIFT); + } else { + Var &= ~((0x1 << Slot) << SLOT_ENABLE_SHIFT); + } + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, 4, &Var); +} + +STATIC +VOID +XenonSetSdio ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINTN Voltage + ) +{ + // Currently SDIO isn't supported + return; +} + +STATIC +VOID +XenonSetPower ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT32 Vcc, + IN UINT32 Vccq, + IN UINT8 Mode + ) +{ + UINT8 Pwr = 0; + UINT32 Ctrl = 0; + + // Set VCC + switch (Vcc) { + case MMC_VDD_165_195: + Pwr = SDHCI_POWER_180; + if (Mode == XENON_MMC_MODE_SD_SDIO) { + XenonSetSdio (PciIo, 0); + } + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + Pwr = SDHCI_POWER_300; + if (Mode == XENON_MMC_MODE_SD_SDIO) { + XenonSetSdio (PciIo, 1); + } + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + Pwr = SDHCI_POWER_330; + if (Mode == XENON_MMC_MODE_SD_SDIO) { + XenonSetSdio (PciIo, 1); + } + break; + default: + DEBUG((DEBUG_ERROR, "SD/MMC: Does not support power mode(0x%X)\n", Vcc)); + break; + } + + if (Pwr == 0) { + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_POWER_CTRL, FALSE, 1, &Pwr); + return; + } + + Pwr |= SDHCI_POWER_ON; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_POWER_CTRL, FALSE, 1, &Pwr); + + // Set VCCQ + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, TRUE, 4, &Ctrl); + Ctrl |= Vccq; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, FALSE, 4, &Ctrl); +} + +UINTN +XenonSetClk ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT32 Clock + ) +{ + UINT32 Div; + UINT32 Clk; + UINT32 Timeout; + UINT16 Value = 0; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Value); + + if (Clock == 0) + return 0; + + if (Private->ControllerVersion >= SDHCI_SPEC_300) { + // Version 3.00 Divisors must be a multiple of 2 + if (XENON_MMC_MAX_CLK <= Clock) { + Div = 1; + } else { + for (Div = 2; Div < SDHCI_MAX_DIV_SPEC_300; Div += 2) { + if ((XENON_MMC_MAX_CLK / Div) <= Clock) + break; + } + } + } else { + // Version 2.00 Divisors must be a power of 2 + for (Div = 1; Div < SDHCI_MAX_DIV_SPEC_200; Div *= 2) { + if ((XENON_MMC_MAX_CLK / Div) <= Clock) + break; + } + } + Div >>= 1; + + Clk = (Div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; + Clk |= ((Div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; + Clk |= SDHCI_CLOCK_INT_EN; + + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Clk); + + // Wait max 20 ms + Timeout = 200; + + do { + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &Clk); + if (Timeout == 0) { + DEBUG((DEBUG_ERROR, "SD/MMC: Internal Clock never stabilised\n")); + return -1; + } + + Timeout--; + gBS->Stall (1); + + } while (!(Clk & SDHCI_CLOCK_INT_STABLE)); + + Clk |= SDHCI_CLOCK_CARD_EN; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Clk); + + return 0; +} + +VOID +XenonPhyInit ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINT32 Var, Wait, Time; + UINT32 Clock = XENON_MMC_MAX_CLK; + UINT16 ClkCtrl; + + // Need to disable the clock to set EMMC_PHY_TIMING_ADJUST register + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl); + ClkCtrl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl); + + // Enable QSP PHASE SELECT + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var); + Var |= SAMPL_INV_QSP_PHASE_SELECT; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var); + + // Enable internal clock + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl); + ClkCtrl |= SDHCI_CLOCK_INT_EN; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl); + + // + // Poll for host MMC PHY clock init to be stable + // Wait up to 10ms + // + Time = 100; + while (Time--) { + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var); + if (Var & SDHCI_CLOCK_INT_STABLE) { + break; + } + + gBS->Stall (1); + } + if (Time <= 0) { + DEBUG((DEBUG_ERROR, "SD/MMC: Failed to enable MMC internal clock in Time\n")); + return; + } + + // Enable bus clock + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl); + ClkCtrl |= SDHCI_CLOCK_CARD_EN; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl); + + // Delay 200us to Wait for the completion of bus clock + gBS->Stall (200); + + // Init PHY + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var); + Var |= PHY_INITIALIZAION; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var); + + // Add duration of FC_SYNC_RST + Wait = ((Var >> FC_SYNC_RST_DURATION_SHIFT) & FC_SYNC_RST_DURATION_MASK); + + // Add interval between FC_SYNC_EN and FC_SYNC_RST + Wait += ((Var >> FC_SYNC_RST_EN_DURATION_SHIFT) & FC_SYNC_RST_EN_DURATION_MASK); + + // Add duration of asserting FC_SYNC_EN + Wait += ((Var >> FC_SYNC_EN_DURATION_SHIFT) & FC_SYNC_EN_DURATION_MASK); + + // Add duration of Waiting for PHY + Wait += ((Var >> WAIT_CYCLE_BEFORE_USING_SHIFT) & WAIT_CYCLE_BEFORE_USING_MASK); + + // 4 addtional bus clock and 4 AXI bus clock are required left shift 20 bits + Wait += 8; + Wait <<= 20; + + // Use the possibly slowest bus frequency value + if (Clock == 0) { + Clock = 100000; + } + + // Get the Wait Time in unit of ms + Wait = Wait / Clock; + Wait++; + + // Poll for host eMMC PHY init to complete, wait up to 10ms + Time = 100; + while (Time--) { + Var = SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var); + Var &= PHY_INITIALIZAION; + if (!Var) { + break; + } + + // Wait for host eMMC PHY init to complete + gBS->Stall (1); + } + + if (Time <= 0) { + DEBUG((DEBUG_ERROR, "SD/MMC: Failed to init MMC PHY in Time\n")); + return; + } + + return; +} + +STATIC +VOID +XenonSetPhy ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + UINT8 Timing + ) +{ + UINT32 Var = 0; + + // Setup pad, set bit[30], bit[28] and bits[26:24] + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, TRUE, 4, &Var); + Var |= (AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | FC_CMD_RECEN | FC_DQ_RECEN); + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, FALSE, 4, &Var); + + // + // If Timing belongs to high speed, set bit[17] of + // EMMC_PHY_TIMING_ADJUST register + // + if ((Timing == MMC_TIMING_MMC_HS400) || + (Timing == MMC_TIMING_MMC_HS200) || + (Timing == MMC_TIMING_UHS_SDR50) || + (Timing == MMC_TIMING_UHS_SDR104) || + (Timing == MMC_TIMING_UHS_DDR50) || + (Timing == MMC_TIMING_UHS_SDR25)) { + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var); + + // Set SLOW_MODE for PHY + Var |= OUTPUT_QSN_PHASE_SELECT | (1 << 29); + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var); + } + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, 4, &Var); + Var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE; + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, 4, &Var); + + if (Timing == MMC_TIMING_MMC_HS400) { + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, 4, &Var); + Var &= ~DQ_ASYNC_MODE; + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, 4, &Var); + + Var = LOGIC_TIMING_VALUE; + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_LOGIC_TIMING_ADJUST, FALSE, 4, &Var); + } + + XenonPhyInit (PciIo); +} + +STATIC +VOID +XenonConfigureInterrupts ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINT32 Var; + + // Clear interrupt status + Var = 0xFFFFFFFF; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, 4, &Var); + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, 4, &Var); + + // Enable only interrupts served by the SD controller + Var = 0xFFFFFEBF; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS_EN, FALSE, 4, &Var); + + // Mask all sdhci interrupt sources + Var = 0xFFFFFEFF; + SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_SIG_EN, FALSE, 4, &Var); +} + +// Enable Parallel Transfer Mode +STATIC +VOID +XenonSetParallelTransfer ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN BOOLEAN Enable + ) +{ + UINT32 Var; + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, TRUE, 4, &Var); + + if (Enable) { + Var |= (0x1 << Slot); + } else { + Var &= ~(0x1 << Slot); + } + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, FALSE, 4, &Var); +} + +STATIC +VOID +XenonSetTuning ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN BOOLEAN Enable + ) +{ + UINT32 Var; + + // Set the Re-Tuning Request functionality + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, TRUE, 4, &Var); + + if (Enable) { + Var |= RETUNING_COMPATIBLE; + } else { + Var &= ~RETUNING_COMPATIBLE; + } + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, FALSE, 4, &Var); + + // Set the Re-tuning Event Signal Enable + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, TRUE, 4, &Var); + + if (Enable) { + Var |= SDHCI_RETUNE_EVT_INTSIG; + } else { + Var &= ~SDHCI_RETUNE_EVT_INTSIG; + } + + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, FALSE, 4, &Var); +} + +VOID +XenonReset ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN UINT8 Mask + ) +{ + UINT32 Timeout = 1000; + UINT8 SwReset; + + SwReset = Mask; + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_SW_RST, + FALSE, + sizeof (SwReset), + &SwReset + ); + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_SW_RST, + TRUE, + sizeof (SwReset), + &SwReset + ); + + while (SwReset & Mask) { + if (Timeout == 0) { + DEBUG((DEBUG_ERROR, "SD/MMC: Reset never completed\n")); + return; + } + + Timeout--; + gBS-> Stall (100); + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_SW_RST, + TRUE, + sizeof (SwReset), + &SwReset + ); + } +} + +STATIC +VOID +XenonTransferPio ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN OUT VOID *Buffer, + IN UINT16 BlockSize, + IN BOOLEAN Read + ) +{ + UINTN I; + UINT8 *Offs; + + // + // SD stack's intrinsic functions cannot perform properly reading/writing from + // buffer register, that is why MmioRead/MmioWrite are used. It is temporary + // solution. + // + for (I = 0; I < BlockSize; I += 4) { + Offs = Buffer + I; + if (Read) { + *(UINT32 *)Offs = MmioRead32 (0xf06e0020); // SDHCI_BUFFER + } else { + MmioWrite32 (0xf06e0020, *(UINT32 *)Offs); // SDHCI_BUFFER + } + } +} + +EFI_STATUS +XenonTransferData ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN OUT VOID *Buffer, + IN UINT32 DataLen, + IN UINT16 BlockSize, + IN UINT16 Blocks, + IN BOOLEAN Read + ) +{ + UINT32 IntStatus, PresentState, Rdy, Mask, Timeout, Block = 0; + + if (Buffer == NULL) { + return EFI_DEVICE_ERROR; + } + + Timeout = 100000; // 100000 * 10 us = 1 second + Rdy = 0x10 | 0x20; // SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL + Mask = 0x800 | 0x400; // SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE + + do { + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + TRUE, + sizeof (IntStatus), + &IntStatus + ); + + if (IntStatus & BIT15) { // SDHCI_INT_ERROR + DEBUG((DEBUG_INFO, "SD/MMC: Error detected in status %0x\n", IntStatus)); + return EFI_DEVICE_ERROR; + } + + if (IntStatus & Rdy) { + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_PRESENT_STATE, + TRUE, + sizeof (PresentState), + &PresentState + ); + + if (!(PresentState & Mask)) { + continue; + } + + SdMmcHcRwMmio ( + Private->PciIo, + Slot, + SD_MMC_HC_NOR_INT_STS, + FALSE, + sizeof (Rdy), + &Rdy + ); + + XenonTransferPio (Private, Slot, Buffer, BlockSize, Read); + + Buffer += BlockSize; + if (++Block >= Blocks) { + break; + } + } + + if (Timeout-- > 0) { + gBS->Stall (10); + } else { + DEBUG((DEBUG_INFO, "SD/MMC: Transfer data timeout\n")); + return EFI_TIMEOUT; + } + } while (!(IntStatus & BIT1)); // SDHCI_INT_DATA_END + return EFI_SUCCESS; +} + +EFI_STATUS +XenonInit ( + IN SD_MMC_HC_PRIVATE_DATA *Private + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo = Private->PciIo; + + XenonSetMpp (); + + XenonReadVersion (PciIo, &Private->ControllerVersion); + + XenonSetFifo (PciIo); + + XenonSetAcg (PciIo, FALSE); + + // Hyperion has only one port + XenonSetSlot (PciIo, XENON_MMC_SLOT_ID_HYPERION, TRUE); + + XenonSetPower (PciIo, MMC_VDD_165_195, eMMC_VCCQ_1_8V, XENON_MMC_MODE_SD_SDIO); + + // Set MAX_CLOCK for configuring PHY + XenonSetClk (PciIo, Private, XENON_MMC_MAX_CLK); + + XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50); + + XenonConfigureInterrupts (PciIo); + + // Enable parallel transfer + XenonSetParallelTransfer (PciIo, XENON_MMC_SLOT_ID_HYPERION, TRUE); + + XenonSetTuning (PciIo, XENON_MMC_SLOT_ID_HYPERION, FALSE); + + XenonSetAcg (PciIo, TRUE); + + XenonSetClk (PciIo, Private, XENON_MMC_BASE_CLK); + + XenonPhyInit (PciIo); + + return EFI_SUCCESS; +} diff --git a/Drivers/SdMmc/XenonSdhci.h b/Drivers/SdMmc/XenonSdhci.h new file mode 100644 index 0000000..a7b30c3 --- /dev/null +++ b/Drivers/SdMmc/XenonSdhci.h @@ -0,0 +1,278 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h" + +#include <Library/IoLib.h> + +#define SD_BAR_INDEX 0 + +/* Register Offset of SD Host Controller SOCP self-defined register */ + +#define SDHC_IPID 0x0100 +#define SDHC_SYS_CFG_INFO 0x0104 +#define SLOT_TYPE_SDIO_SHIFT 24 +#define SLOT_TYPE_EMMC_MASK 0xff +#define SLOT_TYPE_EMMC_SHIFT 16 +#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xff +#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8 + +#define SDHC_SYS_OP_CTRL 0x0108 +#define AUTO_CLKGATE_DISABLE_MASK (0x1<<20) +#define SDCLK_IDLEOFF_ENABLE_SHIFT 8 +#define SLOT_ENABLE_SHIFT 0 + +#define SDHC_SYS_EXT_OP_CTRL 0x010c +#define SDHC_TEST_OUT 0x0110 +#define SDHC_TESTOUT_MUXSEL 0x0114 + +#define SDHC_SLOT_EXT_INT_STATUS 0x0120 +#define SDHC_SLOT_EXT_ERR_STATUS 0x0122 +#define SDHC_SLOT_EXT_INT_STATUS_EN 0x0124 +#define SDHC_SLOT_EXT_ERR_STATUS_EN 0x0126 + +#define SDHC_SLOT_OP_STATUS_CTRL 0x0128 +#define TUNING_PROG_FIXED_DELAY_MASK 0x7ff +#define FORCE_SEL_INVERSE_CLK_SHIFT 11 + +#define SDHC_SLOT_FIFO_CTRL 0x012c + +#define SDHC_SLOT_eMMC_CTRL 0x0130 +#define ENABLE_DATA_STROBE_SHIFT 24 +#define SET_EMMC_RSTN_SHIFT 16 +#define eMMC_VCCQ_MASK 0x3 +#define eMMC_VCCQ_1_8V 0x1 +#define eMMC_VCCQ_1_2V 0x2 +#define eMMC_VCCQ_3_3V 0x3 + +#define SDHC_SLOT_OUTPUT_DLY_CTRL 0x0134 +#define SDHC_SLOT_DCM_CTRL 0x0137 + +#define SDHC_SLOT_DLL_CTRL 0x0138 +#define SELECT_DEF_DLL 0x1 + +#define SDHC_SLOT_DLL_PHASE_SEL 0x013c +#define DLL_UPDATE_STROBE 7 + +#define SDHC_SLOT_STROBE_DLY_CTRL 0x0140 +#define STROBE_DELAY_FIXED_MASK 0xffff + +#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144 +#define RETUNING_COMPATIBLE 0x1 + +#define SDHC_SLOT_AUTO_RETUNING_CTRL 0x0148 +#define ENABLE_AUTO_RETUNING 0x1 + +#define SDHC_SLOT_EXT_PRESENT_STATE 0x014c +#define SDHC_SLOT_DLL_CUR_DLY_VAL 0x0150 +#define SDHC_SLOT_TUNING_CUR_DLY_VAL 0x0154 +#define SDHC_SLOT_STROBE_CUR_DLY_VAL 0x0158 +#define SDHC_SLOT_SUB_CMD_STRL 0x015c + +#define SDHC_SLOT_CQ_TASK_INFO 0x0160 + +#define SDHC_SLOT_TUNING_DEBUG_INFO 0x01f0 +#define SDHC_SLOT_DATAIN_DEBUG_INFO 0x01f4 + +#define XENON_MMC_MAX_CLK 400000000 +#define XENON_MMC_CLK_RATIO 2046 +#define XENON_MMC_BASE_CLK XENON_MMC_MAX_CLK / XENON_MMC_CLK_RATIO + +#define XENON_MMC_CMD_MAX_TIMEOUT 3200 +#define XENON_MMC_CMD_DEFAULT_TIMEOUT 100 + +/* Tuning Parameter */ +#define TMR_RETUN_NO_PRESENT 0xf +#define XENON_MAX_TUN_COUNT 0xb + +#define EMMC_PHY_REG_BASE 0x170 +#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE +#define OUTPUT_QSN_PHASE_SELECT (1 << 17) +#define SAMPL_INV_QSP_PHASE_SELECT (1 << 18) +#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 +#define PHY_INITIALIZAION (1 << 31) +#define WAIT_CYCLE_BEFORE_USING_MASK 0xf +#define WAIT_CYCLE_BEFORE_USING_SHIFT 12 +#define FC_SYNC_EN_DURATION_MASK 0xf +#define FC_SYNC_EN_DURATION_SHIFT 8 +#define FC_SYNC_RST_EN_DURATION_MASK 0xf +#define FC_SYNC_RST_EN_DURATION_SHIFT 4 +#define FC_SYNC_RST_DURATION_MASK 0xf +#define FC_SYNC_RST_DURATION_SHIFT 0 + +#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4) +#define DQ_ASYNC_MODE (1 << 4) +#define DQ_DDR_MODE_SHIFT 8 +#define DQ_DDR_MODE_MASK 0xff +#define CMD_DDR_MODE (1 << 16) + +#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8) +#define REC_EN_SHIFT 24 +#define REC_EN_MASK 0xf +#define FC_DQ_RECEN (1 << 24) +#define FC_CMD_RECEN (1 << 25) +#define FC_QSP_RECEN (1 << 26) +#define FC_QSN_RECEN (1 << 27) +#define OEN_QSN (1 << 28) +#define AUTO_RECEN_CTRL (1 << 30) + +#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc) +#define EMMC_PHY_PAD_CONTROL2 (EMMC_PHY_REG_BASE + 0x10) +#define EMMC_PHY_DLL_CONTROL (EMMC_PHY_REG_BASE + 0x14) +#define DLL_DELAY_TEST_LOWER_SHIFT 8 +#define DLL_DELAY_TEST_LOWER_MASK 0xff +#define DLL_BYPASS_EN 0x1 + +#define EMMC_LOGIC_TIMING_ADJUST (EMMC_PHY_REG_BASE + 0x18) +#define EMMC_LOGIC_TIMING_ADJUST_LOW (EMMC_PHY_REG_BASE + 0x1c) + +#define MVEBU_IP_CONFIG_REG (0xf0000000 + 0x6F4100) + +#define LOGIC_TIMING_VALUE 0x5a54 /* Recommend by HW team */ + +/* Hyperion only have one slot 0 */ +#define XENON_MMC_SLOT_ID_HYPERION (0) + +#define MMC_TIMING_LEGACY 0 +#define MMC_TIMING_MMC_HS 1 +#define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 3 +#define MMC_TIMING_UHS_SDR25 4 +#define MMC_TIMING_UHS_SDR50 5 +#define MMC_TIMING_UHS_SDR104 6 +#define MMC_TIMING_UHS_DDR50 7 +#define MMC_TIMING_MMC_HS200 8 +#define MMC_TIMING_MMC_HS400 10 + +/* Data time out default value 0xE: TMCLK x 227 */ +#define DATA_TIMEOUT_DEF_VAL 0xe + +/* SDMA start address should allign with 0x8, align mask 0x7 */ +#define DMA_START_ADDR_ALIGN_MASK 0x7 + +#define SDHCI_RETUNE_EVT_INTSIG 0x00001000 + +/* MMC modes */ +#define XENON_MMC_MODE_EMMC 0 +#define XENON_MMC_MODE_SD_SDIO 1 + +/* MMC Voltage */ +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +/* SDHCI FLAGS */ +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_SHIFT 6 +#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK_LEN 8 +#define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_INT_STABLE 0x0002 +#define SDHCI_CLOCK_INT_EN 0x0001 + +#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2 + +#define SDHCI_SIGNAL_ENABLE 0x38 + +#define SDHCI_MAX_DIV_SPEC_200 256 +#define SDHCI_MAX_DIV_SPEC_300 2046 + +UINTN +XenonSetClk ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT32 Clock + ); + +VOID +XenonPhyInit ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ); + +VOID +XenonReset ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN UINT8 Mask + ); + +EFI_STATUS +XenonTransferData ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN OUT VOID *Buffer, + IN UINT32 DataLen, + IN UINT16 BlockSize, + IN UINT16 Blocks, + IN BOOLEAN Read + ); + +EFI_STATUS +XenonInit ( + IN SD_MMC_HC_PRIVATE_DATA *Private + ); + +EFI_STATUS +SdCardSendStatus ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 Slot, + IN UINT16 Rca, + OUT UINT32 *DevStatus + );
On Thu, Nov 17, 2016 at 12:05:24PM +0100, Marcin Wojtas wrote:
From: Jan Dąbroś jsd@semihalf.com
Because Xenon SD/MMC controller isn't fully compatible with SDHC, it demands some quirks on generic driver during initialization and command processing. Below are listed necessary changes:
- Add Xenon-specific init sequence - registers related to PHY
- Add Xenon-specific command processing sequence:
- Because DMA isn't yet supported, we use PIO mode for DATA transfers. It brings necessity of sending SD_STOP_TRANSMISSION for multiple-block transfers and polling for card status after write data transfers, which aren't implemented in edk2's SdMmc stack
- Command processing sequence for Xenon controller have also other quirks regarding flow of operation (please see comments in code) and TRB-oriented method isn't applicable in this case.
Beside above, MvSdMmcPciHcDxe driver is compatible with SdMmcPciHcDxe.
Two files containing Xenon-specific functions and defines were added.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com
Drivers/SdMmc/MvSdMmcPciHcDxe.c | 636 +++++++++++++++++++++++++++++++----- Drivers/SdMmc/MvSdMmcPciHcDxe.inf | 75 +++++ Drivers/SdMmc/XenonSdhci.c | 661 ++++++++++++++++++++++++++++++++++++++ Drivers/SdMmc/XenonSdhci.h | 278 ++++++++++++++++ 4 files changed, 1564 insertions(+), 86 deletions(-) mode change 100644 => 100755 Drivers/SdMmc/MvSdMmcPciHcDxe.c create mode 100644 Drivers/SdMmc/MvSdMmcPciHcDxe.inf create mode 100755 Drivers/SdMmc/XenonSdhci.c create mode 100644 Drivers/SdMmc/XenonSdhci.h
diff --git a/Drivers/SdMmc/MvSdMmcPciHcDxe.c b/Drivers/SdMmc/MvSdMmcPciHcDxe.c old mode 100644 new mode 100755 index 5adbbcd..ef771bb --- a/Drivers/SdMmc/MvSdMmcPciHcDxe.c +++ b/Drivers/SdMmc/MvSdMmcPciHcDxe.c @@ -5,6 +5,8 @@ It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2016, Marvell. All rights reserved.<BR>
- This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at
@@ -15,7 +17,7 @@ **/ -#include "SdMmcPciHcDxe.h" +#include "XenonSdhci.h" // // Driver Global Variables @@ -520,13 +522,10 @@ SdMmcPciHcDriverBindingStart ( EFI_PCI_IO_PROTOCOL *PciIo; UINT64 Supports; UINT64 PciAttributes;
- UINT8 SlotNum;
- UINT8 FirstBar; UINT8 Slot; UINT8 Index; CARD_TYPE_DETECT_ROUTINE *Routine; UINT32 RoutineNum;
- BOOLEAN MediaPresent; BOOLEAN Support64BitDma;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); @@ -593,26 +592,32 @@ SdMmcPciHcDriverBindingStart ( Private->PciAttributes = PciAttributes; InitializeListHead (&Private->Queue);
- //
- // Get SD/MMC Pci Host Controller Slot info
- //
- Status = SdMmcHcGetSlotInfo (PciIo, &FirstBar, &SlotNum);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Support64BitDma = TRUE;
- for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) {
- for (Slot = 0; Slot < (XENON_MMC_SLOT_ID_HYPERION + 1); Slot++) {
Since all this line is currently doing is hardcoding that this loop should only be executed once, could an intermediate define of ..._NUM_SLOTS be introduced, if we're expecting this driver to be reusable for anything else? (And if we don't, can we drop the loop bit?)
Private->Slot[Slot].Enable = TRUE;Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]); if (EFI_ERROR (Status)) { continue; }
- DumpCapabilityReg (Slot, &Private->Capability[Slot]);
Support64BitDma &= Private->Capability[Slot].SysBus64;
- //
- // Override capabilities structure - only 4 Bit width bus is supported
- // by HW and also force using SDR25 mode
- //
- Private->Capability[Slot].Sdr104 = 0;
- Private->Capability[Slot].Ddr50 = 0;
- Private->Capability[Slot].Sdr50 = 0;
- Private->Capability[Slot].BusWidth8 = 0;
And if you are importing the whole driver, I'm guessing you can get rid of this type of thing completely?
- if (Private->Capability[Slot].BaseClkFreq == 0) {
Private->Capability[Slot].BaseClkFreq = 0xff;- }
- DumpCapabilityReg (Slot, &Private->Capability[Slot]);
- Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); if (EFI_ERROR (Status)) { continue;
@@ -624,28 +629,8 @@ SdMmcPciHcDriverBindingStart ( continue; }
- //
- // Reset the specified slot of the SD/MMC Pci Host Controller
- //
- Status = SdMmcHcReset (PciIo, Slot);
- if (EFI_ERROR (Status)) {
continue;- }
- //
- // Check whether there is a SD/MMC card attached
- //
- Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent);
- if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) {
continue;- } else if (!MediaPresent) {
DEBUG ((DEBUG_ERROR, "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n", Slot));continue;- }
- Status = SdMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]);
- if (EFI_ERROR (Status)) {
continue;- }
- // Perform Xenon-specific init sequence
- XenonInit (Private);
Private->Slot[Slot].MediaPresent = TRUE; Private->Slot[Slot].Initialized = TRUE; @@ -889,6 +874,220 @@ SdMmcPciHcDriverBindingStop ( } /**
- Check if card is ready for next data transfer by reading its status.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot The slot number of the device to send the command to.
- @param[in] Rca The relative device address of addressed device.
- @param[in] Timeout The timeout in miliseconds.
- @retval EFI_SUCCESS Card is ready for next data transfer.
- @retval EFI_DEVICE_ERROR Card status is erroneous.
- @retval EFI_TIMEOUT Card is busy.
+**/ +STATIC +EFI_STATUS +SdMmcIsReady (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN UINTN Timeout
- )
+{
- EFI_STATUS Status;
- UINT32 DevStatus;
- do {
- Status = SdCardSendStatus (This, Slot, Rca, &DevStatus);
- if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Cannot read SD status\n"));return Status;- }
- // Check device status
- if ((DevStatus & (1 << 8)) && (DevStatus & (0xf << 9)) != (7 << 9)) {
Some macros here to show which flags are being checked, please?
break;- } else if (DevStatus & ~0x0206BF7F) {
More macros, please.
DEBUG ((DEBUG_ERROR, "SD Status error\n"));return EFI_DEVICE_ERROR;- }
- gBS->Stall (1000);
And a comment with that delay please. (Why? Why this value?)
- } while (Timeout--);
- if (Timeout <= 0) {
- DEBUG ((DEBUG_ERROR, "SD Status timeout\n"));
- return EFI_TIMEOUT;
- }
- if (DevStatus & (1 << 7)) {
Macro?
- DEBUG ((DEBUG_ERROR, "SD switch error\n"));
- return EFI_DEVICE_ERROR;
- }
- return EFI_SUCCESS;
+}
+STATIC +EFI_STATUS +CheckParameters (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN UINT8 Slot
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if ((This == NULL) || (Packet == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- }
- if (!Private->Slot[Slot].Enable) {
- return EFI_INVALID_PARAMETER;
- }
- if (!Private->Slot[Slot].MediaPresent) {
- return EFI_NO_MEDIA;
- }
- // Currently we don't support SDIO
- if (Packet->SdMmcCmdBlk->CommandIndex == SDIO_SEND_OP_COND) {
- return EFI_DEVICE_ERROR;
- }
- return EFI_SUCCESS;
+}
+/**
- Send command SD_STOP_TRANSMISSION to stop multiple block transfer.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot The slot number of the device to send the command to.
- @retval EFI_SUCCESS The request is executed successfully.
- @retval Others The request could not be executed successfully.
+**/ +STATIC +EFI_STATUS +SdMmcSendStopTransmission (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot
- )
+{
- EFI_STATUS Status;
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
- ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
- ZeroMem (&Packet, sizeof (Packet));
- Packet.SdMmcCmdBlk = &SdMmcCmdBlk;
- Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
- Packet.Timeout = 2500 * 1000; // SD generic timeout
Sure, but can we have some defines for it please?
- SdMmcCmdBlk.CommandIndex = SD_STOP_TRANSMISSION;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
- SdMmcCmdBlk.CommandArgument = 0;
- Status = This->PassThru (This, Slot, &Packet, NULL);
- return Status;
+}
+STATIC +EFI_STATUS +WaitForInhibit (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN UINT8 Slot,
- IN BOOLEAN DataTransfer
- )
+{
- UINT32 Mask, PresentState, Time = 0;
- UINT32 CmdTimeout = XENON_MMC_CMD_DEFAULT_TIMEOUT;
- if (Packet->SdMmcCmdBlk != NULL) {
- Mask = BIT0; // SDHCI_CMD_INHIBIT
- }
- if (DataTransfer != FALSE) {
- Mask = BIT1; // SDHCI_DATA_INHIBIT
- }
- //
- // We shouldn't wait for data inhibit for stop commands, even
- // though they might use busy signaling
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_STOP_TRANSMISSION)
- Mask &= ~BIT1;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);- while (PresentState & Mask) {
- if (Time >= CmdTimeout) {
if (2 * CmdTimeout <= XENON_MMC_CMD_MAX_TIMEOUT) {CmdTimeout += CmdTimeout;} else {if (Packet->SdMmcCmdBlk != NULL) {XenonReset (Private, Slot, 0x02); // CMD reset
Could replace the comment with a #define?
}if (DataTransfer) {XenonReset (Private, Slot, 0x04); // DATA reset
Could replace the comment with a #define?
}DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Timeout...\n"));return EFI_TIMEOUT;}- }
- Time++;
- gBS->Stall (1000);
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);- }
- return EFI_SUCCESS;
+}
+// Variable to store current card's Rca - used in polling card status +STATIC UINT16 CurrRca = 0;
I think this should have an m-prefix.
+/** Sends SD command to an SD card that is attached to the SD controller. The PassThru() function sends the SD command specified by Packet to the SD card @@ -934,86 +1133,351 @@ SdMmcPassThruPassThru ( IN EFI_EVENT Event OPTIONAL ) {
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_MMC_HC_TRB *Trb;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- INTN Ret;
- UINTN *Data, DataLen, Index;
- UINT32 Argument, Response[4], Retry, Stat, Mask;
Please not Stat and Status in the same function.
- UINT16 BlockSize, BlkCount;
- UINT16 Cmd, IntStatus, TimeoutCtrl, Mode, BlkSizeReg;
- BOOLEAN MultiFlag = FALSE, SetRcaFlag = FALSE, Read = FALSE;
- BOOLEAN DataTransfer;
- Data = NULL;
- DataLen = 0;
- Retry = 1000;
Could we have a define for that?
- Stat = 0;
- Ret = 0;
- BlockSize = 0x200;
SIZE_512B? (We don't have a global define for that, but it would make it more readable.)
- BlkCount = 0;
- Status = CheckParameters (This, Packet, Slot);
- if (EFI_ERROR(Status)) {
- return Status;
- }
- if ((This == NULL) || (Packet == NULL)) {
- return EFI_INVALID_PARAMETER;
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- //
- // Mark if this is multiblock data transfer since some special
- // acctions must be taken in such circumstances, i.e. it's necessary
- // to send SD_STOP_TRANSMISSION command.
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_WRITE_MULTIPLE_BLOCK ||
Packet->SdMmcCmdBlk->CommandIndex == SD_READ_MULTIPLE_BLOCK) {- MultiFlag = TRUE; }
- if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
- return EFI_INVALID_PARAMETER;
- //
- // Mark if this is command to set new relative card address (RCA),
- // since it's necessary to have updated copy of current RCA in this
- // layer - used in checking card status.
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_SET_RELATIVE_ADDR) {
- SetRcaFlag = TRUE; }
- if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- // Prepare data transfer's flags
- if (((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) ||
((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL))) {- DataTransfer = FALSE; }
- if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
- DataLen = Packet->InTransferLength;
- Data = Packet->InDataBuffer;
- Read = TRUE;
- DataTransfer = TRUE; }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
- DataLen = Packet->OutTransferLength;
- Data = Packet->OutDataBuffer;
- DataTransfer = TRUE;
- }
- if (!Private->Slot[Slot].Enable) {
- return EFI_INVALID_PARAMETER;
- // Clear ERROR_IRQ status
- IntStatus = 0xFFFF;
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_ERR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Cannot clear ERROR_IRQ status\n"));
- return Status; }
- if (!Private->Slot[Slot].MediaPresent) {
- return EFI_NO_MEDIA;
- // Clear IRQ status
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Cannot clear IRQ status\n"));
- return Status; }
- if (!Private->Slot[Slot].Initialized) {
- return EFI_DEVICE_ERROR;
- WaitForInhibit (Private, Packet, Slot, DataTransfer);
- Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
- if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
- Cmd |= BIT5;
Is it possible to give this bit a more descriprive name?
}
- Trb = SdMmcCreateTrb (Private, Slot, Packet, Event);
- if (Trb == NULL) {
- return EFI_OUT_OF_RESOURCES;
- if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
- switch (Packet->SdMmcCmdBlk->ResponseType) {
case SdMmcResponseTypeR1:case SdMmcResponseTypeR5:case SdMmcResponseTypeR6:case SdMmcResponseTypeR7:Cmd |= (BIT1 | BIT3 | BIT4);
Is it possible to give these bits more descriprive names? If not, please sort them in descending order. (Same applies to rest of cases.)
break;case SdMmcResponseTypeR2:Cmd |= (BIT0 | BIT3);break;case SdMmcResponseTypeR3:case SdMmcResponseTypeR4:Cmd |= BIT1;break;case SdMmcResponseTypeR1b:case SdMmcResponseTypeR5b:Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);break;default:ASSERT (FALSE);
Should this not return also? In a release build, this would just keep executing in an unknown state.
break;- } }
- //
- // Immediately return for async I/O.
- //
- if (Event != NULL) {
- return EFI_SUCCESS;
- if ((DataLen % BlockSize) != 0) {
- if (DataLen < BlockSize) {
BlockSize = (UINT16)DataLen;- } }
- BlkCount = (UINT16) (DataLen / BlockSize);
- if (DataTransfer) {
- // Set default timeout value
- TimeoutCtrl = 0xE;
#define?
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_TIMEOUT_CTRL,FALSE,sizeof (TimeoutCtrl),&TimeoutCtrl);- Mode = 0x02; // SDHCI_TRNS_BLK_CNT_EN
- if (BlkCount > 1) {
Mode |= 0x20; // SDHCI_TRNS_MULTI- }
- if (Read) {
Mode |= 0x10; // SDHCI_TRNS_READ
#defines instead of comments?
- }
- //
- // Wait async I/O list is empty before execute sync I/O operation.
- //
- while (TRUE) {
- OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
- if (IsListEmpty (&Private->Queue)) {
gBS->RestoreTPL (OldTpl);
- // Fill BlockSize register
- BlkSizeReg = (0x7 << 12) | (BlockSize & 0xFFF);
#defines?
(SIZE_4KB - 1)?
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_BLK_SIZE,FALSE,sizeof (BlkSizeReg),&BlkSizeReg);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_BLK_COUNT,FALSE,sizeof (BlkCount),&BlkCount);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_TRANS_MOD,FALSE,sizeof (Mode),&Mode);- }
- Argument = Packet->SdMmcCmdBlk->CommandArgument;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_ARG1,FALSE,sizeof (Argument),&Argument);- // Execute cmd
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_COMMAND,FALSE,sizeof (Cmd),&Cmd);- Mask = BIT0; // SDHCI_INT_RESPONSE
#define instead of comment?
- if (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b ||
Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b) {- Mask |= BIT1;
#define instead of comment?
- }
- do {
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER;- }
- if (IntStatus & BIT15) { // SDHCI_INT_STATUS
#define instead of comment?
DEBUG((DEBUG_INFO, "MvSdMmcPassThru: SDHCI_INT_ERROR stat:%x\n",IntStatus)); break;
- gBS->RestoreTPL (OldTpl);
- }
- Status = SdMmcWaitTrbEnv (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- // Stall for 100 microseconds
Yeah, that's what the line below says on its own. Why? Why this period?
- gBS->Stall (100);
- if (--Retry == 0) {
break;- }
- } while ((IntStatus & Mask) != Mask);
- if (Retry == 0) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Rx timeout\n"));
- return EFI_TIMEOUT; }
- Status = SdMmcExecTrb (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- if ((IntStatus & (BIT15 | Mask)) == Mask) {
#define?
- if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
for (Index = 0; Index < 4; Index++) {SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_RESPONSE + Index * 4,TRUE,sizeof (UINT32),
sizeof (Response[Index])? (Or sizeof (*Response)?)
&Response[Index]);}CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));//// Update RCA of current card in order to use it later// for polling card status//if (SetRcaFlag)
Always {} with if.
CurrRca = Packet->SdMmcStatusBlk->Resp0 >> 16;
#define?
- }
- IntStatus = Mask;
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- } else {
- Ret = -1; }
- Status = SdMmcWaitTrbResult (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- if (!Ret && DataTransfer) {
- Status = XenonTransferData (Private, Slot, Data, DataLen, BlockSize, BlkCount, Read); }
-Done:
- if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
- FreePages (Trb->AdmaDesc, Trb->AdmaPages);
- // SDHCI_QUIRK_WAIT_SEND_CMD - 1 milisecond delay
The code already says it's a 1 milisecond delay. Why is there a delay, and why is it of this period?
- gBS->Stall (1000);
- // Save current IRQ status
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- // Clear IRQ
- Stat = 0xFFFFFFFFULL;
Stat (hopefully to be renamed) is UINT32, so why ULL? But would also look much better with a #define.
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (Stat),&Stat);- //
- // There are two quirks for DataTransfer commands:
- // 1. For multipleblock write/read it's necessary to issue
- // SD_STOP_TRANSMISSION command
- // 2. For every write data comand, it's necessary to poll for
- // card status before issuing next data transfer
- //
- if (!Ret && DataTransfer) {
- if (MultiFlag) {
SdMmcSendStopTransmission(This, Slot);- }
- if (!Read) {
return SdMmcIsReady (This, Slot, CurrRca, 1000);
What is 1000?
- }
- return EFI_SUCCESS; }
- if (Trb != NULL) {
- FreePool (Trb);
- // Check previously saved IRQ status for non-data commands
- if (IntStatus & BIT15) {
- if (Packet->SdMmcCmdBlk != NULL) {
XenonReset (Private, Slot, 0x02); // CMD
#define instead of comment.
- }
- if (DataTransfer) {
XenonReset (Private, Slot, 0x04); // DATA
#define instead of comment.
- }
- if (IntStatus & (0x10000 | 0x100000)) { // SDHCI_INT_TIMEOUT
#defines.
DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Timeout!\n"));return EFI_TIMEOUT;- } else {
return EFI_DEVICE_ERROR;- }
- } else {
- return EFI_SUCCESS; }
return Status; diff --git a/Drivers/SdMmc/MvSdMmcPciHcDxe.inf b/Drivers/SdMmc/MvSdMmcPciHcDxe.inf new file mode 100644 index 0000000..a4f66e9 --- /dev/null +++ b/Drivers/SdMmc/MvSdMmcPciHcDxe.inf @@ -0,0 +1,75 @@ +#/******************************************************************************* +#Copyright (C) 2016 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modification, +#are permitted provided that the following conditions are met: +# +#* Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +#* Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +#* Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#*******************************************************************************/
+[Defines]
- INF_VERSION = 0x00010005
0019
- BASE_NAME = MvSdMmcPciHcDxe
- MODULE_UNI_FILE = ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.uni
Refer to local copies.
- FILE_GUID = 5b5b83b8-52b8-4d02-b92b-c84a4dfb539d
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeSdMmcPciHcDxe
+[Sources]
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
Refer to local copies.
- MvSdMmcPciHcDxe.c
- XenonSdhci.c
- XenonSdhci.h
+[Packages]
- MdePkg/MdePkg.dec
+[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- DevicePathLib
- MemoryAllocationLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- UefiLib
- UefiRuntimeServicesTableLib
+[Protocols]
- gEfiDevicePathProtocolGuid ## TO_START
- gEfiPciIoProtocolGuid ## TO_START
- gEfiSdMmcPassThruProtocolGuid ## BY_START
+[UserExtensions.TianoCore."ExtraFiles"]
- SdMmcPciHcDxeExtra.uni
diff --git a/Drivers/SdMmc/XenonSdhci.c b/Drivers/SdMmc/XenonSdhci.c new file mode 100755 index 0000000..6a20105 --- /dev/null +++ b/Drivers/SdMmc/XenonSdhci.c @@ -0,0 +1,661 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd.
+Marvell BSD License Option
+If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met:
+* Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
+* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#include "XenonSdhci.h"
+STATIC +VOID +XenonSetMpp (
- VOID
- )
+{
- UINT32 Reg;
- // Set eMMC/SD PHY output instead of MPPs
As pin control configuration, isn't this something that should be done in Armada70x0Lib or similar?
- Reg = MmioRead32 (MVEBU_IP_CONFIG_REG);
- Reg &= ~(1 << 0);
#define
- MmioWrite32 (MVEBU_IP_CONFIG_REG, Reg);
+}
+STATIC +VOID +XenonReadVersion (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- OUT UINT32 *ControllerVersion
- )
+{
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_CTRL_VER, TRUE, 2, ControllerVersion);
What is 2?
+}
+STATIC +VOID +XenonSetFifo (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINTN Data = 0x315;
#define
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, 4, &Data);
What is 4?
+}
+// Auto Clock Gating +STATIC +VOID +XenonSetAcg (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, 4, &Var);
What is 4?
- if (Enable) {
- Var &= ~AUTO_CLKGATE_DISABLE_MASK;
- } else {
- Var |= AUTO_CLKGATE_DISABLE_MASK;
- }
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, 4, &Var);
What is 4?
+}
+STATIC +VOID +XenonSetSlot (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, 4, &Var);
What is 4?
- if (Enable) {
- Var |= ((0x1 << Slot) << SLOT_ENABLE_SHIFT);
- } else {
- Var &= ~((0x1 << Slot) << SLOT_ENABLE_SHIFT);
- }
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, 4, &Var);
What is 4?
+}
+STATIC +VOID +XenonSetSdio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINTN Voltage
- )
+{
- // Currently SDIO isn't supported
- return;
+}
+STATIC +VOID +XenonSetPower (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Vcc,
- IN UINT32 Vccq,
- IN UINT8 Mode
- )
+{
- UINT8 Pwr = 0;
- UINT32 Ctrl = 0;
- // Set VCC
- switch (Vcc) {
- case MMC_VDD_165_195:
- Pwr = SDHCI_POWER_180;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 0);
OK, so we've just determined above that SDIO isn't currently supported. So why are we enabling/disabling it and not checking any status?
- }
- break;
- case MMC_VDD_29_30:
- case MMC_VDD_30_31:
- Pwr = SDHCI_POWER_300;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 1);- }
- break;
- case MMC_VDD_32_33:
- case MMC_VDD_33_34:
- Pwr = SDHCI_POWER_330;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 1);- }
- break;
- default:
- DEBUG((DEBUG_ERROR, "SD/MMC: Does not support power mode(0x%X)\n", Vcc));
- break;
- }
- if (Pwr == 0) {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_POWER_CTRL, FALSE, 1, &Pwr);
What is 1?
- return;
- }
- Pwr |= SDHCI_POWER_ON;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_POWER_CTRL, FALSE, 1, &Pwr);
What is 1?
- // Set VCCQ
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, TRUE, 4, &Ctrl);
What is 4?
- Ctrl |= Vccq;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, FALSE, 4, &Ctrl);
What is 4?
+}
+UINTN +XenonSetClk (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT32 Clock
- )
+{
- UINT32 Div;
- UINT32 Clk;
- UINT32 Timeout;
- UINT16 Value = 0;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Value);
What is 2?
- if (Clock == 0)
Always {} with if.
- return 0;
- if (Private->ControllerVersion >= SDHCI_SPEC_300) {
- // Version 3.00 Divisors must be a multiple of 2
- if (XENON_MMC_MAX_CLK <= Clock) {
Div = 1;- } else {
for (Div = 2; Div < SDHCI_MAX_DIV_SPEC_300; Div += 2) {if ((XENON_MMC_MAX_CLK / Div) <= Clock)break;}- }
- } else {
- // Version 2.00 Divisors must be a power of 2
- for (Div = 1; Div < SDHCI_MAX_DIV_SPEC_200; Div *= 2) {
if ((XENON_MMC_MAX_CLK / Div) <= Clock)break;- }
- }
- Div >>= 1;
- Clk = (Div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
- Clk |= ((Div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT;
- Clk |= SDHCI_CLOCK_INT_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Clk);
What is 2?
- // Wait max 20 ms
Why?
- Timeout = 200;
And how does 200 delays of 1us end up being related to 20ms?
- do {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &Clk);
What is 2?
- if (Timeout == 0) {
DEBUG((DEBUG_ERROR, "SD/MMC: Internal Clock never stabilised\n"));return -1;- }
- Timeout--;
- gBS->Stall (1);
- } while (!(Clk & SDHCI_CLOCK_INT_STABLE));
- Clk |= SDHCI_CLOCK_CARD_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Clk);
What is 2?
- return 0;
+}
+VOID +XenonPhyInit (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINT32 Var, Wait, Time;
- UINT32 Clock = XENON_MMC_MAX_CLK;
- UINT16 ClkCtrl;
- // Need to disable the clock to set EMMC_PHY_TIMING_ADJUST register
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- // Enable QSP PHASE SELECT
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- Var |= SAMPL_INV_QSP_PHASE_SELECT;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
What is 4?
- // Enable internal clock
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl |= SDHCI_CLOCK_INT_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- //
- // Poll for host MMC PHY clock init to be stable
Excellent - thanks! This is exactly the kind of comment I'm looking for in my previous comments.
- // Wait up to 10ms
- //
- Time = 100;
But how does 100 x 1us end up relating to 10ms?
- while (Time--) {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- if (Var & SDHCI_CLOCK_INT_STABLE) {
break;- }
- gBS->Stall (1);
- }
- if (Time <= 0) {
- DEBUG((DEBUG_ERROR, "SD/MMC: Failed to enable MMC internal clock in Time\n"));
- return;
- }
- // Enable bus clock
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl |= SDHCI_CLOCK_CARD_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- // Delay 200us to Wait for the completion of bus clock
- gBS->Stall (200);
- // Init PHY
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- Var |= PHY_INITIALIZAION;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
What is 4? (OK, I'll stop now, but please provide some #define conveying what the actual significance it.)
- // Add duration of FC_SYNC_RST
- Wait = ((Var >> FC_SYNC_RST_DURATION_SHIFT) & FC_SYNC_RST_DURATION_MASK);
- // Add interval between FC_SYNC_EN and FC_SYNC_RST
- Wait += ((Var >> FC_SYNC_RST_EN_DURATION_SHIFT) & FC_SYNC_RST_EN_DURATION_MASK);
- // Add duration of asserting FC_SYNC_EN
- Wait += ((Var >> FC_SYNC_EN_DURATION_SHIFT) & FC_SYNC_EN_DURATION_MASK);
- // Add duration of Waiting for PHY
- Wait += ((Var >> WAIT_CYCLE_BEFORE_USING_SHIFT) & WAIT_CYCLE_BEFORE_USING_MASK);
- // 4 addtional bus clock and 4 AXI bus clock are required left shift 20 bits
- Wait += 8;
- Wait <<= 20;
- // Use the possibly slowest bus frequency value
- if (Clock == 0) {
- Clock = 100000;
#define?
- }
- // Get the Wait Time in unit of ms
- Wait = Wait / Clock;
- Wait++;
- // Poll for host eMMC PHY init to complete, wait up to 10ms
- Time = 100;
Still not getting the 1 x 100 == 10000.
- while (Time--) {
- Var = SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
- Var &= PHY_INITIALIZAION;
- if (!Var) {
break;- }
- // Wait for host eMMC PHY init to complete
- gBS->Stall (1);
- }
- if (Time <= 0) {
- DEBUG((DEBUG_ERROR, "SD/MMC: Failed to init MMC PHY in Time\n"));
- return;
- }
- return;
+}
+STATIC +VOID +XenonSetPhy (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- UINT8 Timing
- )
+{
- UINT32 Var = 0;
- // Setup pad, set bit[30], bit[28] and bits[26:24]
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, TRUE, 4, &Var);
- Var |= (AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | FC_CMD_RECEN | FC_DQ_RECEN);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, FALSE, 4, &Var);
- //
- // If Timing belongs to high speed, set bit[17] of
- // EMMC_PHY_TIMING_ADJUST register
- //
- if ((Timing == MMC_TIMING_MMC_HS400) ||
(Timing == MMC_TIMING_MMC_HS200) ||(Timing == MMC_TIMING_UHS_SDR50) ||(Timing == MMC_TIMING_UHS_SDR104) ||(Timing == MMC_TIMING_UHS_DDR50) ||(Timing == MMC_TIMING_UHS_SDR25)) {- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
- // Set SLOW_MODE for PHY
- Var |= OUTPUT_QSN_PHASE_SELECT | (1 << 29);
#define?
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, 4, &Var);
- Var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, 4, &Var);
- if (Timing == MMC_TIMING_MMC_HS400) {
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, 4, &Var);
- Var &= ~DQ_ASYNC_MODE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, 4, &Var);
- Var = LOGIC_TIMING_VALUE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_LOGIC_TIMING_ADJUST, FALSE, 4, &Var);
- }
- XenonPhyInit (PciIo);
+}
+STATIC +VOID +XenonConfigureInterrupts (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINT32 Var;
- // Clear interrupt status
- Var = 0xFFFFFFFF;
UINT_MAX? ~0?
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, 4, &Var);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, 4, &Var);
- // Enable only interrupts served by the SD controller
- Var = 0xFFFFFEBF;
Some #define and a ~?
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS_EN, FALSE, 4, &Var);
- // Mask all sdhci interrupt sources
- Var = 0xFFFFFEFF;
Some #define and a ~?
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_SIG_EN, FALSE, 4, &Var);
+}
+// Enable Parallel Transfer Mode +STATIC +VOID +XenonSetParallelTransfer (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, TRUE, 4, &Var);
- if (Enable) {
- Var |= (0x1 << Slot);
- } else {
- Var &= ~(0x1 << Slot);
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, FALSE, 4, &Var);
+}
+STATIC +VOID +XenonSetTuning (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- // Set the Re-Tuning Request functionality
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, TRUE, 4, &Var);
- if (Enable) {
- Var |= RETUNING_COMPATIBLE;
- } else {
- Var &= ~RETUNING_COMPATIBLE;
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, FALSE, 4, &Var);
- // Set the Re-tuning Event Signal Enable
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, TRUE, 4, &Var);
- if (Enable) {
- Var |= SDHCI_RETUNE_EVT_INTSIG;
- } else {
- Var &= ~SDHCI_RETUNE_EVT_INTSIG;
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, FALSE, 4, &Var);
+}
+VOID +XenonReset (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN UINT8 Mask
- )
+{
- UINT32 Timeout = 1000;
Retries?
- UINT8 SwReset;
- SwReset = Mask;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,FALSE,sizeof (SwReset),&SwReset);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,TRUE,sizeof (SwReset),&SwReset);- while (SwReset & Mask) {
- if (Timeout == 0) {
DEBUG((DEBUG_ERROR, "SD/MMC: Reset never completed\n"));return;- }
- Timeout--;
- gBS-> Stall (100);
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,TRUE,sizeof (SwReset),&SwReset);- }
+}
+STATIC +VOID +XenonTransferPio (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN OUT VOID *Buffer,
- IN UINT16 BlockSize,
- IN BOOLEAN Read
- )
+{
- UINTN I;
- UINT8 *Offs;
- //
- // SD stack's intrinsic functions cannot perform properly reading/writing from
- // buffer register, that is why MmioRead/MmioWrite are used. It is temporary
- // solution.
- //
- for (I = 0; I < BlockSize; I += 4) {
- Offs = Buffer + I;
- if (Read) {
*(UINT32 *)Offs = MmioRead32 (0xf06e0020); // SDHCI_BUFFER
#define.
- } else {
MmioWrite32 (0xf06e0020, *(UINT32 *)Offs); // SDHCI_BUFFER
#define.
Also - this driver is still doing PCI semantics, but now it's doing direct access to a hard-coded memory address. That's not very pretty. Can we either obtain this information in a more dynamic fasion, or cut away every last mention of PCI?
- }
- }
+}
+EFI_STATUS +XenonTransferData (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN OUT VOID *Buffer,
- IN UINT32 DataLen,
- IN UINT16 BlockSize,
- IN UINT16 Blocks,
- IN BOOLEAN Read
- )
+{
- UINT32 IntStatus, PresentState, Rdy, Mask, Timeout, Block = 0;
- if (Buffer == NULL) {
- return EFI_DEVICE_ERROR;
- }
- Timeout = 100000; // 100000 * 10 us = 1 second
This line inserted to clarify below comment does not apply to above.
- Rdy = 0x10 | 0x20; // SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL
- Mask = 0x800 | 0x400; // SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE
#defines instead of comments?
- do {
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- if (IntStatus & BIT15) { // SDHCI_INT_ERROR
#define instead of comment?
DEBUG((DEBUG_INFO, "SD/MMC: Error detected in status %0x\n", IntStatus));return EFI_DEVICE_ERROR;- }
- if (IntStatus & Rdy) {
SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);if (!(PresentState & Mask)) {continue;}SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (Rdy),&Rdy);XenonTransferPio (Private, Slot, Buffer, BlockSize, Read);Buffer += BlockSize;if (++Block >= Blocks) {break;}- }
- if (Timeout-- > 0) {
gBS->Stall (10);- } else {
DEBUG((DEBUG_INFO, "SD/MMC: Transfer data timeout\n"));return EFI_TIMEOUT;- }
- } while (!(IntStatus & BIT1)); // SDHCI_INT_DATA_END
#define instead of comment?
(Oh, and please add blank line before return.
- return EFI_SUCCESS;
+}
+EFI_STATUS +XenonInit (
- IN SD_MMC_HC_PRIVATE_DATA *Private
- )
+{
- EFI_PCI_IO_PROTOCOL *PciIo = Private->PciIo;
- XenonSetMpp ();
- XenonReadVersion (PciIo, &Private->ControllerVersion);
- XenonSetFifo (PciIo);
- XenonSetAcg (PciIo, FALSE);
The blank lines between every function call actually makes this function a bit difficult to read. Can calls be grouped as logically connected? Or more comments added?
- // Hyperion has only one port
- XenonSetSlot (PciIo, XENON_MMC_SLOT_ID_HYPERION, TRUE);
- XenonSetPower (PciIo, MMC_VDD_165_195, eMMC_VCCQ_1_8V, XENON_MMC_MODE_SD_SDIO);
- // Set MAX_CLOCK for configuring PHY
- XenonSetClk (PciIo, Private, XENON_MMC_MAX_CLK);
- XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50);
- XenonConfigureInterrupts (PciIo);
- // Enable parallel transfer
- XenonSetParallelTransfer (PciIo, XENON_MMC_SLOT_ID_HYPERION, TRUE);
- XenonSetTuning (PciIo, XENON_MMC_SLOT_ID_HYPERION, FALSE);
- XenonSetAcg (PciIo, TRUE);
- XenonSetClk (PciIo, Private, XENON_MMC_BASE_CLK);
- XenonPhyInit (PciIo);
- return EFI_SUCCESS;
+} diff --git a/Drivers/SdMmc/XenonSdhci.h b/Drivers/SdMmc/XenonSdhci.h new file mode 100644 index 0000000..a7b30c3 --- /dev/null +++ b/Drivers/SdMmc/XenonSdhci.h @@ -0,0 +1,278 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd.
+Marvell BSD License Option
+If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met:
+* Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
+* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#include "../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h"
Use local copy.
+#include <Library/IoLib.h>
+#define SD_BAR_INDEX 0
+/* Register Offset of SD Host Controller SOCP self-defined register */
+#define SDHC_IPID 0x0100 +#define SDHC_SYS_CFG_INFO 0x0104 +#define SLOT_TYPE_SDIO_SHIFT 24 +#define SLOT_TYPE_EMMC_MASK 0xff +#define SLOT_TYPE_EMMC_SHIFT 16 +#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xff +#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8
+#define SDHC_SYS_OP_CTRL 0x0108 +#define AUTO_CLKGATE_DISABLE_MASK (0x1<<20) +#define SDCLK_IDLEOFF_ENABLE_SHIFT 8 +#define SLOT_ENABLE_SHIFT 0
+#define SDHC_SYS_EXT_OP_CTRL 0x010c +#define SDHC_TEST_OUT 0x0110 +#define SDHC_TESTOUT_MUXSEL 0x0114
+#define SDHC_SLOT_EXT_INT_STATUS 0x0120 +#define SDHC_SLOT_EXT_ERR_STATUS 0x0122 +#define SDHC_SLOT_EXT_INT_STATUS_EN 0x0124 +#define SDHC_SLOT_EXT_ERR_STATUS_EN 0x0126
+#define SDHC_SLOT_OP_STATUS_CTRL 0x0128 +#define TUNING_PROG_FIXED_DELAY_MASK 0x7ff +#define FORCE_SEL_INVERSE_CLK_SHIFT 11
+#define SDHC_SLOT_FIFO_CTRL 0x012c
+#define SDHC_SLOT_eMMC_CTRL 0x0130 +#define ENABLE_DATA_STROBE_SHIFT 24 +#define SET_EMMC_RSTN_SHIFT 16 +#define eMMC_VCCQ_MASK 0x3 +#define eMMC_VCCQ_1_8V 0x1 +#define eMMC_VCCQ_1_2V 0x2 +#define eMMC_VCCQ_3_3V 0x3
+#define SDHC_SLOT_OUTPUT_DLY_CTRL 0x0134 +#define SDHC_SLOT_DCM_CTRL 0x0137
+#define SDHC_SLOT_DLL_CTRL 0x0138 +#define SELECT_DEF_DLL 0x1
+#define SDHC_SLOT_DLL_PHASE_SEL 0x013c +#define DLL_UPDATE_STROBE 7
+#define SDHC_SLOT_STROBE_DLY_CTRL 0x0140 +#define STROBE_DELAY_FIXED_MASK 0xffff
+#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144 +#define RETUNING_COMPATIBLE 0x1
+#define SDHC_SLOT_AUTO_RETUNING_CTRL 0x0148 +#define ENABLE_AUTO_RETUNING 0x1
+#define SDHC_SLOT_EXT_PRESENT_STATE 0x014c +#define SDHC_SLOT_DLL_CUR_DLY_VAL 0x0150 +#define SDHC_SLOT_TUNING_CUR_DLY_VAL 0x0154 +#define SDHC_SLOT_STROBE_CUR_DLY_VAL 0x0158 +#define SDHC_SLOT_SUB_CMD_STRL 0x015c
+#define SDHC_SLOT_CQ_TASK_INFO 0x0160
+#define SDHC_SLOT_TUNING_DEBUG_INFO 0x01f0 +#define SDHC_SLOT_DATAIN_DEBUG_INFO 0x01f4
+#define XENON_MMC_MAX_CLK 400000000
HZ? (A comment would suffice.)
+#define XENON_MMC_CLK_RATIO 2046 +#define XENON_MMC_BASE_CLK XENON_MMC_MAX_CLK / XENON_MMC_CLK_RATIO
+#define XENON_MMC_CMD_MAX_TIMEOUT 3200 +#define XENON_MMC_CMD_DEFAULT_TIMEOUT 100
+/* Tuning Parameter */ +#define TMR_RETUN_NO_PRESENT 0xf +#define XENON_MAX_TUN_COUNT 0xb
+#define EMMC_PHY_REG_BASE 0x170 +#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE +#define OUTPUT_QSN_PHASE_SELECT (1 << 17) +#define SAMPL_INV_QSP_PHASE_SELECT (1 << 18) +#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 +#define PHY_INITIALIZAION (1 << 31) +#define WAIT_CYCLE_BEFORE_USING_MASK 0xf +#define WAIT_CYCLE_BEFORE_USING_SHIFT 12 +#define FC_SYNC_EN_DURATION_MASK 0xf +#define FC_SYNC_EN_DURATION_SHIFT 8 +#define FC_SYNC_RST_EN_DURATION_MASK 0xf +#define FC_SYNC_RST_EN_DURATION_SHIFT 4 +#define FC_SYNC_RST_DURATION_MASK 0xf +#define FC_SYNC_RST_DURATION_SHIFT 0
+#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4) +#define DQ_ASYNC_MODE (1 << 4) +#define DQ_DDR_MODE_SHIFT 8 +#define DQ_DDR_MODE_MASK 0xff +#define CMD_DDR_MODE (1 << 16)
+#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8) +#define REC_EN_SHIFT 24 +#define REC_EN_MASK 0xf +#define FC_DQ_RECEN (1 << 24) +#define FC_CMD_RECEN (1 << 25) +#define FC_QSP_RECEN (1 << 26) +#define FC_QSN_RECEN (1 << 27) +#define OEN_QSN (1 << 28) +#define AUTO_RECEN_CTRL (1 << 30)
+#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc) +#define EMMC_PHY_PAD_CONTROL2 (EMMC_PHY_REG_BASE + 0x10) +#define EMMC_PHY_DLL_CONTROL (EMMC_PHY_REG_BASE + 0x14) +#define DLL_DELAY_TEST_LOWER_SHIFT 8 +#define DLL_DELAY_TEST_LOWER_MASK 0xff +#define DLL_BYPASS_EN 0x1
+#define EMMC_LOGIC_TIMING_ADJUST (EMMC_PHY_REG_BASE + 0x18) +#define EMMC_LOGIC_TIMING_ADJUST_LOW (EMMC_PHY_REG_BASE + 0x1c)
+#define MVEBU_IP_CONFIG_REG (0xf0000000 + 0x6F4100)
Again, slightly uncomfortable with this hard-coded address. (But depending on what you do about my comment on where this is actually used, could possibly be dropped.)
+#define LOGIC_TIMING_VALUE 0x5a54 /* Recommend by HW team */
+/* Hyperion only have one slot 0 */
What is Hyperion? Internal name of a specific devboard?
Regards,
Leif
+#define XENON_MMC_SLOT_ID_HYPERION (0)
+#define MMC_TIMING_LEGACY 0 +#define MMC_TIMING_MMC_HS 1 +#define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 3 +#define MMC_TIMING_UHS_SDR25 4 +#define MMC_TIMING_UHS_SDR50 5 +#define MMC_TIMING_UHS_SDR104 6 +#define MMC_TIMING_UHS_DDR50 7 +#define MMC_TIMING_MMC_HS200 8 +#define MMC_TIMING_MMC_HS400 10
+/* Data time out default value 0xE: TMCLK x 227 */ +#define DATA_TIMEOUT_DEF_VAL 0xe
+/* SDMA start address should allign with 0x8, align mask 0x7 */ +#define DMA_START_ADDR_ALIGN_MASK 0x7
+#define SDHCI_RETUNE_EVT_INTSIG 0x00001000
+/* MMC modes */ +#define XENON_MMC_MODE_EMMC 0 +#define XENON_MMC_MODE_SD_SDIO 1
+/* MMC Voltage */ +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
+/* SDHCI FLAGS */ +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E
+#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_SHIFT 6 +#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK_LEN 8 +#define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_INT_STABLE 0x0002 +#define SDHCI_CLOCK_INT_EN 0x0001
+#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2
+#define SDHCI_SIGNAL_ENABLE 0x38
+#define SDHCI_MAX_DIV_SPEC_200 256 +#define SDHCI_MAX_DIV_SPEC_300 2046
+UINTN +XenonSetClk (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT32 Clock
- );
+VOID +XenonPhyInit (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- );
+VOID +XenonReset (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN UINT8 Mask
- );
+EFI_STATUS +XenonTransferData (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN OUT VOID *Buffer,
- IN UINT32 DataLen,
- IN UINT16 BlockSize,
- IN UINT16 Blocks,
- IN BOOLEAN Read
- );
+EFI_STATUS +XenonInit (
- IN SD_MMC_HC_PRIVATE_DATA *Private
- );
+EFI_STATUS +SdCardSendStatus (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
- IN UINT8 Slot,
- IN UINT16 Rca,
- OUT UINT32 *DevStatus
- );
-- 1.8.3.1
Hi Leif,
Thanks a lot for your remarks. Please find comments inline.
Best Regards, Jan
- //
- // Get SD/MMC Pci Host Controller Slot info
- //
- Status = SdMmcHcGetSlotInfo (PciIo, &FirstBar, &SlotNum);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Support64BitDma = TRUE;
- for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) {
- for (Slot = 0; Slot < (XENON_MMC_SLOT_ID_HYPERION + 1); Slot++) {
Since all this line is currently doing is hardcoding that this loop should only be executed once, could an intermediate define of ..._NUM_SLOTS be introduced, if we're expecting this driver to be reusable for anything else? (And if we don't, can we drop the loop bit?)
Indeed, current solution isn't reusable. We should drop the loop.
- //
- // Override capabilities structure - only 4 Bit width bus is supported
- // by HW and also force using SDR25 mode
- //
- Private->Capability[Slot].Sdr104 = 0;
- Private->Capability[Slot].Ddr50 = 0;
- Private->Capability[Slot].Sdr50 = 0;
- Private->Capability[Slot].BusWidth8 = 0;
And if you are importing the whole driver, I'm guessing you can get rid of this type of thing completely?
We want to have as small diff as possible in comparison to MdeModulePkg stack. If we wouldn't do this here, few other steps in init sequence will have to be changed. Overriding capability fields in one place (which allows to clearly see what are differences between HW capabilities and software support) is cleaner way in my opinion. What do you think?
- if (Private->Capability[Slot].BaseClkFreq == 0) {
Private->Capability[Slot].BaseClkFreq = 0xff;- }
- DumpCapabilityReg (Slot, &Private->Capability[Slot]);
- Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); if (EFI_ERROR (Status)) { continue;
@@ -624,28 +629,8 @@ SdMmcPciHcDriverBindingStart ( continue; }
- //
- // Reset the specified slot of the SD/MMC Pci Host Controller
- //
- Status = SdMmcHcReset (PciIo, Slot);
- if (EFI_ERROR (Status)) {
continue;- }
- //
- // Check whether there is a SD/MMC card attached
- //
- Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent);
- if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) {
continue;- } else if (!MediaPresent) {
DEBUG ((DEBUG_ERROR, "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n", Slot));continue;- }
- Status = SdMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]);
- if (EFI_ERROR (Status)) {
continue;- }
// Perform Xenon-specific init sequence
XenonInit (Private);
Private->Slot[Slot].MediaPresent = TRUE; Private->Slot[Slot].Initialized = TRUE;
@@ -889,6 +874,220 @@ SdMmcPciHcDriverBindingStop ( }
/**
- Check if card is ready for next data transfer by reading its status.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot The slot number of the device to send the command to.
- @param[in] Rca The relative device address of addressed device.
- @param[in] Timeout The timeout in miliseconds.
- @retval EFI_SUCCESS Card is ready for next data transfer.
- @retval EFI_DEVICE_ERROR Card status is erroneous.
- @retval EFI_TIMEOUT Card is busy.
+**/ +STATIC +EFI_STATUS +SdMmcIsReady (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN UINTN Timeout
- )
+{
- EFI_STATUS Status;
- UINT32 DevStatus;
- do {
- Status = SdCardSendStatus (This, Slot, Rca, &DevStatus);
- if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Cannot read SD status\n"));return Status;- }
- // Check device status
- if ((DevStatus & (1 << 8)) && (DevStatus & (0xf << 9)) != (7 << 9)) {
Some macros here to show which flags are being checked, please?
Yes, whole function should be corrected in terms of magic numbers.
break;- } else if (DevStatus & ~0x0206BF7F) {
More macros, please.
DEBUG ((DEBUG_ERROR, "SD Status error\n"));return EFI_DEVICE_ERROR;- }
- gBS->Stall (1000);
And a comment with that delay please. (Why? Why this value?)
Ok.
- } while (Timeout--);
- if (Timeout <= 0) {
- DEBUG ((DEBUG_ERROR, "SD Status timeout\n"));
- return EFI_TIMEOUT;
- }
- if (DevStatus & (1 << 7)) {
Macro?
Ok
- DEBUG ((DEBUG_ERROR, "SD switch error\n"));
- return EFI_DEVICE_ERROR;
- }
- return EFI_SUCCESS;
+}
+STATIC +EFI_STATUS +CheckParameters (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN UINT8 Slot
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if ((This == NULL) || (Packet == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- }
- if (!Private->Slot[Slot].Enable) {
- return EFI_INVALID_PARAMETER;
- }
- if (!Private->Slot[Slot].MediaPresent) {
- return EFI_NO_MEDIA;
- }
- // Currently we don't support SDIO
- if (Packet->SdMmcCmdBlk->CommandIndex == SDIO_SEND_OP_COND) {
- return EFI_DEVICE_ERROR;
- }
- return EFI_SUCCESS;
+}
+/**
- Send command SD_STOP_TRANSMISSION to stop multiple block transfer.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot The slot number of the device to send the command to.
- @retval EFI_SUCCESS The request is executed successfully.
- @retval Others The request could not be executed successfully.
+**/ +STATIC +EFI_STATUS +SdMmcSendStopTransmission (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot
- )
+{
- EFI_STATUS Status;
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
- ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
- ZeroMem (&Packet, sizeof (Packet));
- Packet.SdMmcCmdBlk = &SdMmcCmdBlk;
- Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
- Packet.Timeout = 2500 * 1000; // SD generic timeout
Sure, but can we have some defines for it please?
Ok, will replace comment with define.
- SdMmcCmdBlk.CommandIndex = SD_STOP_TRANSMISSION;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
- SdMmcCmdBlk.CommandArgument = 0;
- Status = This->PassThru (This, Slot, &Packet, NULL);
- return Status;
+}
+STATIC +EFI_STATUS +WaitForInhibit (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN UINT8 Slot,
- IN BOOLEAN DataTransfer
- )
+{
- UINT32 Mask, PresentState, Time = 0;
- UINT32 CmdTimeout = XENON_MMC_CMD_DEFAULT_TIMEOUT;
- if (Packet->SdMmcCmdBlk != NULL) {
- Mask = BIT0; // SDHCI_CMD_INHIBIT
- }
- if (DataTransfer != FALSE) {
- Mask = BIT1; // SDHCI_DATA_INHIBIT
- }
- //
- // We shouldn't wait for data inhibit for stop commands, even
- // though they might use busy signaling
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_STOP_TRANSMISSION)
- Mask &= ~BIT1;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);- while (PresentState & Mask) {
- if (Time >= CmdTimeout) {
if (2 * CmdTimeout <= XENON_MMC_CMD_MAX_TIMEOUT) {CmdTimeout += CmdTimeout;} else {if (Packet->SdMmcCmdBlk != NULL) {XenonReset (Private, Slot, 0x02); // CMD resetCould replace the comment with a #define?
Ok.
}if (DataTransfer) {XenonReset (Private, Slot, 0x04); // DATA resetCould replace the comment with a #define?
Ok.
}DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Timeout...\n"));return EFI_TIMEOUT;}- }
- Time++;
- gBS->Stall (1000);
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);- }
- return EFI_SUCCESS;
+}
+// Variable to store current card's Rca - used in polling card status +STATIC UINT16 CurrRca = 0;
I think this should have an m-prefix.
Agree.
+/** Sends SD command to an SD card that is attached to the SD controller.
The PassThru() function sends the SD command specified by Packet to the SD card @@ -934,86 +1133,351 @@ SdMmcPassThruPassThru ( IN EFI_EVENT Event OPTIONAL ) {
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_MMC_HC_TRB *Trb;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- INTN Ret;
- UINTN *Data, DataLen, Index;
- UINT32 Argument, Response[4], Retry, Stat, Mask;
Please not Stat and Status in the same function.
Ok, will change first one.
- UINT16 BlockSize, BlkCount;
- UINT16 Cmd, IntStatus, TimeoutCtrl, Mode, BlkSizeReg;
- BOOLEAN MultiFlag = FALSE, SetRcaFlag = FALSE, Read = FALSE;
- BOOLEAN DataTransfer;
- Data = NULL;
- DataLen = 0;
- Retry = 1000;
Could we have a define for that?
Ok.
- Stat = 0;
- Ret = 0;
- BlockSize = 0x200;
SIZE_512B? (We don't have a global define for that, but it would make it more readable.)
Ok.
- BlkCount = 0;
- Status = CheckParameters (This, Packet, Slot);
- if (EFI_ERROR(Status)) {
- return Status;
- }
- if ((This == NULL) || (Packet == NULL)) {
- return EFI_INVALID_PARAMETER;
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- //
- // Mark if this is multiblock data transfer since some special
- // acctions must be taken in such circumstances, i.e. it's necessary
- // to send SD_STOP_TRANSMISSION command.
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_WRITE_MULTIPLE_BLOCK ||
Packet->SdMmcCmdBlk->CommandIndex == SD_READ_MULTIPLE_BLOCK) {- MultiFlag = TRUE; }
- if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
- return EFI_INVALID_PARAMETER;
- //
- // Mark if this is command to set new relative card address (RCA),
- // since it's necessary to have updated copy of current RCA in this
- // layer - used in checking card status.
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_SET_RELATIVE_ADDR) {
- SetRcaFlag = TRUE; }
- if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- // Prepare data transfer's flags
- if (((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) ||
((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL))) {- DataTransfer = FALSE; }
- if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
- DataLen = Packet->InTransferLength;
- Data = Packet->InDataBuffer;
- Read = TRUE;
- DataTransfer = TRUE; }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
- DataLen = Packet->OutTransferLength;
- Data = Packet->OutDataBuffer;
- DataTransfer = TRUE;
- }
- if (!Private->Slot[Slot].Enable) {
- return EFI_INVALID_PARAMETER;
- // Clear ERROR_IRQ status
- IntStatus = 0xFFFF;
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_ERR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Cannot clear ERROR_IRQ status\n"));
- return Status; }
- if (!Private->Slot[Slot].MediaPresent) {
- return EFI_NO_MEDIA;
- // Clear IRQ status
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Cannot clear IRQ status\n"));
- return Status; }
- if (!Private->Slot[Slot].Initialized) {
- return EFI_DEVICE_ERROR;
- WaitForInhibit (Private, Packet, Slot, DataTransfer);
- Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
- if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
- Cmd |= BIT5;
Is it possible to give this bit a more descriprive name?
Please see below comment.
}
- Trb = SdMmcCreateTrb (Private, Slot, Packet, Event);
- if (Trb == NULL) {
- return EFI_OUT_OF_RESOURCES;
- if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
- switch (Packet->SdMmcCmdBlk->ResponseType) {
case SdMmcResponseTypeR1:case SdMmcResponseTypeR5:case SdMmcResponseTypeR6:case SdMmcResponseTypeR7:Cmd |= (BIT1 | BIT3 | BIT4);Is it possible to give these bits more descriprive names? If not, please sort them in descending order. (Same applies to rest of cases.)
This switch-case statement is taken from MdeModulePkg driver and ResponsesTypes (with according BITs in CMD) are well documented in SD specification. But if you think it isn't enough, I will add #defines.
break;case SdMmcResponseTypeR2:Cmd |= (BIT0 | BIT3);break;case SdMmcResponseTypeR3:case SdMmcResponseTypeR4:Cmd |= BIT1;break;case SdMmcResponseTypeR1b:case SdMmcResponseTypeR5b:Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);break;default:ASSERT (FALSE);Should this not return also? In a release build, this would just keep executing in an unknown state.
Yes, agree.
break;- } }
- //
- // Immediately return for async I/O.
- //
- if (Event != NULL) {
- return EFI_SUCCESS;
- if ((DataLen % BlockSize) != 0) {
- if (DataLen < BlockSize) {
BlockSize = (UINT16)DataLen;- } }
- BlkCount = (UINT16) (DataLen / BlockSize);
- if (DataTransfer) {
- // Set default timeout value
- TimeoutCtrl = 0xE;
#define?
Ok.
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_TIMEOUT_CTRL,FALSE,sizeof (TimeoutCtrl),&TimeoutCtrl);- Mode = 0x02; // SDHCI_TRNS_BLK_CNT_EN
- if (BlkCount > 1) {
Mode |= 0x20; // SDHCI_TRNS_MULTI- }
- if (Read) {
Mode |= 0x10; // SDHCI_TRNS_READ#defines instead of comments?
Ok.
- }
- //
- // Wait async I/O list is empty before execute sync I/O operation.
- //
- while (TRUE) {
- OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
- if (IsListEmpty (&Private->Queue)) {
gBS->RestoreTPL (OldTpl);
- // Fill BlockSize register
- BlkSizeReg = (0x7 << 12) | (BlockSize & 0xFFF);
#defines?
(SIZE_4KB - 1)?
Ok.
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_BLK_SIZE,FALSE,sizeof (BlkSizeReg),&BlkSizeReg);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_BLK_COUNT,FALSE,sizeof (BlkCount),&BlkCount);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_TRANS_MOD,FALSE,sizeof (Mode),&Mode);- }
- Argument = Packet->SdMmcCmdBlk->CommandArgument;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_ARG1,FALSE,sizeof (Argument),&Argument);- // Execute cmd
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_COMMAND,FALSE,sizeof (Cmd),&Cmd);- Mask = BIT0; // SDHCI_INT_RESPONSE
#define instead of comment?
Ok. Will apply to every comment of this type.
- if (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b ||
Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b) {- Mask |= BIT1;
#define instead of comment?
- }
- do {
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER;- }
- if (IntStatus & BIT15) { // SDHCI_INT_STATUS
#define instead of comment?
DEBUG((DEBUG_INFO, "MvSdMmcPassThru: SDHCI_INT_ERROR stat:%x\n",IntStatus)); break;
gBS->RestoreTPL (OldTpl);
}
Status = SdMmcWaitTrbEnv (Private, Trb);
if (EFI_ERROR (Status)) {
goto Done;
- // Stall for 100 microseconds
Yeah, that's what the line below says on its own. Why? Why this period?
Ok, we will add more precise description to every delay.
- gBS->Stall (100);
- if (--Retry == 0) {
break;- }
- } while ((IntStatus & Mask) != Mask);
- if (Retry == 0) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Rx timeout\n"));
- return EFI_TIMEOUT; }
- Status = SdMmcExecTrb (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- if ((IntStatus & (BIT15 | Mask)) == Mask) {
#define?
Ok.
- if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
for (Index = 0; Index < 4; Index++) {SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_RESPONSE + Index * 4,TRUE,sizeof (UINT32),sizeof (Response[Index])? (Or sizeof (*Response)?)
Yes, first option will suit here.
&Response[Index]);}CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));//// Update RCA of current card in order to use it later// for polling card status//if (SetRcaFlag)Always {} with if.
Ok.
CurrRca = Packet->SdMmcStatusBlk->Resp0 >> 16;#define?
As with my comment to switch-case statement. Such shift for RCA is commonly used in MdeModulePkg, but for clarity we will make it #define.
- }
- IntStatus = Mask;
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- } else {
- Ret = -1; }
- Status = SdMmcWaitTrbResult (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- if (!Ret && DataTransfer) {
- Status = XenonTransferData (Private, Slot, Data, DataLen, BlockSize, BlkCount, Read); }
-Done:
- if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
- FreePages (Trb->AdmaDesc, Trb->AdmaPages);
- // SDHCI_QUIRK_WAIT_SEND_CMD - 1 milisecond delay
The code already says it's a 1 milisecond delay. Why is there a delay, and why is it of this period?
Will add proper comment.
- gBS->Stall (1000);
- // Save current IRQ status
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- // Clear IRQ
- Stat = 0xFFFFFFFFULL;
Stat (hopefully to be renamed) is UINT32, so why ULL? But would also look much better with a #define.
ULL sufix isn't necessary here. Ok.
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (Stat),&Stat);- //
- // There are two quirks for DataTransfer commands:
- // 1. For multipleblock write/read it's necessary to issue
- // SD_STOP_TRANSMISSION command
- // 2. For every write data comand, it's necessary to poll for
- // card status before issuing next data transfer
- //
- if (!Ret && DataTransfer) {
- if (MultiFlag) {
SdMmcSendStopTransmission(This, Slot);- }
- if (!Read) {
return SdMmcIsReady (This, Slot, CurrRca, 1000);What is 1000?
It's max timeout value for which we will poll device status. Will add proper define to make it more clear.
- }
- return EFI_SUCCESS; }
- if (Trb != NULL) {
- FreePool (Trb);
- // Check previously saved IRQ status for non-data commands
- if (IntStatus & BIT15) {
- if (Packet->SdMmcCmdBlk != NULL) {
XenonReset (Private, Slot, 0x02); // CMD#define instead of comment.
Ok, will apply for whole file.
- }
- if (DataTransfer) {
XenonReset (Private, Slot, 0x04); // DATA#define instead of comment.
- }
- if (IntStatus & (0x10000 | 0x100000)) { // SDHCI_INT_TIMEOUT
#defines.
DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Timeout!\n"));return EFI_TIMEOUT;} else {
return EFI_DEVICE_ERROR;}
} else {
return EFI_SUCCESS; }
return Status;
diff --git a/Drivers/SdMmc/MvSdMmcPciHcDxe.inf b/Drivers/SdMmc/MvSdMmcPciHcDxe.inf new file mode 100644 index 0000000..a4f66e9 --- /dev/null +++ b/Drivers/SdMmc/MvSdMmcPciHcDxe.inf @@ -0,0 +1,75 @@ +#/******************************************************************************* +#Copyright (C) 2016 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modification, +#are permitted provided that the following conditions are met: +# +#* Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +#* Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +#* Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#*******************************************************************************/
+[Defines]
- INF_VERSION = 0x00010005
0019
Ok.
- BASE_NAME = MvSdMmcPciHcDxe
- MODULE_UNI_FILE = ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.uni
Refer to local copies.
Ok.
- FILE_GUID = 5b5b83b8-52b8-4d02-b92b-c84a4dfb539d
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeSdMmcPciHcDxe
+[Sources]
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
Refer to local copies.
Ok.
- MvSdMmcPciHcDxe.c
- XenonSdhci.c
- XenonSdhci.h
+[Packages]
- MdePkg/MdePkg.dec
+[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- DevicePathLib
- MemoryAllocationLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- UefiLib
- UefiRuntimeServicesTableLib
+[Protocols]
- gEfiDevicePathProtocolGuid ## TO_START
- gEfiPciIoProtocolGuid ## TO_START
- gEfiSdMmcPassThruProtocolGuid ## BY_START
+[UserExtensions.TianoCore."ExtraFiles"]
- SdMmcPciHcDxeExtra.uni
diff --git a/Drivers/SdMmc/XenonSdhci.c b/Drivers/SdMmc/XenonSdhci.c new file mode 100755 index 0000000..6a20105 --- /dev/null +++ b/Drivers/SdMmc/XenonSdhci.c @@ -0,0 +1,661 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd.
+Marvell BSD License Option
+If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met:
+* Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
+* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#include "XenonSdhci.h"
+STATIC +VOID +XenonSetMpp (
- VOID
- )
+{
- UINT32 Reg;
- // Set eMMC/SD PHY output instead of MPPs
As pin control configuration, isn't this something that should be done in Armada70x0Lib or similar?
This code will be moved in next spin.
- Reg = MmioRead32 (MVEBU_IP_CONFIG_REG);
- Reg &= ~(1 << 0);
#define
Ok.
- MmioWrite32 (MVEBU_IP_CONFIG_REG, Reg);
+}
+STATIC +VOID +XenonReadVersion (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- OUT UINT32 *ControllerVersion
- )
+{
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_CTRL_VER, TRUE, 2, ControllerVersion);
What is 2?
All of these '1', '2', and '4' are registers' sizes (I wouldn't write it so many times :) ). Define will be used to improve readability.
+}
+STATIC +VOID +XenonSetFifo (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINTN Data = 0x315;
#define
Ok.
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, 4, &Data);
What is 4?
+}
+// Auto Clock Gating +STATIC +VOID +XenonSetAcg (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, 4, &Var);
What is 4?
- if (Enable) {
- Var &= ~AUTO_CLKGATE_DISABLE_MASK;
- } else {
- Var |= AUTO_CLKGATE_DISABLE_MASK;
- }
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, 4, &Var);
What is 4?
+}
+STATIC +VOID +XenonSetSlot (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, 4, &Var);
What is 4?
- if (Enable) {
- Var |= ((0x1 << Slot) << SLOT_ENABLE_SHIFT);
- } else {
- Var &= ~((0x1 << Slot) << SLOT_ENABLE_SHIFT);
- }
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, 4, &Var);
What is 4?
+}
+STATIC +VOID +XenonSetSdio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINTN Voltage
- )
+{
- // Currently SDIO isn't supported
- return;
+}
+STATIC +VOID +XenonSetPower (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Vcc,
- IN UINT32 Vccq,
- IN UINT8 Mode
- )
+{
- UINT8 Pwr = 0;
- UINT32 Ctrl = 0;
- // Set VCC
- switch (Vcc) {
- case MMC_VDD_165_195:
- Pwr = SDHCI_POWER_180;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 0);OK, so we've just determined above that SDIO isn't currently supported. So why are we enabling/disabling it and not checking any status?
SDIO isn't currently supported and it's stub which may be improved (implemented correctly) in future. For now, code silently go through this. Do you think it should be removed for now?
- }
- break;
- case MMC_VDD_29_30:
- case MMC_VDD_30_31:
- Pwr = SDHCI_POWER_300;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 1);- }
- break;
- case MMC_VDD_32_33:
- case MMC_VDD_33_34:
- Pwr = SDHCI_POWER_330;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 1);- }
- break;
- default:
- DEBUG((DEBUG_ERROR, "SD/MMC: Does not support power mode(0x%X)\n", Vcc));
- break;
- }
- if (Pwr == 0) {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_POWER_CTRL, FALSE, 1, &Pwr);
What is 1?
- return;
- }
- Pwr |= SDHCI_POWER_ON;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_POWER_CTRL, FALSE, 1, &Pwr);
What is 1?
- // Set VCCQ
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, TRUE, 4, &Ctrl);
What is 4?
- Ctrl |= Vccq;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, FALSE, 4, &Ctrl);
What is 4?
+}
+UINTN +XenonSetClk (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT32 Clock
- )
+{
- UINT32 Div;
- UINT32 Clk;
- UINT32 Timeout;
- UINT16 Value = 0;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Value);
What is 2?
- if (Clock == 0)
Always {} with if.
Ok.
- return 0;
- if (Private->ControllerVersion >= SDHCI_SPEC_300) {
- // Version 3.00 Divisors must be a multiple of 2
- if (XENON_MMC_MAX_CLK <= Clock) {
Div = 1;- } else {
for (Div = 2; Div < SDHCI_MAX_DIV_SPEC_300; Div += 2) {if ((XENON_MMC_MAX_CLK / Div) <= Clock)break;}- }
- } else {
- // Version 2.00 Divisors must be a power of 2
- for (Div = 1; Div < SDHCI_MAX_DIV_SPEC_200; Div *= 2) {
if ((XENON_MMC_MAX_CLK / Div) <= Clock)break;- }
- }
- Div >>= 1;
- Clk = (Div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
- Clk |= ((Div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT;
- Clk |= SDHCI_CLOCK_INT_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Clk);
What is 2?
- // Wait max 20 ms
Why?
Will add more descriptive comment.
- Timeout = 200;
And how does 200 delays of 1us end up being related to 20ms?
All of these mismatch between comment and delay's value are simply that text doesn't follow with changes in code. Will review whole file in terms of this, thanks.
- do {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &Clk);
What is 2?
- if (Timeout == 0) {
DEBUG((DEBUG_ERROR, "SD/MMC: Internal Clock never stabilised\n"));return -1;- }
- Timeout--;
- gBS->Stall (1);
- } while (!(Clk & SDHCI_CLOCK_INT_STABLE));
- Clk |= SDHCI_CLOCK_CARD_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Clk);
What is 2?
- return 0;
+}
+VOID +XenonPhyInit (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINT32 Var, Wait, Time;
- UINT32 Clock = XENON_MMC_MAX_CLK;
- UINT16 ClkCtrl;
- // Need to disable the clock to set EMMC_PHY_TIMING_ADJUST register
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- // Enable QSP PHASE SELECT
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- Var |= SAMPL_INV_QSP_PHASE_SELECT;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
What is 4?
- // Enable internal clock
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl |= SDHCI_CLOCK_INT_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- //
- // Poll for host MMC PHY clock init to be stable
Excellent - thanks! This is exactly the kind of comment I'm looking for in my previous comments.
- // Wait up to 10ms
- //
- Time = 100;
But how does 100 x 1us end up relating to 10ms?
- while (Time--) {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- if (Var & SDHCI_CLOCK_INT_STABLE) {
break;- }
- gBS->Stall (1);
- }
- if (Time <= 0) {
- DEBUG((DEBUG_ERROR, "SD/MMC: Failed to enable MMC internal clock in Time\n"));
- return;
- }
- // Enable bus clock
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl |= SDHCI_CLOCK_CARD_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- // Delay 200us to Wait for the completion of bus clock
- gBS->Stall (200);
- // Init PHY
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- Var |= PHY_INITIALIZAION;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
What is 4? (OK, I'll stop now, but please provide some #define conveying what the actual significance it.)
- // Add duration of FC_SYNC_RST
- Wait = ((Var >> FC_SYNC_RST_DURATION_SHIFT) & FC_SYNC_RST_DURATION_MASK);
- // Add interval between FC_SYNC_EN and FC_SYNC_RST
- Wait += ((Var >> FC_SYNC_RST_EN_DURATION_SHIFT) & FC_SYNC_RST_EN_DURATION_MASK);
- // Add duration of asserting FC_SYNC_EN
- Wait += ((Var >> FC_SYNC_EN_DURATION_SHIFT) & FC_SYNC_EN_DURATION_MASK);
- // Add duration of Waiting for PHY
- Wait += ((Var >> WAIT_CYCLE_BEFORE_USING_SHIFT) & WAIT_CYCLE_BEFORE_USING_MASK);
- // 4 addtional bus clock and 4 AXI bus clock are required left shift 20 bits
- Wait += 8;
- Wait <<= 20;
- // Use the possibly slowest bus frequency value
- if (Clock == 0) {
- Clock = 100000;
#define?
Ok.
- }
- // Get the Wait Time in unit of ms
- Wait = Wait / Clock;
- Wait++;
- // Poll for host eMMC PHY init to complete, wait up to 10ms
- Time = 100;
Still not getting the 1 x 100 == 10000.
As above.
- while (Time--) {
- Var = SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
- Var &= PHY_INITIALIZAION;
- if (!Var) {
break;- }
- // Wait for host eMMC PHY init to complete
- gBS->Stall (1);
- }
- if (Time <= 0) {
- DEBUG((DEBUG_ERROR, "SD/MMC: Failed to init MMC PHY in Time\n"));
- return;
- }
- return;
+}
+STATIC +VOID +XenonSetPhy (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- UINT8 Timing
- )
+{
- UINT32 Var = 0;
- // Setup pad, set bit[30], bit[28] and bits[26:24]
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, TRUE, 4, &Var);
- Var |= (AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | FC_CMD_RECEN | FC_DQ_RECEN);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, FALSE, 4, &Var);
- //
- // If Timing belongs to high speed, set bit[17] of
- // EMMC_PHY_TIMING_ADJUST register
- //
- if ((Timing == MMC_TIMING_MMC_HS400) ||
(Timing == MMC_TIMING_MMC_HS200) ||(Timing == MMC_TIMING_UHS_SDR50) ||(Timing == MMC_TIMING_UHS_SDR104) ||(Timing == MMC_TIMING_UHS_DDR50) ||(Timing == MMC_TIMING_UHS_SDR25)) {- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
- // Set SLOW_MODE for PHY
- Var |= OUTPUT_QSN_PHASE_SELECT | (1 << 29);
#define?
Ok, as I wrote above, we will replace comments with #defines.
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, 4, &Var);
- Var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, 4, &Var);
- if (Timing == MMC_TIMING_MMC_HS400) {
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, 4, &Var);
- Var &= ~DQ_ASYNC_MODE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, 4, &Var);
- Var = LOGIC_TIMING_VALUE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_LOGIC_TIMING_ADJUST, FALSE, 4, &Var);
- }
- XenonPhyInit (PciIo);
+}
+STATIC +VOID +XenonConfigureInterrupts (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINT32 Var;
- // Clear interrupt status
- Var = 0xFFFFFFFF;
UINT_MAX? ~0?
Ok
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, 4, &Var);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, 4, &Var);
- // Enable only interrupts served by the SD controller
- Var = 0xFFFFFEBF;
Some #define and a ~?
Ok
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS_EN, FALSE, 4, &Var);
- // Mask all sdhci interrupt sources
- Var = 0xFFFFFEFF;
Some #define and a ~?
Ok
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_SIG_EN, FALSE, 4, &Var);
+}
+// Enable Parallel Transfer Mode +STATIC +VOID +XenonSetParallelTransfer (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, TRUE, 4, &Var);
- if (Enable) {
- Var |= (0x1 << Slot);
- } else {
- Var &= ~(0x1 << Slot);
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, FALSE, 4, &Var);
+}
+STATIC +VOID +XenonSetTuning (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- // Set the Re-Tuning Request functionality
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, TRUE, 4, &Var);
- if (Enable) {
- Var |= RETUNING_COMPATIBLE;
- } else {
- Var &= ~RETUNING_COMPATIBLE;
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, FALSE, 4, &Var);
- // Set the Re-tuning Event Signal Enable
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, TRUE, 4, &Var);
- if (Enable) {
- Var |= SDHCI_RETUNE_EVT_INTSIG;
- } else {
- Var &= ~SDHCI_RETUNE_EVT_INTSIG;
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, FALSE, 4, &Var);
+}
+VOID +XenonReset (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN UINT8 Mask
- )
+{
- UINT32 Timeout = 1000;
Retries?
Rigth, it's better.
- UINT8 SwReset;
- SwReset = Mask;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,FALSE,sizeof (SwReset),&SwReset);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,TRUE,sizeof (SwReset),&SwReset);- while (SwReset & Mask) {
- if (Timeout == 0) {
DEBUG((DEBUG_ERROR, "SD/MMC: Reset never completed\n"));return;- }
- Timeout--;
- gBS-> Stall (100);
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,TRUE,sizeof (SwReset),&SwReset);- }
+}
+STATIC +VOID +XenonTransferPio (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN OUT VOID *Buffer,
- IN UINT16 BlockSize,
- IN BOOLEAN Read
- )
+{
- UINTN I;
- UINT8 *Offs;
- //
- // SD stack's intrinsic functions cannot perform properly reading/writing from
- // buffer register, that is why MmioRead/MmioWrite are used. It is temporary
- // solution.
- //
- for (I = 0; I < BlockSize; I += 4) {
- Offs = Buffer + I;
- if (Read) {
*(UINT32 *)Offs = MmioRead32 (0xf06e0020); // SDHCI_BUFFER#define.
Ok.
- } else {
MmioWrite32 (0xf06e0020, *(UINT32 *)Offs); // SDHCI_BUFFER#define.
Also - this driver is still doing PCI semantics, but now it's doing direct access to a hard-coded memory address. That's not very pretty. Can we either obtain this information in a more dynamic fasion, or cut away every last mention of PCI?
Comment above for loop specify why we use such approach. Will revisit and try to debug one more time, but if it doesn't help we will use consistent approach.
- }
- }
+}
+EFI_STATUS +XenonTransferData (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN OUT VOID *Buffer,
- IN UINT32 DataLen,
- IN UINT16 BlockSize,
- IN UINT16 Blocks,
- IN BOOLEAN Read
- )
+{
- UINT32 IntStatus, PresentState, Rdy, Mask, Timeout, Block = 0;
- if (Buffer == NULL) {
- return EFI_DEVICE_ERROR;
- }
- Timeout = 100000; // 100000 * 10 us = 1 second
This line inserted to clarify below comment does not apply to above.
Agree.
- Rdy = 0x10 | 0x20; // SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL
- Mask = 0x800 | 0x400; // SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE
#defines instead of comments?
Ok.
- do {
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- if (IntStatus & BIT15) { // SDHCI_INT_ERROR
#define instead of comment?
DEBUG((DEBUG_INFO, "SD/MMC: Error detected in status %0x\n", IntStatus));return EFI_DEVICE_ERROR;- }
- if (IntStatus & Rdy) {
SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);if (!(PresentState & Mask)) {continue;}SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (Rdy),&Rdy);XenonTransferPio (Private, Slot, Buffer, BlockSize, Read);Buffer += BlockSize;if (++Block >= Blocks) {break;}- }
- if (Timeout-- > 0) {
gBS->Stall (10);- } else {
DEBUG((DEBUG_INFO, "SD/MMC: Transfer data timeout\n"));return EFI_TIMEOUT;- }
- } while (!(IntStatus & BIT1)); // SDHCI_INT_DATA_END
#define instead of comment?
(Oh, and please add blank line before return.
Ok.
- return EFI_SUCCESS;
+}
+EFI_STATUS +XenonInit (
- IN SD_MMC_HC_PRIVATE_DATA *Private
- )
+{
- EFI_PCI_IO_PROTOCOL *PciIo = Private->PciIo;
- XenonSetMpp ();
- XenonReadVersion (PciIo, &Private->ControllerVersion);
- XenonSetFifo (PciIo);
- XenonSetAcg (PciIo, FALSE);
The blank lines between every function call actually makes this function a bit difficult to read. Can calls be grouped as logically connected? Or more comments added?
I think adding more comments will make it looks better.
- // Hyperion has only one port
- XenonSetSlot (PciIo, XENON_MMC_SLOT_ID_HYPERION, TRUE);
- XenonSetPower (PciIo, MMC_VDD_165_195, eMMC_VCCQ_1_8V, XENON_MMC_MODE_SD_SDIO);
- // Set MAX_CLOCK for configuring PHY
- XenonSetClk (PciIo, Private, XENON_MMC_MAX_CLK);
- XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50);
- XenonConfigureInterrupts (PciIo);
- // Enable parallel transfer
- XenonSetParallelTransfer (PciIo, XENON_MMC_SLOT_ID_HYPERION, TRUE);
- XenonSetTuning (PciIo, XENON_MMC_SLOT_ID_HYPERION, FALSE);
- XenonSetAcg (PciIo, TRUE);
- XenonSetClk (PciIo, Private, XENON_MMC_BASE_CLK);
- XenonPhyInit (PciIo);
- return EFI_SUCCESS;
+} diff --git a/Drivers/SdMmc/XenonSdhci.h b/Drivers/SdMmc/XenonSdhci.h new file mode 100644 index 0000000..a7b30c3 --- /dev/null +++ b/Drivers/SdMmc/XenonSdhci.h @@ -0,0 +1,278 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd.
+Marvell BSD License Option
+If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met:
+* Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
+* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#include "../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h"
Use local copy.
Ok.
+#include <Library/IoLib.h>
+#define SD_BAR_INDEX 0
+/* Register Offset of SD Host Controller SOCP self-defined register */
+#define SDHC_IPID 0x0100 +#define SDHC_SYS_CFG_INFO 0x0104 +#define SLOT_TYPE_SDIO_SHIFT 24 +#define SLOT_TYPE_EMMC_MASK 0xff +#define SLOT_TYPE_EMMC_SHIFT 16 +#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xff +#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8
+#define SDHC_SYS_OP_CTRL 0x0108 +#define AUTO_CLKGATE_DISABLE_MASK (0x1<<20) +#define SDCLK_IDLEOFF_ENABLE_SHIFT 8 +#define SLOT_ENABLE_SHIFT 0
+#define SDHC_SYS_EXT_OP_CTRL 0x010c +#define SDHC_TEST_OUT 0x0110 +#define SDHC_TESTOUT_MUXSEL 0x0114
+#define SDHC_SLOT_EXT_INT_STATUS 0x0120 +#define SDHC_SLOT_EXT_ERR_STATUS 0x0122 +#define SDHC_SLOT_EXT_INT_STATUS_EN 0x0124 +#define SDHC_SLOT_EXT_ERR_STATUS_EN 0x0126
+#define SDHC_SLOT_OP_STATUS_CTRL 0x0128 +#define TUNING_PROG_FIXED_DELAY_MASK 0x7ff +#define FORCE_SEL_INVERSE_CLK_SHIFT 11
+#define SDHC_SLOT_FIFO_CTRL 0x012c
+#define SDHC_SLOT_eMMC_CTRL 0x0130 +#define ENABLE_DATA_STROBE_SHIFT 24 +#define SET_EMMC_RSTN_SHIFT 16 +#define eMMC_VCCQ_MASK 0x3 +#define eMMC_VCCQ_1_8V 0x1 +#define eMMC_VCCQ_1_2V 0x2 +#define eMMC_VCCQ_3_3V 0x3
+#define SDHC_SLOT_OUTPUT_DLY_CTRL 0x0134 +#define SDHC_SLOT_DCM_CTRL 0x0137
+#define SDHC_SLOT_DLL_CTRL 0x0138 +#define SELECT_DEF_DLL 0x1
+#define SDHC_SLOT_DLL_PHASE_SEL 0x013c +#define DLL_UPDATE_STROBE 7
+#define SDHC_SLOT_STROBE_DLY_CTRL 0x0140 +#define STROBE_DELAY_FIXED_MASK 0xffff
+#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144 +#define RETUNING_COMPATIBLE 0x1
+#define SDHC_SLOT_AUTO_RETUNING_CTRL 0x0148 +#define ENABLE_AUTO_RETUNING 0x1
+#define SDHC_SLOT_EXT_PRESENT_STATE 0x014c +#define SDHC_SLOT_DLL_CUR_DLY_VAL 0x0150 +#define SDHC_SLOT_TUNING_CUR_DLY_VAL 0x0154 +#define SDHC_SLOT_STROBE_CUR_DLY_VAL 0x0158 +#define SDHC_SLOT_SUB_CMD_STRL 0x015c
+#define SDHC_SLOT_CQ_TASK_INFO 0x0160
+#define SDHC_SLOT_TUNING_DEBUG_INFO 0x01f0 +#define SDHC_SLOT_DATAIN_DEBUG_INFO 0x01f4
+#define XENON_MMC_MAX_CLK 400000000
HZ? (A comment would suffice.)
Ok.
+#define XENON_MMC_CLK_RATIO 2046 +#define XENON_MMC_BASE_CLK XENON_MMC_MAX_CLK / XENON_MMC_CLK_RATIO
+#define XENON_MMC_CMD_MAX_TIMEOUT 3200 +#define XENON_MMC_CMD_DEFAULT_TIMEOUT 100
+/* Tuning Parameter */ +#define TMR_RETUN_NO_PRESENT 0xf +#define XENON_MAX_TUN_COUNT 0xb
+#define EMMC_PHY_REG_BASE 0x170 +#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE +#define OUTPUT_QSN_PHASE_SELECT (1 << 17) +#define SAMPL_INV_QSP_PHASE_SELECT (1 << 18) +#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 +#define PHY_INITIALIZAION (1 << 31) +#define WAIT_CYCLE_BEFORE_USING_MASK 0xf +#define WAIT_CYCLE_BEFORE_USING_SHIFT 12 +#define FC_SYNC_EN_DURATION_MASK 0xf +#define FC_SYNC_EN_DURATION_SHIFT 8 +#define FC_SYNC_RST_EN_DURATION_MASK 0xf +#define FC_SYNC_RST_EN_DURATION_SHIFT 4 +#define FC_SYNC_RST_DURATION_MASK 0xf +#define FC_SYNC_RST_DURATION_SHIFT 0
+#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4) +#define DQ_ASYNC_MODE (1 << 4) +#define DQ_DDR_MODE_SHIFT 8 +#define DQ_DDR_MODE_MASK 0xff +#define CMD_DDR_MODE (1 << 16)
+#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8) +#define REC_EN_SHIFT 24 +#define REC_EN_MASK 0xf +#define FC_DQ_RECEN (1 << 24) +#define FC_CMD_RECEN (1 << 25) +#define FC_QSP_RECEN (1 << 26) +#define FC_QSN_RECEN (1 << 27) +#define OEN_QSN (1 << 28) +#define AUTO_RECEN_CTRL (1 << 30)
+#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc) +#define EMMC_PHY_PAD_CONTROL2 (EMMC_PHY_REG_BASE + 0x10) +#define EMMC_PHY_DLL_CONTROL (EMMC_PHY_REG_BASE + 0x14) +#define DLL_DELAY_TEST_LOWER_SHIFT 8 +#define DLL_DELAY_TEST_LOWER_MASK 0xff +#define DLL_BYPASS_EN 0x1
+#define EMMC_LOGIC_TIMING_ADJUST (EMMC_PHY_REG_BASE + 0x18) +#define EMMC_LOGIC_TIMING_ADJUST_LOW (EMMC_PHY_REG_BASE + 0x1c)
+#define MVEBU_IP_CONFIG_REG (0xf0000000 + 0x6F4100)
Again, slightly uncomfortable with this hard-coded address. (But depending on what you do about my comment on where this is actually used, could possibly be dropped.)
Yes, It will be removed from there.
+#define LOGIC_TIMING_VALUE 0x5a54 /* Recommend by HW team */
+/* Hyperion only have one slot 0 */
What is Hyperion? Internal name of a specific devboard?
It's old name and should be removed
On Thu, Nov 17, 2016 at 03:57:46PM +0100, Jan Dąbroś wrote:
Hi Leif,
Thanks a lot for your remarks. Please find comments inline.
Best Regards, Jan
- //
- // Get SD/MMC Pci Host Controller Slot info
- //
- Status = SdMmcHcGetSlotInfo (PciIo, &FirstBar, &SlotNum);
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- Support64BitDma = TRUE;
- for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) {
- for (Slot = 0; Slot < (XENON_MMC_SLOT_ID_HYPERION + 1); Slot++) {
Since all this line is currently doing is hardcoding that this loop should only be executed once, could an intermediate define of ..._NUM_SLOTS be introduced, if we're expecting this driver to be reusable for anything else? (And if we don't, can we drop the loop bit?)
Indeed, current solution isn't reusable. We should drop the loop.
- //
- // Override capabilities structure - only 4 Bit width bus is supported
- // by HW and also force using SDR25 mode
- //
- Private->Capability[Slot].Sdr104 = 0;
- Private->Capability[Slot].Ddr50 = 0;
- Private->Capability[Slot].Sdr50 = 0;
- Private->Capability[Slot].BusWidth8 = 0;
And if you are importing the whole driver, I'm guessing you can get rid of this type of thing completely?
We want to have as small diff as possible in comparison to MdeModulePkg stack. If we wouldn't do this here, few other steps in init sequence will have to be changed. Overriding capability fields in one place (which allows to clearly see what are differences between HW capabilities and software support) is cleaner way in my opinion. What do you think?
Well, you have a much better overview of the implications than what I'm able to get at a quick scan. My main thing is that if we are hard-coding things we don't have in order to be able to keep code we're not using, we're better off putting our trust in diff.
If we're only preseeding information we the original would have received dynamically, I have no issue with that.
- if (Private->Capability[Slot].BaseClkFreq == 0) {
Private->Capability[Slot].BaseClkFreq = 0xff;- }
- DumpCapabilityReg (Slot, &Private->Capability[Slot]);
- Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); if (EFI_ERROR (Status)) { continue;
@@ -624,28 +629,8 @@ SdMmcPciHcDriverBindingStart ( continue; }
- //
- // Reset the specified slot of the SD/MMC Pci Host Controller
- //
- Status = SdMmcHcReset (PciIo, Slot);
- if (EFI_ERROR (Status)) {
continue;- }
- //
- // Check whether there is a SD/MMC card attached
- //
- Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent);
- if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) {
continue;- } else if (!MediaPresent) {
DEBUG ((DEBUG_ERROR, "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n", Slot));continue;- }
- Status = SdMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]);
- if (EFI_ERROR (Status)) {
continue;- }
// Perform Xenon-specific init sequence
XenonInit (Private);
Private->Slot[Slot].MediaPresent = TRUE; Private->Slot[Slot].Initialized = TRUE;
@@ -889,6 +874,220 @@ SdMmcPciHcDriverBindingStop ( }
/**
- Check if card is ready for next data transfer by reading its status.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot The slot number of the device to send the command to.
- @param[in] Rca The relative device address of addressed device.
- @param[in] Timeout The timeout in miliseconds.
- @retval EFI_SUCCESS Card is ready for next data transfer.
- @retval EFI_DEVICE_ERROR Card status is erroneous.
- @retval EFI_TIMEOUT Card is busy.
+**/ +STATIC +EFI_STATUS +SdMmcIsReady (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot,
- IN UINT16 Rca,
- IN UINTN Timeout
- )
+{
- EFI_STATUS Status;
- UINT32 DevStatus;
- do {
- Status = SdCardSendStatus (This, Slot, Rca, &DevStatus);
- if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Cannot read SD status\n"));return Status;- }
- // Check device status
- if ((DevStatus & (1 << 8)) && (DevStatus & (0xf << 9)) != (7 << 9)) {
Some macros here to show which flags are being checked, please?
Yes, whole function should be corrected in terms of magic numbers.
break;- } else if (DevStatus & ~0x0206BF7F) {
More macros, please.
DEBUG ((DEBUG_ERROR, "SD Status error\n"));return EFI_DEVICE_ERROR;- }
- gBS->Stall (1000);
And a comment with that delay please. (Why? Why this value?)
Ok.
- } while (Timeout--);
- if (Timeout <= 0) {
- DEBUG ((DEBUG_ERROR, "SD Status timeout\n"));
- return EFI_TIMEOUT;
- }
- if (DevStatus & (1 << 7)) {
Macro?
Ok
- DEBUG ((DEBUG_ERROR, "SD switch error\n"));
- return EFI_DEVICE_ERROR;
- }
- return EFI_SUCCESS;
+}
+STATIC +EFI_STATUS +CheckParameters (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN UINT8 Slot
- )
+{
- SD_MMC_HC_PRIVATE_DATA *Private;
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if ((This == NULL) || (Packet == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- }
- if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- }
- if (!Private->Slot[Slot].Enable) {
- return EFI_INVALID_PARAMETER;
- }
- if (!Private->Slot[Slot].MediaPresent) {
- return EFI_NO_MEDIA;
- }
- // Currently we don't support SDIO
- if (Packet->SdMmcCmdBlk->CommandIndex == SDIO_SEND_OP_COND) {
- return EFI_DEVICE_ERROR;
- }
- return EFI_SUCCESS;
+}
+/**
- Send command SD_STOP_TRANSMISSION to stop multiple block transfer.
- @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
- @param[in] Slot The slot number of the device to send the command to.
- @retval EFI_SUCCESS The request is executed successfully.
- @retval Others The request could not be executed successfully.
+**/ +STATIC +EFI_STATUS +SdMmcSendStopTransmission (
- IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,
- IN UINT8 Slot
- )
+{
- EFI_STATUS Status;
- EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
- EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
- EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
- ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
- ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
- ZeroMem (&Packet, sizeof (Packet));
- Packet.SdMmcCmdBlk = &SdMmcCmdBlk;
- Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
- Packet.Timeout = 2500 * 1000; // SD generic timeout
Sure, but can we have some defines for it please?
Ok, will replace comment with define.
- SdMmcCmdBlk.CommandIndex = SD_STOP_TRANSMISSION;
- SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
- SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
- SdMmcCmdBlk.CommandArgument = 0;
- Status = This->PassThru (This, Slot, &Packet, NULL);
- return Status;
+}
+STATIC +EFI_STATUS +WaitForInhibit (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
- IN UINT8 Slot,
- IN BOOLEAN DataTransfer
- )
+{
- UINT32 Mask, PresentState, Time = 0;
- UINT32 CmdTimeout = XENON_MMC_CMD_DEFAULT_TIMEOUT;
- if (Packet->SdMmcCmdBlk != NULL) {
- Mask = BIT0; // SDHCI_CMD_INHIBIT
- }
- if (DataTransfer != FALSE) {
- Mask = BIT1; // SDHCI_DATA_INHIBIT
- }
- //
- // We shouldn't wait for data inhibit for stop commands, even
- // though they might use busy signaling
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_STOP_TRANSMISSION)
- Mask &= ~BIT1;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);- while (PresentState & Mask) {
- if (Time >= CmdTimeout) {
if (2 * CmdTimeout <= XENON_MMC_CMD_MAX_TIMEOUT) {CmdTimeout += CmdTimeout;} else {if (Packet->SdMmcCmdBlk != NULL) {XenonReset (Private, Slot, 0x02); // CMD resetCould replace the comment with a #define?
Ok.
}if (DataTransfer) {XenonReset (Private, Slot, 0x04); // DATA resetCould replace the comment with a #define?
Ok.
}DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Timeout...\n"));return EFI_TIMEOUT;}- }
- Time++;
- gBS->Stall (1000);
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);- }
- return EFI_SUCCESS;
+}
+// Variable to store current card's Rca - used in polling card status +STATIC UINT16 CurrRca = 0;
I think this should have an m-prefix.
Agree.
+/** Sends SD command to an SD card that is attached to the SD controller.
The PassThru() function sends the SD command specified by Packet to the SD card @@ -934,86 +1133,351 @@ SdMmcPassThruPassThru ( IN EFI_EVENT Event OPTIONAL ) {
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- SD_MMC_HC_TRB *Trb;
- EFI_TPL OldTpl;
- EFI_STATUS Status;
- SD_MMC_HC_PRIVATE_DATA *Private;
- INTN Ret;
- UINTN *Data, DataLen, Index;
- UINT32 Argument, Response[4], Retry, Stat, Mask;
Please not Stat and Status in the same function.
Ok, will change first one.
- UINT16 BlockSize, BlkCount;
- UINT16 Cmd, IntStatus, TimeoutCtrl, Mode, BlkSizeReg;
- BOOLEAN MultiFlag = FALSE, SetRcaFlag = FALSE, Read = FALSE;
- BOOLEAN DataTransfer;
- Data = NULL;
- DataLen = 0;
- Retry = 1000;
Could we have a define for that?
Ok.
- Stat = 0;
- Ret = 0;
- BlockSize = 0x200;
SIZE_512B? (We don't have a global define for that, but it would make it more readable.)
Ok.
- BlkCount = 0;
- Status = CheckParameters (This, Packet, Slot);
- if (EFI_ERROR(Status)) {
- return Status;
- }
- if ((This == NULL) || (Packet == NULL)) {
- return EFI_INVALID_PARAMETER;
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- //
- // Mark if this is multiblock data transfer since some special
- // acctions must be taken in such circumstances, i.e. it's necessary
- // to send SD_STOP_TRANSMISSION command.
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_WRITE_MULTIPLE_BLOCK ||
Packet->SdMmcCmdBlk->CommandIndex == SD_READ_MULTIPLE_BLOCK) {- MultiFlag = TRUE; }
- if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
- return EFI_INVALID_PARAMETER;
- //
- // Mark if this is command to set new relative card address (RCA),
- // since it's necessary to have updated copy of current RCA in this
- // layer - used in checking card status.
- //
- if (Packet->SdMmcCmdBlk->CommandIndex == SD_SET_RELATIVE_ADDR) {
- SetRcaFlag = TRUE; }
- if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- // Prepare data transfer's flags
- if (((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) ||
((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL))) {- DataTransfer = FALSE; }
- if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
- return EFI_INVALID_PARAMETER;
- if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
- DataLen = Packet->InTransferLength;
- Data = Packet->InDataBuffer;
- Read = TRUE;
- DataTransfer = TRUE; }
- Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
- if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
- DataLen = Packet->OutTransferLength;
- Data = Packet->OutDataBuffer;
- DataTransfer = TRUE;
- }
- if (!Private->Slot[Slot].Enable) {
- return EFI_INVALID_PARAMETER;
- // Clear ERROR_IRQ status
- IntStatus = 0xFFFF;
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_ERR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Cannot clear ERROR_IRQ status\n"));
- return Status; }
- if (!Private->Slot[Slot].MediaPresent) {
- return EFI_NO_MEDIA;
- // Clear IRQ status
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Cannot clear IRQ status\n"));
- return Status; }
- if (!Private->Slot[Slot].Initialized) {
- return EFI_DEVICE_ERROR;
- WaitForInhibit (Private, Packet, Slot, DataTransfer);
- Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
- if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
- Cmd |= BIT5;
Is it possible to give this bit a more descriprive name?
Please see below comment.
}
- Trb = SdMmcCreateTrb (Private, Slot, Packet, Event);
- if (Trb == NULL) {
- return EFI_OUT_OF_RESOURCES;
- if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
- switch (Packet->SdMmcCmdBlk->ResponseType) {
case SdMmcResponseTypeR1:case SdMmcResponseTypeR5:case SdMmcResponseTypeR6:case SdMmcResponseTypeR7:Cmd |= (BIT1 | BIT3 | BIT4);Is it possible to give these bits more descriprive names? If not, please sort them in descending order. (Same applies to rest of cases.)
This switch-case statement is taken from MdeModulePkg driver and ResponsesTypes (with according BITs in CMD) are well documented in SD specification. But if you think it isn't enough, I will add #defines.
It's just not of much use if you're not sitting with the spec in your lap. I'd be head cheerleader for getting those same changes into the core driver.
break;case SdMmcResponseTypeR2:Cmd |= (BIT0 | BIT3);break;case SdMmcResponseTypeR3:case SdMmcResponseTypeR4:Cmd |= BIT1;break;case SdMmcResponseTypeR1b:case SdMmcResponseTypeR5b:Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);break;default:ASSERT (FALSE);Should this not return also? In a release build, this would just keep executing in an unknown state.
Yes, agree.
break;- } }
- //
- // Immediately return for async I/O.
- //
- if (Event != NULL) {
- return EFI_SUCCESS;
- if ((DataLen % BlockSize) != 0) {
- if (DataLen < BlockSize) {
BlockSize = (UINT16)DataLen;- } }
- BlkCount = (UINT16) (DataLen / BlockSize);
- if (DataTransfer) {
- // Set default timeout value
- TimeoutCtrl = 0xE;
#define?
Ok.
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_TIMEOUT_CTRL,FALSE,sizeof (TimeoutCtrl),&TimeoutCtrl);- Mode = 0x02; // SDHCI_TRNS_BLK_CNT_EN
- if (BlkCount > 1) {
Mode |= 0x20; // SDHCI_TRNS_MULTI- }
- if (Read) {
Mode |= 0x10; // SDHCI_TRNS_READ#defines instead of comments?
Ok.
- }
- //
- // Wait async I/O list is empty before execute sync I/O operation.
- //
- while (TRUE) {
- OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
- if (IsListEmpty (&Private->Queue)) {
gBS->RestoreTPL (OldTpl);
- // Fill BlockSize register
- BlkSizeReg = (0x7 << 12) | (BlockSize & 0xFFF);
#defines?
(SIZE_4KB - 1)?
Ok.
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_BLK_SIZE,FALSE,sizeof (BlkSizeReg),&BlkSizeReg);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_BLK_COUNT,FALSE,sizeof (BlkCount),&BlkCount);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_TRANS_MOD,FALSE,sizeof (Mode),&Mode);- }
- Argument = Packet->SdMmcCmdBlk->CommandArgument;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_ARG1,FALSE,sizeof (Argument),&Argument);- // Execute cmd
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_COMMAND,FALSE,sizeof (Cmd),&Cmd);- Mask = BIT0; // SDHCI_INT_RESPONSE
#define instead of comment?
Ok. Will apply to every comment of this type.
- if (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b ||
Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b) {- Mask |= BIT1;
#define instead of comment?
- }
- do {
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER;- }
- if (IntStatus & BIT15) { // SDHCI_INT_STATUS
#define instead of comment?
DEBUG((DEBUG_INFO, "MvSdMmcPassThru: SDHCI_INT_ERROR stat:%x\n",IntStatus)); break;
gBS->RestoreTPL (OldTpl);
}
Status = SdMmcWaitTrbEnv (Private, Trb);
if (EFI_ERROR (Status)) {
goto Done;
- // Stall for 100 microseconds
Yeah, that's what the line below says on its own. Why? Why this period?
Ok, we will add more precise description to every delay.
- gBS->Stall (100);
- if (--Retry == 0) {
break;- }
- } while ((IntStatus & Mask) != Mask);
- if (Retry == 0) {
- DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Rx timeout\n"));
- return EFI_TIMEOUT; }
- Status = SdMmcExecTrb (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- if ((IntStatus & (BIT15 | Mask)) == Mask) {
#define?
Ok.
- if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
for (Index = 0; Index < 4; Index++) {SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_RESPONSE + Index * 4,TRUE,sizeof (UINT32),sizeof (Response[Index])? (Or sizeof (*Response)?)
Yes, first option will suit here.
&Response[Index]);}CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));//// Update RCA of current card in order to use it later// for polling card status//if (SetRcaFlag)Always {} with if.
Ok.
CurrRca = Packet->SdMmcStatusBlk->Resp0 >> 16;#define?
As with my comment to switch-case statement. Such shift for RCA is commonly used in MdeModulePkg, but for clarity we will make it #define.
Thanks.
- }
- IntStatus = Mask;
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (IntStatus),&IntStatus);- } else {
- Ret = -1; }
- Status = SdMmcWaitTrbResult (Private, Trb);
- if (EFI_ERROR (Status)) {
- goto Done;
- if (!Ret && DataTransfer) {
- Status = XenonTransferData (Private, Slot, Data, DataLen, BlockSize, BlkCount, Read); }
-Done:
- if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
- FreePages (Trb->AdmaDesc, Trb->AdmaPages);
- // SDHCI_QUIRK_WAIT_SEND_CMD - 1 milisecond delay
The code already says it's a 1 milisecond delay. Why is there a delay, and why is it of this period?
Will add proper comment.
- gBS->Stall (1000);
- // Save current IRQ status
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- // Clear IRQ
- Stat = 0xFFFFFFFFULL;
Stat (hopefully to be renamed) is UINT32, so why ULL? But would also look much better with a #define.
ULL sufix isn't necessary here. Ok.
- Status = SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (Stat),&Stat);- //
- // There are two quirks for DataTransfer commands:
- // 1. For multipleblock write/read it's necessary to issue
- // SD_STOP_TRANSMISSION command
- // 2. For every write data comand, it's necessary to poll for
- // card status before issuing next data transfer
- //
- if (!Ret && DataTransfer) {
- if (MultiFlag) {
SdMmcSendStopTransmission(This, Slot);- }
- if (!Read) {
return SdMmcIsReady (This, Slot, CurrRca, 1000);What is 1000?
It's max timeout value for which we will poll device status. Will add proper define to make it more clear.
- }
- return EFI_SUCCESS; }
- if (Trb != NULL) {
- FreePool (Trb);
- // Check previously saved IRQ status for non-data commands
- if (IntStatus & BIT15) {
- if (Packet->SdMmcCmdBlk != NULL) {
XenonReset (Private, Slot, 0x02); // CMD#define instead of comment.
Ok, will apply for whole file.
- }
- if (DataTransfer) {
XenonReset (Private, Slot, 0x04); // DATA#define instead of comment.
- }
- if (IntStatus & (0x10000 | 0x100000)) { // SDHCI_INT_TIMEOUT
#defines.
DEBUG((DEBUG_ERROR, "MvSdMmcPassThru: Timeout!\n"));return EFI_TIMEOUT;} else {
return EFI_DEVICE_ERROR;}
} else {
return EFI_SUCCESS; }
return Status;
diff --git a/Drivers/SdMmc/MvSdMmcPciHcDxe.inf b/Drivers/SdMmc/MvSdMmcPciHcDxe.inf new file mode 100644 index 0000000..a4f66e9 --- /dev/null +++ b/Drivers/SdMmc/MvSdMmcPciHcDxe.inf @@ -0,0 +1,75 @@ +#/******************************************************************************* +#Copyright (C) 2016 Marvell International Ltd. +# +#Marvell BSD License Option +# +#If you received this File from Marvell, you may opt to use, redistribute and/or +#modify this File under the following licensing terms. +#Redistribution and use in source and binary forms, with or without modification, +#are permitted provided that the following conditions are met: +# +#* Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +#* Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +#* Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#*******************************************************************************/
+[Defines]
- INF_VERSION = 0x00010005
0019
Ok.
- BASE_NAME = MvSdMmcPciHcDxe
- MODULE_UNI_FILE = ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.uni
Refer to local copies.
Ok.
- FILE_GUID = 5b5b83b8-52b8-4d02-b92b-c84a4dfb539d
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeSdMmcPciHcDxe
+[Sources]
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ComponentName.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
- ../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
Refer to local copies.
Ok.
- MvSdMmcPciHcDxe.c
- XenonSdhci.c
- XenonSdhci.h
+[Packages]
- MdePkg/MdePkg.dec
+[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- DevicePathLib
- MemoryAllocationLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- UefiLib
- UefiRuntimeServicesTableLib
+[Protocols]
- gEfiDevicePathProtocolGuid ## TO_START
- gEfiPciIoProtocolGuid ## TO_START
- gEfiSdMmcPassThruProtocolGuid ## BY_START
+[UserExtensions.TianoCore."ExtraFiles"]
- SdMmcPciHcDxeExtra.uni
diff --git a/Drivers/SdMmc/XenonSdhci.c b/Drivers/SdMmc/XenonSdhci.c new file mode 100755 index 0000000..6a20105 --- /dev/null +++ b/Drivers/SdMmc/XenonSdhci.c @@ -0,0 +1,661 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd.
+Marvell BSD License Option
+If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met:
+* Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
+* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#include "XenonSdhci.h"
+STATIC +VOID +XenonSetMpp (
- VOID
- )
+{
- UINT32 Reg;
- // Set eMMC/SD PHY output instead of MPPs
As pin control configuration, isn't this something that should be done in Armada70x0Lib or similar?
This code will be moved in next spin.
- Reg = MmioRead32 (MVEBU_IP_CONFIG_REG);
- Reg &= ~(1 << 0);
#define
Ok.
- MmioWrite32 (MVEBU_IP_CONFIG_REG, Reg);
+}
+STATIC +VOID +XenonReadVersion (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- OUT UINT32 *ControllerVersion
- )
+{
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_CTRL_VER, TRUE, 2, ControllerVersion);
What is 2?
All of these '1', '2', and '4' are registers' sizes (I wouldn't write it so many times :) ). Define will be used to improve readability.
Thanks, that'll be a big improvement.
+}
+STATIC +VOID +XenonSetFifo (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINTN Data = 0x315;
#define
Ok.
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, 4, &Data);
What is 4?
+}
+// Auto Clock Gating +STATIC +VOID +XenonSetAcg (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, 4, &Var);
What is 4?
- if (Enable) {
- Var &= ~AUTO_CLKGATE_DISABLE_MASK;
- } else {
- Var |= AUTO_CLKGATE_DISABLE_MASK;
- }
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, 4, &Var);
What is 4?
+}
+STATIC +VOID +XenonSetSlot (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, 4, &Var);
What is 4?
- if (Enable) {
- Var |= ((0x1 << Slot) << SLOT_ENABLE_SHIFT);
- } else {
- Var &= ~((0x1 << Slot) << SLOT_ENABLE_SHIFT);
- }
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, 4, &Var);
What is 4?
+}
+STATIC +VOID +XenonSetSdio (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINTN Voltage
- )
+{
- // Currently SDIO isn't supported
- return;
+}
+STATIC +VOID +XenonSetPower (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Vcc,
- IN UINT32 Vccq,
- IN UINT8 Mode
- )
+{
- UINT8 Pwr = 0;
- UINT32 Ctrl = 0;
- // Set VCC
- switch (Vcc) {
- case MMC_VDD_165_195:
- Pwr = SDHCI_POWER_180;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 0);OK, so we've just determined above that SDIO isn't currently supported. So why are we enabling/disabling it and not checking any status?
SDIO isn't currently supported and it's stub which may be improved (implemented correctly) in future. For now, code silently go through this. Do you think it should be removed for now?
I don't mind adding stubs to be expanded as a concept.
My issue is how, given there is no code in XenonSetSdio, I have no way to determine whether Voltage being 0 in this case and 1 in the others is a reasonable thing.
Proper function descriptions for both XenonSetSdio and XenonSetPower would tip the balance tn it being a net-positive in having it in.
- }
- break;
- case MMC_VDD_29_30:
- case MMC_VDD_30_31:
- Pwr = SDHCI_POWER_300;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 1);- }
- break;
- case MMC_VDD_32_33:
- case MMC_VDD_33_34:
- Pwr = SDHCI_POWER_330;
- if (Mode == XENON_MMC_MODE_SD_SDIO) {
XenonSetSdio (PciIo, 1);- }
- break;
- default:
- DEBUG((DEBUG_ERROR, "SD/MMC: Does not support power mode(0x%X)\n", Vcc));
- break;
- }
- if (Pwr == 0) {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_POWER_CTRL, FALSE, 1, &Pwr);
What is 1?
- return;
- }
- Pwr |= SDHCI_POWER_ON;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_POWER_CTRL, FALSE, 1, &Pwr);
What is 1?
- // Set VCCQ
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, TRUE, 4, &Ctrl);
What is 4?
- Ctrl |= Vccq;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, FALSE, 4, &Ctrl);
What is 4?
+}
+UINTN +XenonSetClk (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT32 Clock
- )
+{
- UINT32 Div;
- UINT32 Clk;
- UINT32 Timeout;
- UINT16 Value = 0;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Value);
What is 2?
- if (Clock == 0)
Always {} with if.
Ok.
- return 0;
- if (Private->ControllerVersion >= SDHCI_SPEC_300) {
- // Version 3.00 Divisors must be a multiple of 2
- if (XENON_MMC_MAX_CLK <= Clock) {
Div = 1;- } else {
for (Div = 2; Div < SDHCI_MAX_DIV_SPEC_300; Div += 2) {if ((XENON_MMC_MAX_CLK / Div) <= Clock)break;}- }
- } else {
- // Version 2.00 Divisors must be a power of 2
- for (Div = 1; Div < SDHCI_MAX_DIV_SPEC_200; Div *= 2) {
if ((XENON_MMC_MAX_CLK / Div) <= Clock)break;- }
- }
- Div >>= 1;
- Clk = (Div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
- Clk |= ((Div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT;
- Clk |= SDHCI_CLOCK_INT_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Clk);
What is 2?
- // Wait max 20 ms
Why?
Will add more descriptive comment.
- Timeout = 200;
And how does 200 delays of 1us end up being related to 20ms?
All of these mismatch between comment and delay's value are simply that text doesn't follow with changes in code. Will review whole file in terms of this, thanks.
Thanks, I suspected asmuch but feared it could be something like "and we know the Mmio op takes at least 8").
- do {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &Clk);
What is 2?
- if (Timeout == 0) {
DEBUG((DEBUG_ERROR, "SD/MMC: Internal Clock never stabilised\n"));return -1;- }
- Timeout--;
- gBS->Stall (1);
- } while (!(Clk & SDHCI_CLOCK_INT_STABLE));
- Clk |= SDHCI_CLOCK_CARD_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &Clk);
What is 2?
- return 0;
+}
+VOID +XenonPhyInit (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINT32 Var, Wait, Time;
- UINT32 Clock = XENON_MMC_MAX_CLK;
- UINT16 ClkCtrl;
- // Need to disable the clock to set EMMC_PHY_TIMING_ADJUST register
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- // Enable QSP PHASE SELECT
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- Var |= SAMPL_INV_QSP_PHASE_SELECT;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
What is 4?
- // Enable internal clock
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl |= SDHCI_CLOCK_INT_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- //
- // Poll for host MMC PHY clock init to be stable
Excellent - thanks! This is exactly the kind of comment I'm looking for in my previous comments.
- // Wait up to 10ms
- //
- Time = 100;
But how does 100 x 1us end up relating to 10ms?
- while (Time--) {
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- if (Var & SDHCI_CLOCK_INT_STABLE) {
break;- }
- gBS->Stall (1);
- }
- if (Time <= 0) {
- DEBUG((DEBUG_ERROR, "SD/MMC: Failed to enable MMC internal clock in Time\n"));
- return;
- }
- // Enable bus clock
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, 2, &ClkCtrl);
What is 2?
- ClkCtrl |= SDHCI_CLOCK_CARD_EN;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, 2, &ClkCtrl);
What is 2?
- // Delay 200us to Wait for the completion of bus clock
- gBS->Stall (200);
- // Init PHY
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
What is 4?
- Var |= PHY_INITIALIZAION;
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
What is 4? (OK, I'll stop now, but please provide some #define conveying what the actual significance it.)
- // Add duration of FC_SYNC_RST
- Wait = ((Var >> FC_SYNC_RST_DURATION_SHIFT) & FC_SYNC_RST_DURATION_MASK);
- // Add interval between FC_SYNC_EN and FC_SYNC_RST
- Wait += ((Var >> FC_SYNC_RST_EN_DURATION_SHIFT) & FC_SYNC_RST_EN_DURATION_MASK);
- // Add duration of asserting FC_SYNC_EN
- Wait += ((Var >> FC_SYNC_EN_DURATION_SHIFT) & FC_SYNC_EN_DURATION_MASK);
- // Add duration of Waiting for PHY
- Wait += ((Var >> WAIT_CYCLE_BEFORE_USING_SHIFT) & WAIT_CYCLE_BEFORE_USING_MASK);
- // 4 addtional bus clock and 4 AXI bus clock are required left shift 20 bits
- Wait += 8;
- Wait <<= 20;
- // Use the possibly slowest bus frequency value
- if (Clock == 0) {
- Clock = 100000;
#define?
Ok.
- }
- // Get the Wait Time in unit of ms
- Wait = Wait / Clock;
- Wait++;
- // Poll for host eMMC PHY init to complete, wait up to 10ms
- Time = 100;
Still not getting the 1 x 100 == 10000.
As above.
- while (Time--) {
- Var = SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
- Var &= PHY_INITIALIZAION;
- if (!Var) {
break;- }
- // Wait for host eMMC PHY init to complete
- gBS->Stall (1);
- }
- if (Time <= 0) {
- DEBUG((DEBUG_ERROR, "SD/MMC: Failed to init MMC PHY in Time\n"));
- return;
- }
- return;
+}
+STATIC +VOID +XenonSetPhy (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- UINT8 Timing
- )
+{
- UINT32 Var = 0;
- // Setup pad, set bit[30], bit[28] and bits[26:24]
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, TRUE, 4, &Var);
- Var |= (AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | FC_CMD_RECEN | FC_DQ_RECEN);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, FALSE, 4, &Var);
- //
- // If Timing belongs to high speed, set bit[17] of
- // EMMC_PHY_TIMING_ADJUST register
- //
- if ((Timing == MMC_TIMING_MMC_HS400) ||
(Timing == MMC_TIMING_MMC_HS200) ||(Timing == MMC_TIMING_UHS_SDR50) ||(Timing == MMC_TIMING_UHS_SDR104) ||(Timing == MMC_TIMING_UHS_DDR50) ||(Timing == MMC_TIMING_UHS_SDR25)) {- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, 4, &Var);
- // Set SLOW_MODE for PHY
- Var |= OUTPUT_QSN_PHASE_SELECT | (1 << 29);
#define?
Ok, as I wrote above, we will replace comments with #defines.
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, 4, &Var);
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, 4, &Var);
- Var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, 4, &Var);
- if (Timing == MMC_TIMING_MMC_HS400) {
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, 4, &Var);
- Var &= ~DQ_ASYNC_MODE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, 4, &Var);
- Var = LOGIC_TIMING_VALUE;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_LOGIC_TIMING_ADJUST, FALSE, 4, &Var);
- }
- XenonPhyInit (PciIo);
+}
+STATIC +VOID +XenonConfigureInterrupts (
- IN EFI_PCI_IO_PROTOCOL *PciIo
- )
+{
- UINT32 Var;
- // Clear interrupt status
- Var = 0xFFFFFFFF;
UINT_MAX? ~0?
Ok
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, 4, &Var);
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, 4, &Var);
- // Enable only interrupts served by the SD controller
- Var = 0xFFFFFEBF;
Some #define and a ~?
Ok
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS_EN, FALSE, 4, &Var);
- // Mask all sdhci interrupt sources
- Var = 0xFFFFFEFF;
Some #define and a ~?
Ok
- SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_SIG_EN, FALSE, 4, &Var);
+}
+// Enable Parallel Transfer Mode +STATIC +VOID +XenonSetParallelTransfer (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, TRUE, 4, &Var);
- if (Enable) {
- Var |= (0x1 << Slot);
- } else {
- Var &= ~(0x1 << Slot);
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, FALSE, 4, &Var);
+}
+STATIC +VOID +XenonSetTuning (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Slot,
- IN BOOLEAN Enable
- )
+{
- UINT32 Var;
- // Set the Re-Tuning Request functionality
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, TRUE, 4, &Var);
- if (Enable) {
- Var |= RETUNING_COMPATIBLE;
- } else {
- Var &= ~RETUNING_COMPATIBLE;
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, FALSE, 4, &Var);
- // Set the Re-tuning Event Signal Enable
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, TRUE, 4, &Var);
- if (Enable) {
- Var |= SDHCI_RETUNE_EVT_INTSIG;
- } else {
- Var &= ~SDHCI_RETUNE_EVT_INTSIG;
- }
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, FALSE, 4, &Var);
+}
+VOID +XenonReset (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN UINT8 Mask
- )
+{
- UINT32 Timeout = 1000;
Retries?
Rigth, it's better.
- UINT8 SwReset;
- SwReset = Mask;
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,FALSE,sizeof (SwReset),&SwReset);- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,TRUE,sizeof (SwReset),&SwReset);- while (SwReset & Mask) {
- if (Timeout == 0) {
DEBUG((DEBUG_ERROR, "SD/MMC: Reset never completed\n"));return;- }
- Timeout--;
- gBS-> Stall (100);
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_SW_RST,TRUE,sizeof (SwReset),&SwReset);- }
+}
+STATIC +VOID +XenonTransferPio (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN OUT VOID *Buffer,
- IN UINT16 BlockSize,
- IN BOOLEAN Read
- )
+{
- UINTN I;
- UINT8 *Offs;
- //
- // SD stack's intrinsic functions cannot perform properly reading/writing from
- // buffer register, that is why MmioRead/MmioWrite are used. It is temporary
- // solution.
- //
- for (I = 0; I < BlockSize; I += 4) {
- Offs = Buffer + I;
- if (Read) {
*(UINT32 *)Offs = MmioRead32 (0xf06e0020); // SDHCI_BUFFER#define.
Ok.
- } else {
MmioWrite32 (0xf06e0020, *(UINT32 *)Offs); // SDHCI_BUFFER#define.
Also - this driver is still doing PCI semantics, but now it's doing direct access to a hard-coded memory address. That's not very pretty. Can we either obtain this information in a more dynamic fasion, or cut away every last mention of PCI?
Comment above for loop specify why we use such approach. Will revisit and try to debug one more time, but if it doesn't help we will use consistent approach.
- }
- }
+}
+EFI_STATUS +XenonTransferData (
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN UINT8 Slot,
- IN OUT VOID *Buffer,
- IN UINT32 DataLen,
- IN UINT16 BlockSize,
- IN UINT16 Blocks,
- IN BOOLEAN Read
- )
+{
- UINT32 IntStatus, PresentState, Rdy, Mask, Timeout, Block = 0;
- if (Buffer == NULL) {
- return EFI_DEVICE_ERROR;
- }
- Timeout = 100000; // 100000 * 10 us = 1 second
This line inserted to clarify below comment does not apply to above.
Agree.
- Rdy = 0x10 | 0x20; // SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL
- Mask = 0x800 | 0x400; // SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE
#defines instead of comments?
Ok.
- do {
- SdMmcHcRwMmio (
Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (IntStatus),&IntStatus);- if (IntStatus & BIT15) { // SDHCI_INT_ERROR
#define instead of comment?
DEBUG((DEBUG_INFO, "SD/MMC: Error detected in status %0x\n", IntStatus));return EFI_DEVICE_ERROR;- }
- if (IntStatus & Rdy) {
SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (PresentState),&PresentState);if (!(PresentState & Mask)) {continue;}SdMmcHcRwMmio (Private->PciIo,Slot,SD_MMC_HC_NOR_INT_STS,FALSE,sizeof (Rdy),&Rdy);XenonTransferPio (Private, Slot, Buffer, BlockSize, Read);Buffer += BlockSize;if (++Block >= Blocks) {break;}- }
- if (Timeout-- > 0) {
gBS->Stall (10);- } else {
DEBUG((DEBUG_INFO, "SD/MMC: Transfer data timeout\n"));return EFI_TIMEOUT;- }
- } while (!(IntStatus & BIT1)); // SDHCI_INT_DATA_END
#define instead of comment?
(Oh, and please add blank line before return.
Ok.
- return EFI_SUCCESS;
+}
+EFI_STATUS +XenonInit (
- IN SD_MMC_HC_PRIVATE_DATA *Private
- )
+{
- EFI_PCI_IO_PROTOCOL *PciIo = Private->PciIo;
- XenonSetMpp ();
- XenonReadVersion (PciIo, &Private->ControllerVersion);
- XenonSetFifo (PciIo);
- XenonSetAcg (PciIo, FALSE);
The blank lines between every function call actually makes this function a bit difficult to read. Can calls be grouped as logically connected? Or more comments added?
I think adding more comments will make it looks better.
- // Hyperion has only one port
- XenonSetSlot (PciIo, XENON_MMC_SLOT_ID_HYPERION, TRUE);
- XenonSetPower (PciIo, MMC_VDD_165_195, eMMC_VCCQ_1_8V, XENON_MMC_MODE_SD_SDIO);
- // Set MAX_CLOCK for configuring PHY
- XenonSetClk (PciIo, Private, XENON_MMC_MAX_CLK);
- XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50);
- XenonConfigureInterrupts (PciIo);
- // Enable parallel transfer
- XenonSetParallelTransfer (PciIo, XENON_MMC_SLOT_ID_HYPERION, TRUE);
- XenonSetTuning (PciIo, XENON_MMC_SLOT_ID_HYPERION, FALSE);
- XenonSetAcg (PciIo, TRUE);
- XenonSetClk (PciIo, Private, XENON_MMC_BASE_CLK);
- XenonPhyInit (PciIo);
- return EFI_SUCCESS;
+} diff --git a/Drivers/SdMmc/XenonSdhci.h b/Drivers/SdMmc/XenonSdhci.h new file mode 100644 index 0000000..a7b30c3 --- /dev/null +++ b/Drivers/SdMmc/XenonSdhci.h @@ -0,0 +1,278 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd.
+Marvell BSD License Option
+If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met:
+* Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
+* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#include "../../../MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h"
Use local copy.
Ok.
+#include <Library/IoLib.h>
+#define SD_BAR_INDEX 0
+/* Register Offset of SD Host Controller SOCP self-defined register */
+#define SDHC_IPID 0x0100 +#define SDHC_SYS_CFG_INFO 0x0104 +#define SLOT_TYPE_SDIO_SHIFT 24 +#define SLOT_TYPE_EMMC_MASK 0xff +#define SLOT_TYPE_EMMC_SHIFT 16 +#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xff +#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8
+#define SDHC_SYS_OP_CTRL 0x0108 +#define AUTO_CLKGATE_DISABLE_MASK (0x1<<20) +#define SDCLK_IDLEOFF_ENABLE_SHIFT 8 +#define SLOT_ENABLE_SHIFT 0
+#define SDHC_SYS_EXT_OP_CTRL 0x010c +#define SDHC_TEST_OUT 0x0110 +#define SDHC_TESTOUT_MUXSEL 0x0114
+#define SDHC_SLOT_EXT_INT_STATUS 0x0120 +#define SDHC_SLOT_EXT_ERR_STATUS 0x0122 +#define SDHC_SLOT_EXT_INT_STATUS_EN 0x0124 +#define SDHC_SLOT_EXT_ERR_STATUS_EN 0x0126
+#define SDHC_SLOT_OP_STATUS_CTRL 0x0128 +#define TUNING_PROG_FIXED_DELAY_MASK 0x7ff +#define FORCE_SEL_INVERSE_CLK_SHIFT 11
+#define SDHC_SLOT_FIFO_CTRL 0x012c
+#define SDHC_SLOT_eMMC_CTRL 0x0130 +#define ENABLE_DATA_STROBE_SHIFT 24 +#define SET_EMMC_RSTN_SHIFT 16 +#define eMMC_VCCQ_MASK 0x3 +#define eMMC_VCCQ_1_8V 0x1 +#define eMMC_VCCQ_1_2V 0x2 +#define eMMC_VCCQ_3_3V 0x3
+#define SDHC_SLOT_OUTPUT_DLY_CTRL 0x0134 +#define SDHC_SLOT_DCM_CTRL 0x0137
+#define SDHC_SLOT_DLL_CTRL 0x0138 +#define SELECT_DEF_DLL 0x1
+#define SDHC_SLOT_DLL_PHASE_SEL 0x013c +#define DLL_UPDATE_STROBE 7
+#define SDHC_SLOT_STROBE_DLY_CTRL 0x0140 +#define STROBE_DELAY_FIXED_MASK 0xffff
+#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144 +#define RETUNING_COMPATIBLE 0x1
+#define SDHC_SLOT_AUTO_RETUNING_CTRL 0x0148 +#define ENABLE_AUTO_RETUNING 0x1
+#define SDHC_SLOT_EXT_PRESENT_STATE 0x014c +#define SDHC_SLOT_DLL_CUR_DLY_VAL 0x0150 +#define SDHC_SLOT_TUNING_CUR_DLY_VAL 0x0154 +#define SDHC_SLOT_STROBE_CUR_DLY_VAL 0x0158 +#define SDHC_SLOT_SUB_CMD_STRL 0x015c
+#define SDHC_SLOT_CQ_TASK_INFO 0x0160
+#define SDHC_SLOT_TUNING_DEBUG_INFO 0x01f0 +#define SDHC_SLOT_DATAIN_DEBUG_INFO 0x01f4
+#define XENON_MMC_MAX_CLK 400000000
HZ? (A comment would suffice.)
Ok.
+#define XENON_MMC_CLK_RATIO 2046 +#define XENON_MMC_BASE_CLK XENON_MMC_MAX_CLK / XENON_MMC_CLK_RATIO
+#define XENON_MMC_CMD_MAX_TIMEOUT 3200 +#define XENON_MMC_CMD_DEFAULT_TIMEOUT 100
+/* Tuning Parameter */ +#define TMR_RETUN_NO_PRESENT 0xf +#define XENON_MAX_TUN_COUNT 0xb
+#define EMMC_PHY_REG_BASE 0x170 +#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE +#define OUTPUT_QSN_PHASE_SELECT (1 << 17) +#define SAMPL_INV_QSP_PHASE_SELECT (1 << 18) +#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 +#define PHY_INITIALIZAION (1 << 31) +#define WAIT_CYCLE_BEFORE_USING_MASK 0xf +#define WAIT_CYCLE_BEFORE_USING_SHIFT 12 +#define FC_SYNC_EN_DURATION_MASK 0xf +#define FC_SYNC_EN_DURATION_SHIFT 8 +#define FC_SYNC_RST_EN_DURATION_MASK 0xf +#define FC_SYNC_RST_EN_DURATION_SHIFT 4 +#define FC_SYNC_RST_DURATION_MASK 0xf +#define FC_SYNC_RST_DURATION_SHIFT 0
+#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4) +#define DQ_ASYNC_MODE (1 << 4) +#define DQ_DDR_MODE_SHIFT 8 +#define DQ_DDR_MODE_MASK 0xff +#define CMD_DDR_MODE (1 << 16)
+#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8) +#define REC_EN_SHIFT 24 +#define REC_EN_MASK 0xf +#define FC_DQ_RECEN (1 << 24) +#define FC_CMD_RECEN (1 << 25) +#define FC_QSP_RECEN (1 << 26) +#define FC_QSN_RECEN (1 << 27) +#define OEN_QSN (1 << 28) +#define AUTO_RECEN_CTRL (1 << 30)
+#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc) +#define EMMC_PHY_PAD_CONTROL2 (EMMC_PHY_REG_BASE + 0x10) +#define EMMC_PHY_DLL_CONTROL (EMMC_PHY_REG_BASE + 0x14) +#define DLL_DELAY_TEST_LOWER_SHIFT 8 +#define DLL_DELAY_TEST_LOWER_MASK 0xff +#define DLL_BYPASS_EN 0x1
+#define EMMC_LOGIC_TIMING_ADJUST (EMMC_PHY_REG_BASE + 0x18) +#define EMMC_LOGIC_TIMING_ADJUST_LOW (EMMC_PHY_REG_BASE + 0x1c)
+#define MVEBU_IP_CONFIG_REG (0xf0000000 + 0x6F4100)
Again, slightly uncomfortable with this hard-coded address. (But depending on what you do about my comment on where this is actually used, could possibly be dropped.)
Yes, It will be removed from there.
+#define LOGIC_TIMING_VALUE 0x5a54 /* Recommend by HW team */
+/* Hyperion only have one slot 0 */
What is Hyperion? Internal name of a specific devboard?
It's old name and should be removed
Thanks!
Regards,
Leif
From: Jan Dąbroś jsd@semihalf.com
FV size had to be increased after this change, as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com --- Platforms/Marvell/Armada/Armada.dsc.inc | 5 +++++ Platforms/Marvell/Armada/Armada70x0.fdf | 7 ++++++- 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc index 0b1c50d..f585e90 100644 --- a/Platforms/Marvell/Armada/Armada.dsc.inc +++ b/Platforms/Marvell/Armada/Armada.dsc.inc @@ -436,6 +436,11 @@ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ # SD/MMC + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + OpenPlatformPkg/Drivers/SdMmc/MvSdMmcPciHcDxe.inf + # Console packages MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf diff --git a/Platforms/Marvell/Armada/Armada70x0.fdf b/Platforms/Marvell/Armada/Armada70x0.fdf index b420153..173f05d 100644 --- a/Platforms/Marvell/Armada/Armada70x0.fdf +++ b/Platforms/Marvell/Armada/Armada70x0.fdf @@ -49,7 +49,7 @@ NumBlocks = 0x400 # ################################################################################
-0x00000000|0x000E0000 +0x00000000|0x000E6000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT
@@ -141,6 +141,11 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ # SD/MMC + INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + INF OpenPlatformPkg/Drivers/SdMmc/MvSdMmcPciHcDxe.inf + # Multiple Console IO support INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
On Thu, Nov 17, 2016 at 12:05:25PM +0100, Marcin Wojtas wrote:
From: Jan Dąbroś jsd@semihalf.com
FV size had to be increased after this change, as well.
If you can just expand the commit message slightly... "Add MvSdMmcPciHcDxe driver, and required core libraries. Increase FV size to accommodate new additions."
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros jsd@semihalf.com Signed-off-by: Marcin Wojtas mw@semihalf.com
Platforms/Marvell/Armada/Armada.dsc.inc | 5 +++++ Platforms/Marvell/Armada/Armada70x0.fdf | 7 ++++++- 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc index 0b1c50d..f585e90 100644 --- a/Platforms/Marvell/Armada/Armada.dsc.inc +++ b/Platforms/Marvell/Armada/Armada.dsc.inc @@ -436,6 +436,11 @@ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- # SD/MMC
- MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
- MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
- OpenPlatformPkg/Drivers/SdMmc/MvSdMmcPciHcDxe.inf
- # Console packages MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
diff --git a/Platforms/Marvell/Armada/Armada70x0.fdf b/Platforms/Marvell/Armada/Armada70x0.fdf index b420153..173f05d 100644 --- a/Platforms/Marvell/Armada/Armada70x0.fdf +++ b/Platforms/Marvell/Armada/Armada70x0.fdf @@ -49,7 +49,7 @@ NumBlocks = 0x400 # ################################################################################ -0x00000000|0x000E0000 +0x00000000|0x000E6000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT @@ -141,6 +141,11 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- # SD/MMC
- INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
- INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
- INF OpenPlatformPkg/Drivers/SdMmc/MvSdMmcPciHcDxe.inf
- # Multiple Console IO support INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
-- 1.8.3.1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com --- Platforms/Marvell/Armada/Armada70x0.dsc | 1 + 1 file changed, 1 insertion(+)
diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 3c0cbad..4014d00 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -142,6 +142,7 @@ #PciEmulation gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
#ResetLib gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084
On Thu, Nov 17, 2016 at 12:05:26PM +0100, Marcin Wojtas wrote:
Some kind of commit message please.
"Add a Pcd entry to make NonDiscoverable platform library pick up the driver..." or something.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Platforms/Marvell/Armada/Armada70x0.dsc | 1 + 1 file changed, 1 insertion(+)
diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 3c0cbad..4014d00 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -142,6 +142,7 @@ #PciEmulation gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
#ResetLib gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084 -- 1.8.3.1
-
Jan Dąbroś -
Leif Lindholm -
Marcin Wojtas