Hisilicon new platform D05 will be pushed to Linaro Reference Platform 16.12 release, and these patches are to enable Hisilicon D05 in OPP. Also add the patches D02/3 platform bug fixed.
Code can also be found in my linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-16.12-03-all
Changelog v5>v6:
- Improve the code according to Leif's comments - Add new patches to fix new issues after updating EDKII base code and some new bug fix they are path 31--37: Hisilicon/D05: update distance of Slit table Platforms/D05/ACPI:dynamically detect chip version to set port enable/disable D03 enhance RTC lock acquiring Hisilicon: fix PXE boot fail issue Hisilicon/D05: flash related drivers switch to use generic BaseMemoryLib Hisilicon/D03: flash related drivers switch to use generic BaseMemoryLib Hisilicon/D02: flash related drivers switch to use generic
Chenhui Sun (6): D02/ACPI: Use HISI0031 HID for uart on Hip05 soc Platform/D02: Update ACPI table header D03: Update ACPI Oem table header id D02: Update ACPI table header id D02/D03: Update version to 16.08 RC1 Hisilicon/D05: update distance of Slit table
Hanjun Guo (1): D03/DSDT: use irq producer/consumer to support mbi-gen
Heyi Guo (19): Platforms/Hisilicon: add D05 platform modules and files Hisilicon: fix FirmwareVendor pcd Hisilicon/D02: enlarge FVMAIN_COMPACT Hisilicon/D02: update ATF binaries to fix a bug in ATF code Hisilicon/D03: enlarge FVMAIN_COMPACT Platforms/D03: Update binaries D02/D03/D05: Support Spd mirror mode Hisilicon: remove D02 unused ACPI files Hisilicon: Add D03 ACPI tables Hisilicon/SMBIOS: Update ProcessorID from MIDR Hisilicon: Remove unnesseary variable initializtion D03/FdtUpdateLib: Update refclk in DT D03/ACPI: Refine SAS ASL code indention D03/USB: fix ehci interrupt pin number Hisilicon/D03: switch to NullMemoryTest Hisilicon: fix PXE boot fail issue Hisilicon/D05: flash related drivers switch to use generic BaseMemoryLib Hisilicon/D03: flash related drivers switch to use generic BaseMemoryLib Hisilicon/D02: flash related drivers switch to use generic BaseMemoryLib
Kefeng Wang (1): D02/D03/ACPI: Fix wrong GTDT length
Kejian Yan (2): D02/D03/Dsdt: add media-type property for hns D02/D03/Dsdt/hns: fix the bug of serdes loopback
MaJun (1): D03/IORT:Change the single mapping flags of mbigen node to 1
Peicong Li (2): D03/D05: Change to access EEPROM data by checking page boundary D03: enhance RTC lock acquiring
Salil Mehta (3): D03/ACPI: Add RoCE device to ACPI & IORT Tables D03/ACPI: Add support of RoCE Reset in DSDT D03/ACPI/ROCE: Add node-guid parameter to DSDT
flyingnosky (1): D03/ACPI: support 50MHZ and 66MHZ boards in acpi mode
huangming23 (1): Platforms/D05/ACPI:dynamically detect chip version to set port enable/disable
.../Library/Hi1610Serdes/Hi1610SerdesLib.lib | Bin 601828 -> 603524 bytes .../Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib | Bin 253328 -> 247176 bytes .../Binary/Hi1610/Library/LpcLib/LpcLib.lib | Bin 13870 -> 13998 bytes .../Uart/LpcSerialPortLib/LpcSerialPortLib.lib | Bin 17086 -> 17022 bytes .../ProcessorSubClassDxe/ProcessorSubClass.c | 6 +- .../Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf | 56 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 368 +++++++++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 85 +++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl | 88 +++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 36 ++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 691 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 305 +++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 261 ++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 367 +++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 136 ++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 29 + .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 91 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 96 +++ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 48 ++ .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 128 ++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc | 81 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc | 115 ++++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 8 +- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 33 +- Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 71 +++ Chips/Hisilicon/HisiPkg.dec | 3 + Chips/Hisilicon/Include/Library/HwMemInitLib.h | 4 + .../Library/PlatformIntelBdsLib/IntelBdsPlatform.c | 2 + .../PlatformIntelBdsLib/PlatformIntelBdsLib.inf | 1 + .../Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf | 56 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl | 337 ---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc | 85 --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 5 +- .../Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 558 ----------------- .../Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl | 125 ---- .../Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl | 261 -------- .../Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl | 247 -------- .../Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl | 136 ---- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- .../Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl | 29 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 16 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl | 25 - Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 6 +- .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 128 ---- .../Pv660/Pv660AcpiTables/Pv660Platform.h | 10 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 2 +- Platforms/Hisilicon/Binary/D02/bl1.bin | Bin 14344 -> 12296 bytes Platforms/Hisilicon/Binary/D02/fip.bin | Bin 45621 -> 45621 bytes .../D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 22304 -> 21696 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 22240 -> 22208 bytes .../Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 26720 -> 25440 bytes .../D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 24704 -> 23712 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 18368 -> 18080 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 63648 -> 56832 bytes .../Binary/D03/Drivers/OhciDxe/NativeOhci.efi | Bin 55488 -> 48352 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 22752 -> 22112 bytes .../Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi | Bin 262144 -> 262144 bytes .../D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 38624 -> 36480 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 22112 -> 21408 bytes Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi | Bin 159744 -> 134240 bytes .../Library/OemAddressMap2P/OemAddressMap2P.lib | Bin 19568 -> 19486 bytes Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/Binary/D03/bl1.bin | Bin 14336 -> 14336 bytes Platforms/Hisilicon/Binary/D03/fip.bin | Bin 45601 -> 45601 bytes Platforms/Hisilicon/D02/Pv660D02.dsc | 9 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 22 +- Platforms/Hisilicon/D03/D03.dsc | 17 +- Platforms/Hisilicon/D03/D03.fdf | 10 +- .../Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 45 +- Platforms/Hisilicon/D03/Include/Library/CpldD03.h | 4 + .../DS3231RealTimeClockLib.c | 83 ++- .../DS3231RealTimeClockLib.inf | 2 + .../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 60 ++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 + Platforms/Hisilicon/D05/D05.dsc | 679 ++++++++++++++++++++ Platforms/Hisilicon/D05/D05.fdf | 366 +++++++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 64 ++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 ++ .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 225 +++++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 ++ .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 ++++++ 91 files changed, 5488 insertions(+), 2066 deletions(-) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
D05 is a new Hisilicon reference hardware platform, which is a dual socket SMP system and has 32 cores on each socket.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 71 +++ Chips/Hisilicon/HisiPkg.dec | 3 + Platforms/Hisilicon/D05/D05.dsc | 674 +++++++++++++++++++++ Platforms/Hisilicon/D05/D05.fdf | 366 +++++++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 64 ++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 ++ .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 225 +++++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 ++ .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 ++++++ 12 files changed, 2136 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h new file mode 100644 index 0000000..941bb04 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -0,0 +1,71 @@ +#ifndef _SERDES_LIB_H_ +#define _SERDES_LIB_H_ + +typedef enum hilink0_mode_type { + EM_HILINK0_HCCS1_8LANE = 0, + EM_HILINK0_PCIE1_8LANE = 2, + EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3, + EM_HILINK0_SAS2_8LANE = 4, + EM_HILINK0_HCCS1_8LANE_16, + EM_HILINK0_HCCS1_8LANE_32, + EM_HILINK0_HCCS1_8LANE_5000, +} hilink0_mode_type_e; + +typedef enum hilink1_mode_type { + EM_HILINK1_SAS2_1LANE = 0, + EM_HILINK1_HCCS0_8LANE = 1, + EM_HILINK1_PCIE0_8LANE = 2, + EM_HILINK1_HCCS0_8LANE_16, + EM_HILINK1_HCCS0_8LANE_32, + EM_HILINK1_HCCS0_8LANE_5000, +} hilink1_mode_type_e; + +typedef enum hilink2_mode_type { + EM_HILINK2_PCIE2_8LANE = 0, + EM_HILINK2_HCCS2_8LANE = 1, + EM_HILINK2_SAS0_8LANE = 2, + EM_HILINK2_HCCS2_8LANE_16, + EM_HILINK2_HCCS2_8LANE_32, + EM_HILINK2_HCCS2_8LANE_5000, +} hilink2_mode_type_e; + +typedef enum hilink5_mode_type { + EM_HILINK5_PCIE3_4LANE = 0, + EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1, + EM_HILINK5_SAS1_4LANE = 2, +} hilink5_mode_type_e; + + +typedef struct serdes_param { + hilink0_mode_type_e hilink0_mode; + hilink1_mode_type_e hilink1_mode; + hilink2_mode_type_e hilink2_mode; + UINT32 hilink3_mode; + UINT32 hilink4_mode; + hilink5_mode_type_e hilink5_mode; + UINT32 hilink6_mode; + UINT32 use_ssc; +} serdes_param_t; + +#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF + +typedef struct { + UINT32 MacroId; + UINT32 DsNum; + UINT32 DsCfg; +} SERDES_POLARITY_INVERT; + +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; +UINT32 GetEthType(UINT8 EthChannel); +VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); + +EFI_STATUS +EfiSerdesInitWrap (VOID); +INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); +VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro); + +#endif diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 0faa100..2c02e14 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -104,7 +104,10 @@ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a + gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b + gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
+ gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d
gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038 diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000..edaad18 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -0,0 +1,674 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = D05 + PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf + DEFINE EDK2_SKIP_PEICORE=0 + DEFINE INCLUDE_TFTP_COMMAND=1 + DEFINE NETWORK_IP6_ENABLE = FALSE + DEFINE HTTP_BOOT_ENABLE = FALSE + +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + + + I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf + + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + +!if $(NETWORK_IP6_ENABLE) == TRUE + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf +!endif + +!if $(HTTP_BOOT_ENABLE) == TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + +!ifdef $(FDT_ENABLE) + #FDTUpdateLib + FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf +!endif #$(FDT_ENABLE) + + CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf + + SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf + + EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf + #D05 RTC hardware is same as D03 + RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf + + OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf + OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf + PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf + PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + +[LibraryClasses.common.SEC] + ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf + + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + +[BuildOptions] + GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + +!if $(EDK2_SKIP_PEICORE) == 1 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE + +[PcdsFixedAtBuild.common] + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05" + + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000 + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00 + + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 + + + gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000 + + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000 + + gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1 + + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + + gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2 + + + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000 + + ## Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000 + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + # use the TTY terminal type (which has a working backspace) + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + + gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 + gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 + gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 + gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 + + + gHisiTokenSpaceGuid.PcdIsMPBoot|1 + gHisiTokenSpaceGuid.PcdSocketMask|0x3 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1" + + gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" + + gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12" + + gHisiTokenSpaceGuid.PcdSystemProductName|L"D05" + gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" + gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05" + gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary" + + gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616" + + + gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000 + + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM Architectual Timer Frequency + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + + gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000 + gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 + + gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000 + + gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000 + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000 + + + gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128 + + + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000 + + + gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000 + + ## DTB address at spi flash + gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000 + + gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1 + + gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000 + + gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000 + + gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000 + + gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000 + gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000 + + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1 + gHisiTokenSpaceGuid.PcdNumaEnable|1 + gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000 + + gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000 + + + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000 + + gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000 + gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000 + gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000 + gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000 + gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000 + gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000 + gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000 + gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000 + gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000 + gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000 + gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000 + gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000 + gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000 + gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000 + gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000 + gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000 + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000 + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000 + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K + + gHisiTokenSpaceGuid.Pcdsoctype|0x1610 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + + # + # PEI Phase modules + # + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf + + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf + + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug. + #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { + <LibraryClasses> + CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf + } + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + # + #ACPI + # + OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + # Usb Support + # + OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf + + # + #network + # + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf + + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + NetworkPkg/Ip6Dxe/Ip6Dxe.inf + NetworkPkg/TcpDxe/TcpDxe.inf + NetworkPkg/Udp6Dxe/Udp6Dxe.inf + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf +!endif + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(HTTP_BOOT_ENABLE) == TRUE + NetworkPkg/DnsDxe/DnsDxe.inf + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + NetworkPkg/HttpDxe/HttpDxe.inf + NetworkPkg/HttpBootDxe/HttpBootDxe.inf +!endif + + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + + OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf + + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + +!ifdef $(FDT_ENABLE) + OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +!endif #$(FDT_ENABLE) + + #PCIe Support + OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf { + <LibraryClasses> + NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + <LibraryClasses> + NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + + + OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + # Memory test + # + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + <LibraryClasses> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf +!endif + +!ifdef $(INCLUDE_DP) + NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf +!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND) + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000..bdfb211 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -0,0 +1,366 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[DEFINES] + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05] + +BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. + +Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv + +0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin +0x002A0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin + +0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 + 0xB8, 0xdF, 0x00, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, + 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +0x002F0000|0x00010000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + } + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf + + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + + # + # Usb Support + # + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf + + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + #ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf + + INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + #Network + # + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf + + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf +!endif + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(HTTP_BOOT_ENABLE) == TRUE + INF NetworkPkg/DnsDxe/DnsDxe.inf + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + INF NetworkPkg/HttpDxe/HttpDxe.inf + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf +!endif + +!ifdef $(FDT_ENABLE) + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +!endif #$(FDT_ENABLE) + + # + # PCI Support + # + INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf + # VGA Driver + # + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf + # + # UEFI application (Shell Embedded Boot Loader) + # + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf + + # + # Build Shell from latest source code instead of prebuilt binary + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + } + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc + diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000..76a055c --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + + +#include <PiPei.h> +#include <PlatformArch.h> +#include <Uefi.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformSysCtrlLib.h> + +VOID +QResetAp ( + VOID + ) +{ + MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0); + (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8); + + if (!PcdGet64 (PcdTrustedFirmwareEnable)) { + StartupAp(); + } +} + + +EFI_STATUS +EFIAPI +EarlyConfigEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG((DEBUG_INFO,"SMMU CONFIG.........")); + (VOID)SmmuConfigForBios(); + DEBUG((DEBUG_INFO,"Done\n")); + + DEBUG((DEBUG_INFO,"AP CONFIG.........")); + (VOID)QResetAp(); + DEBUG((DEBUG_INFO,"Done\n")); + + DEBUG((DEBUG_INFO,"MN CONFIG.........")); + (VOID)MN_CONFIG(); + DEBUG((DEBUG_INFO,"Done\n")); + + return EFI_SUCCESS; +} + diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000..5fdf555 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = EarlyConfigPeimD05 + FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = EarlyConfigEntry + +[Sources.common] + EarlyConfigPeimD05.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + ArmLib + CacheMaintenanceLib + DebugLib + IoLib + PcdLib + PeimEntryPoint + PlatformSysCtrlLib + +[Pcd] + gHisiTokenSpaceGuid.PcdMailBoxAddress + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + +[Depex] +## As we will clean mailbox in this module, need to wait memory init complete + gEfiPeiMemoryDiscoveredPpiGuid + +[BuildOptions] + diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000..473da0a --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,225 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <PlatformArch.h> +#include <Uefi.h> +#include <IndustryStandard/SmBios.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HiiLib.h> +#include <Library/I2CLib.h> +#include <Library/IoLib.h> +#include <Library/OemMiscLib.h> +#include <Library/SerdesLib.h> +#include <Protocol/Smbios.h> + + +I2C_DEVICE gDS3231RtcDevice = { + .Socket = 0, + .Port = 4, + .DeviceType = DEVICE_TYPE_SPD, + .SlaveDeviceAddress = 0x68 +}; + +SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = { + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = { + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +serdes_param_t gSerdesParamNA = { + .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16, + .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16, + .hilink2_mode = EM_HILINK2_PCIE2_8LANE, + .hilink3_mode = 0x0, + .hilink4_mode = 0xF, + .hilink5_mode = EM_HILINK5_SAS1_4LANE, + .hilink6_mode = 0x0, + .use_ssc = 0, +}; + +serdes_param_t gSerdesParamNB = { + .hilink0_mode = EM_HILINK0_PCIE1_8LANE, + .hilink1_mode = EM_HILINK1_PCIE0_8LANE, + .hilink2_mode = EM_HILINK2_SAS0_8LANE, + .hilink3_mode = 0x0, + .hilink4_mode = 0xF, + .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE, + .hilink6_mode = 0xF, + .use_ssc = 0, +}; + +serdes_param_t gSerdesParamS1NA = { + .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16, + .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16, + .hilink2_mode = EM_HILINK2_PCIE2_8LANE, + .hilink3_mode = 0x0, + .hilink4_mode = 0xF, + .hilink5_mode = EM_HILINK5_SAS1_4LANE, + .hilink6_mode = 0x0, + .use_ssc = 0, +}; + +serdes_param_t gSerdesParamS1NB = { + .hilink0_mode = EM_HILINK0_PCIE1_8LANE, + .hilink1_mode = EM_HILINK1_PCIE0_8LANE, + .hilink2_mode = EM_HILINK2_SAS0_8LANE, + .hilink3_mode = 0x0, + .hilink4_mode = 0xF, + .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE, + .hilink6_mode = 0xF, + .use_ssc = 0, +}; + + +EFI_STATUS +OemGetSerdesParam ( + OUT serdes_param_t *ParamA, + OUT serdes_param_t *ParamB, + IN UINT32 SocketId + ) +{ + if (ParamA == NULL || ParamB == NULL) { + DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + if (SocketId == 0) { + (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA)); + (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB)); + } else { + (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA)); + (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB)); + } + + return EFI_SUCCESS; +} + +VOID +OemPcieResetAndOffReset ( + VOID + ) +{ + return; +} + +SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = { + // PCIe0 Slot 1 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0001, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + + // PCIe0 Slot 4 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0004, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + } +}; + + +UINT8 +OemGetPcieSlotNumber ( + VOID + ) +{ + return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); +} + +EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { + {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}}, + + {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}} +}; + +EFI_HII_HANDLE +EFIAPI +OemGetPackages ( + ) +{ + return HiiAddPackages ( + &gEfiCallerIdGuid, + NULL, + OemMiscLibHi1616EvbStrings, + NULL, + NULL + ); +} + + diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/ + +/=# + +#langdef en-US "English" + +// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown" + +// +// DIMM Device Locator strings + +#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28" + +// +// End English Language Strings +// + diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..b17eead --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <PlatformArch.h> +#include <Uefi.h> + +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h> + +#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2 + +REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { + {67,0,0,0}, + {225,0,0,3}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF} +}; + + +BOOLEAN OemIsSocketPresent (UINTN Socket) +{ + if (PcdGet32(PcdSocketMask) & (1 << Socket)) { + return TRUE; + } else { + return FALSE; + } +} + + +UINTN OemGetSocketNumber (VOID) +{ + + if(!OemIsMpBoot()) { + return OEM_SINGLE_SOCKET; + } + + return OEM_DUAL_SOCKET; +} + + +UINTN OemGetDdrChannel (VOID) +{ + return 4; +} + + +UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{ + return 2; +} + +VOID CoreSelectBoot(VOID) +{ + if (!PcdGet64 (PcdTrustedFirmwareEnable)) { + StartupAp (); + } + + return; +} + +BOOLEAN OemIsMpBoot() +{ + return PcdGet32(PcdIsMPBoot); +} + +VOID OemLpcInit(VOID) +{ + LpcInit(); + return; +} + +UINT32 OemIsWarmBoot(VOID) +{ + return 0; +} + +VOID OemBiosSwitch(UINT32 Master) +{ + (VOID)Master; + return; +} + +BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{ + return TRUE; +} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = OemMiscLibHi1616Evb + FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = OemMiscLib + +[Sources.common] + BoardFeatureD05.c + BoardFeatureD05Strings.uni + OemMiscLibD05.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + TimerLib + +[BuildOptions] + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES + +[Pcd] + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz + gHisiTokenSpaceGuid.PcdIsMPBoot + gHisiTokenSpaceGuid.PcdSocketMask + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + +[FixedPcd.common] + +[Guids] + +[Protocols] + diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file + + Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> + +UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000}, + {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}}; +UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000}, + {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}}; +UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000}, + {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}}; +UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040}, + {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}}; + +PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { + {// HostBridge 0 + /* Port 0 */ + { + PCI_HB0RB0_ECAM_BASE, //ecam + 0x80, //BusBase + 0x87, //BusLimit + PCI_HB0RB0_PCIREGION_BASE, //Membase + PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit + PCI_HB0RB0_IO_BASE, //IoBase + (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB0_PCI_BASE),//RbPciBar + PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 1 */ + { + PCI_HB0RB1_ECAM_BASE,//ecam + 0x90, //BusBase + 0x97, //BusLimit + PCI_HB0RB1_PCIREGION_BASE, //Membase + PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB1_IO_BASE), //IoBase + (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit + PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 2 */ + { + PCI_HB0RB2_ECAM_BASE, + 0x80, //BusBase + 0x87, //BusLimit + PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase + PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB2_IO_BASE), //IOBase + (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit + PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 3 */ + { + PCI_HB0RB3_ECAM_BASE, + 0xb0, //BusBase + 0xb7, //BusLimit + (PCI_HB0RB3_ECAM_BASE), //MemBase + (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit + (PCI_HB0RB3_IO_BASE), //IoBase + (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit + PCI_HB0RB3_CPUMEMREGIONBASE, + PCI_HB0RB3_CPUIOREGIONBASE, + (PCI_HB0RB3_PCI_BASE), //RbPciBar + PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 4 */ + { + PCI_HB0RB4_ECAM_BASE, //ecam + 0x88, //BusBase + 0x8f, //BusLimit + PCI_HB0RB4_CPUMEMREGIONBASE, //Membase + PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit + PCI_HB0RB4_IO_BASE, //IoBase + (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit + PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB4_PCI_BASE), //RbPciBar + PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 5 */ + { + PCI_HB0RB5_ECAM_BASE,//ecam + 0x0, //BusBase + 0x7, //BusLimit + PCI_HB0RB5_CPUMEMREGIONBASE, //Membase + PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB5_IO_BASE), //IoBase + (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit + PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB5_PCI_BASE), //RbPciBar + PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 6 */ + { + PCI_HB0RB6_ECAM_BASE, + 0xC0, //BusBase + 0xC7, //BusLimit + PCI_HB0RB6_PCIREGION_BASE ,//MemBase + PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB6_IO_BASE), //IOBase + (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit + PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB6_PCI_BASE), //RbPciBar + PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 7 */ + { + PCI_HB0RB7_ECAM_BASE, + 0x90, //BusBase + 0x97, //BusLimit + PCI_HB0RB7_CPUMEMREGIONBASE, //MemBase + PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB7_IO_BASE), //IoBase + (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit + PCI_HB0RB7_CPUMEMREGIONBASE, + PCI_HB0RB7_CPUIOREGIONBASE, + (PCI_HB0RB7_PCI_BASE), //RbPciBar + PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit + } + }, +{// HostBridge 1 + /* Port 0 */ + { + PCI_HB1RB0_ECAM_BASE, + 0x80, //BusBase + 0x87, //BusLimit + (PCI_HB1RB0_ECAM_BASE), //MemBase + (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB0_IO_BASE, //IoBase + (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB0_PCI_BASE), //RbPciBar + PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 1 */ + { + PCI_HB1RB1_ECAM_BASE, + 0x90, //BusBase + 0x97, //BusLimit + (PCI_HB1RB1_ECAM_BASE), //MemBase + (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB1_IO_BASE, //IoBase + (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB1_PCI_BASE), //RbPciBar + PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 2 */ + { + PCI_HB1RB2_ECAM_BASE, + 0x10, //BusBase + 0x1f, //BusLimit + PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB2_IO_BASE, //IoBase + (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB2_PCI_BASE), //RbPciBar + PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 3 */ + { + PCI_HB1RB3_ECAM_BASE, + 0xb0, //BusBase + 0xb7, //BusLimit + (PCI_HB1RB3_ECAM_BASE), //MemBase + (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB3_IO_BASE, //IoBase + (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB3_PCI_BASE), //RbPciBar + PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 4 */ + { + PCI_HB1RB4_ECAM_BASE, + 0x20, //BusBase + 0x2f, //BusLimit + PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB4_IO_BASE, //IoBase + (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB4_PCI_BASE), //RbPciBar + PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 5 */ + { + PCI_HB1RB5_ECAM_BASE, + 0x30, //BusBase + 0x3f, //BusLimit + PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB5_IO_BASE, //IoBase + (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB5_PCI_BASE), //RbPciBar + PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 6 */ + { + PCI_HB1RB6_ECAM_BASE, + 0xa8, //BusBase + 0xaf, //BusLimit + (PCI_HB1RB6_ECAM_BASE), //MemBase + PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB6_IO_BASE, //IoBase + (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB6_PCI_BASE), //RbPciBar + PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 7 */ + { + PCI_HB1RB7_ECAM_BASE, + 0xb8, //BusBase + 0xbf, //BusLimit + (PCI_HB1RB7_ECAM_BASE), //MemBase + PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB7_IO_BASE, //IoBase + (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB7_PCI_BASE), //RbPciBar + PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit + } + + } +}; + diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = PlatformPciLib + FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + +[Sources] + PlatformPciLib.c + +[Packages] + MdePkg/MdePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + +[FixedPcd] + gHisiTokenSpaceGuid.PcdHb1BaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PciHb0Rb0Base + gHisiTokenSpaceGuid.PciHb0Rb1Base + gHisiTokenSpaceGuid.PciHb0Rb2Base + gHisiTokenSpaceGuid.PciHb0Rb3Base + gHisiTokenSpaceGuid.PciHb0Rb4Base + gHisiTokenSpaceGuid.PciHb0Rb5Base + gHisiTokenSpaceGuid.PciHb0Rb6Base + gHisiTokenSpaceGuid.PciHb0Rb7Base + gHisiTokenSpaceGuid.PciHb1Rb0Base + gHisiTokenSpaceGuid.PciHb1Rb1Base + gHisiTokenSpaceGuid.PciHb1Rb2Base + gHisiTokenSpaceGuid.PciHb1Rb3Base + gHisiTokenSpaceGuid.PciHb1Rb4Base + gHisiTokenSpaceGuid.PciHb1Rb5Base + gHisiTokenSpaceGuid.PciHb1Rb6Base + gHisiTokenSpaceGuid.PciHb1Rb7Base + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize +
On Tue, Dec 06, 2016 at 06:56:32PM +0800, Heyi Guo wrote:
D05 is a new Hisilicon reference hardware platform, which is a dual socket SMP system and has 32 cores on each socket.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 71 +++ Chips/Hisilicon/HisiPkg.dec | 3 + Platforms/Hisilicon/D05/D05.dsc | 674 +++++++++++++++++++++ Platforms/Hisilicon/D05/D05.fdf | 366 +++++++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 64 ++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 ++ .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 225 +++++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 ++ .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 ++++++ 12 files changed, 2136 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h new file mode 100644 index 0000000..941bb04 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -0,0 +1,71 @@ +#ifndef _SERDES_LIB_H_ +#define _SERDES_LIB_H_
+typedef enum hilink0_mode_type {
- EM_HILINK0_HCCS1_8LANE = 0,
- EM_HILINK0_PCIE1_8LANE = 2,
- EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3,
- EM_HILINK0_SAS2_8LANE = 4,
- EM_HILINK0_HCCS1_8LANE_16,
- EM_HILINK0_HCCS1_8LANE_32,
- EM_HILINK0_HCCS1_8LANE_5000,
+} hilink0_mode_type_e;
+typedef enum hilink1_mode_type {
- EM_HILINK1_SAS2_1LANE = 0,
- EM_HILINK1_HCCS0_8LANE = 1,
- EM_HILINK1_PCIE0_8LANE = 2,
- EM_HILINK1_HCCS0_8LANE_16,
- EM_HILINK1_HCCS0_8LANE_32,
- EM_HILINK1_HCCS0_8LANE_5000,
+} hilink1_mode_type_e;
+typedef enum hilink2_mode_type {
- EM_HILINK2_PCIE2_8LANE = 0,
- EM_HILINK2_HCCS2_8LANE = 1,
- EM_HILINK2_SAS0_8LANE = 2,
- EM_HILINK2_HCCS2_8LANE_16,
- EM_HILINK2_HCCS2_8LANE_32,
- EM_HILINK2_HCCS2_8LANE_5000,
+} hilink2_mode_type_e;
+typedef enum hilink5_mode_type {
- EM_HILINK5_PCIE3_4LANE = 0,
- EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1,
- EM_HILINK5_SAS1_4LANE = 2,
+} hilink5_mode_type_e;
+typedef struct serdes_param {
- hilink0_mode_type_e hilink0_mode;
- hilink1_mode_type_e hilink1_mode;
- hilink2_mode_type_e hilink2_mode;
- UINT32 hilink3_mode;
- UINT32 hilink4_mode;
- hilink5_mode_type_e hilink5_mode;
- UINT32 hilink6_mode;
- UINT32 use_ssc;
+} serdes_param_t;
So, you have fixed the indentation here, but not the rest of my comments.
None of these typedefs conform to coding style. They should start like
typedef struct {
Contain CamelCase members.
and end like
} SERDES_PARAM;
Please correct all of the structs in this file, not just the local one.
(Although there was an error in my comment - no need to name the struct, we just need the typedef. So this particular struct should look like
typedef struct { HiLink0ModeType HiLink0Mode; ... } SERDES_PARAM;
.)
The rest of this patch (apart from the bits that will need to change to adapt to the above) is now fine.
Please fix and resubmit this patch only.
Regards,
Leif
+#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF
+typedef struct {
- UINT32 MacroId;
- UINT32 DsNum;
- UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; +UINT32 GetEthType(UINT8 EthChannel); +VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode);
+EFI_STATUS +EfiSerdesInitWrap (VOID); +INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); +VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
+#endif diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 0faa100..2c02e14 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -104,7 +104,10 @@ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
- gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
- gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
- gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d
gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038 diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000..edaad18 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -0,0 +1,674 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#
+################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines]
- PLATFORM_NAME = D05
- PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x00010019
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64
- BUILD_TARGETS = DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
- DEFINE EDK2_SKIP_PEICORE=0
- DEFINE INCLUDE_TFTP_COMMAND=1
- DEFINE NETWORK_IP6_ENABLE = FALSE
- DEFINE HTTP_BOOT_ENABLE = FALSE
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+[LibraryClasses.common]
- ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
- BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+!endif
+!if $(HTTP_BOOT_ENABLE) == TRUE
- HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+!ifdef $(FDT_ENABLE)
- #FDTUpdateLib
- FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
- CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
- SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
- EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
- #D05 RTC hardware is same as D03
- RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
- OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
- OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
- PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
- PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
- # USB Requirements
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
- LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[LibraryClasses.common.SEC]
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[BuildOptions]
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include
+################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################
+[PcdsFeatureFlag.common]
+!if $(EDK2_SKIP_PEICORE) == 1
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
- # It could be set FALSE to save size.
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
- gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+[PcdsFixedAtBuild.common]
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"
- gArmPlatformTokenSpaceGuid.PcdCoreCount|8
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- # Stacks for MPCores in Secure World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
- # Stacks for MPCores in Monitor Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
- # Stacks for MPCores in Normal World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
- gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
- #
- # ARM Pcds
- #
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
- gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- ## SP805 Watchdog - Motherboard Watchdog
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
- ## Serial Terminal
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
- # use the TTY terminal type (which has a working backspace)
- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
- gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
- gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
- gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
- gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gHisiTokenSpaceGuid.PcdIsMPBoot|1
- gHisiTokenSpaceGuid.PcdSocketMask|0x3
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1"
- gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
- gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
- gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
- gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
- #
- # ARM Architectual Timer Frequency
- #
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
- gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
- gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
- gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
- gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
- gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
- gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
- gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
- ## DTB address at spi flash
- gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000
- gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
- gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
- gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
- gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
- gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
- gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
- gHisiTokenSpaceGuid.PcdNumaEnable|1
- gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
- gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
- gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
- gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
- gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
- gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
- gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
- gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
- gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
- gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
- gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
- gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
- gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common]
- #
- # SEC
- #
- #
- # PEI Phase modules
- #
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- MdeModulePkg/Core/Pei/PeiMain.inf
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- ArmPkg/Drivers/CpuPei/CpuPei.inf
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf- }
- #
- # DXE
- #
- MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf- }
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # Architectural Protocols
- #
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug.
- #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf- }
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>
CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf- }
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- #ACPI
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- # Usb Support
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- #
- #network
- #
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- NetworkPkg/TcpDxe/TcpDxe.inf
- NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- NetworkPkg/DnsDxe/DnsDxe.inf
- NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- NetworkPkg/HttpDxe/HttpDxe.inf
- NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Bds
- #
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+!ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #PCIe Support
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- # Memory test
- #
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.infNULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.infNULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.infNULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.infNULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.infNULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.infHandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.infPrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.infBcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf+!if $(NETWORK_IP6_ENABLE) == TRUE
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf+!endif
+!ifdef $(INCLUDE_DP)
NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf+!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND)
NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf+!endif #$(INCLUDE_TFTP_COMMAND)
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFFgEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSEgEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000- }
diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000..bdfb211 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -0,0 +1,366 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#
+[DEFINES]
+################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05]
+BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1
+# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30
+################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################
+0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
+0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT
+0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin +0x002A0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin
+0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = {
- ## This is the EFI_FIRMWARE_VOLUME_HEADER
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- # FileSystemGuid: gEfiSystemNvDataFvGuid =
- 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
- 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
- # FvLength: 0x20000
- 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- #Signature "_FVH" #Attributes
- 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
- #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
- 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
- #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
- #Blockmap[1]: End
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
- 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
- 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
- #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
- 0xB8, 0xdF, 0x00, 0x00,
- #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
- 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = {
- # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
- 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
- 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
- # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
- 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
- # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
- 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+0x002F0000|0x00010000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################
+[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI DXE {
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- }
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
- #
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- #
- # Multiple Console IO support
- #
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- INF FatBinPkg/EnhancedFatDxe/Fat.inf
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- # Usb Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
- INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- #ACPI
- #
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- #Network
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- INF NetworkPkg/TcpDxe/TcpDxe.inf
- INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- INF NetworkPkg/DnsDxe/DnsDxe.inf
- INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- INF NetworkPkg/HttpDxe/HttpDxe.inf
- INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
+!ifdef $(FDT_ENABLE)
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #
- # PCI Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
- INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- # VGA Driver
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Build Shell from latest source code instead of prebuilt binary
- #
- INF ShellPkg/Application/Shell/Shell.inf
- #
- # Bds
- #
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI PEI {
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- }
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- INF MdeModulePkg/Core/Pei/PeiMain.inf
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN- }
- }
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000..76a055c --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PiPei.h> +#include <PlatformArch.h> +#include <Uefi.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformSysCtrlLib.h>
+VOID +QResetAp (
- VOID
- )
+{
- MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
- (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
- StartupAp();
- }
+}
+EFI_STATUS +EFIAPI +EarlyConfigEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
+{
- DEBUG((DEBUG_INFO,"SMMU CONFIG........."));
- (VOID)SmmuConfigForBios();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"AP CONFIG........."));
- (VOID)QResetAp();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"MN CONFIG........."));
- (VOID)MN_CONFIG();
- DEBUG((DEBUG_INFO,"Done\n"));
- return EFI_SUCCESS;
+}
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000..5fdf555 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = EarlyConfigPeimD05
- FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = EarlyConfigEntry
+[Sources.common]
- EarlyConfigPeimD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- ArmLib
- CacheMaintenanceLib
- DebugLib
- IoLib
- PcdLib
- PeimEntryPoint
- PlatformSysCtrlLib
+[Pcd]
- gHisiTokenSpaceGuid.PcdMailBoxAddress
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[Depex] +## As we will clean mailbox in this module, need to wait memory init complete
- gEfiPeiMemoryDiscoveredPpiGuid
+[BuildOptions]
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000..473da0a --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,225 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h> +#include <IndustryStandard/SmBios.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HiiLib.h> +#include <Library/I2CLib.h> +#include <Library/IoLib.h> +#include <Library/OemMiscLib.h> +#include <Library/SerdesLib.h> +#include <Protocol/Smbios.h>
+I2C_DEVICE gDS3231RtcDevice = {
- .Socket = 0,
- .Port = 4,
- .DeviceType = DEVICE_TYPE_SPD,
- .SlaveDeviceAddress = 0x68
+};
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+serdes_param_t gSerdesParamNA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamNB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+EFI_STATUS +OemGetSerdesParam (
- OUT serdes_param_t *ParamA,
- OUT serdes_param_t *ParamB,
- IN UINT32 SocketId
- )
+{
- if (ParamA == NULL || ParamB == NULL) {
- DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
- return EFI_INVALID_PARAMETER;
- }
- if (SocketId == 0) {
- (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
- } else {
- (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
- }
- return EFI_SUCCESS;
+}
+VOID +OemPcieResetAndOffReset (
- VOID
- )
+{
- return;
+}
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
- // PCIe0 Slot 1
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0001, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- },
- // PCIe0 Slot 4
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0004, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- }
+};
+UINT8 +OemGetPcieSlotNumber (
- VOID
- )
+{
- return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+EFI_HII_HANDLE +EFIAPI +OemGetPackages (
- )
+{
- return HiiAddPackages (
&gEfiCallerIdGuid,NULL,OemMiscLibHi1616EvbStrings,NULL,NULL);+}
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/
+/=#
+#langdef en-US "English"
+// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"
+// +// DIMM Device Locator strings
+#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28"
+// +// End English Language Strings +//
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..b17eead --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h>
+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h>
+#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
- {67,0,0,0},
- {225,0,0,3},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+BOOLEAN OemIsSocketPresent (UINTN Socket) +{
- if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
- return TRUE;
- } else {
- return FALSE;
- }
+}
+UINTN OemGetSocketNumber (VOID) +{
- if(!OemIsMpBoot()) {
- return OEM_SINGLE_SOCKET;
- }
- return OEM_DUAL_SOCKET;
+}
+UINTN OemGetDdrChannel (VOID) +{
- return 4;
+}
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{
- return 2;
+}
+VOID CoreSelectBoot(VOID) +{
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
StartupAp ();- }
- return;
+}
+BOOLEAN OemIsMpBoot() +{
- return PcdGet32(PcdIsMPBoot);
+}
+VOID OemLpcInit(VOID) +{
- LpcInit();
- return;
+}
+UINT32 OemIsWarmBoot(VOID) +{
- return 0;
+}
+VOID OemBiosSwitch(UINT32 Master) +{
- (VOID)Master;
- return;
+}
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{
- return TRUE;
+} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = OemMiscLibHi1616Evb
- FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = OemMiscLib
+[Sources.common]
- BoardFeatureD05.c
- BoardFeatureD05Strings.uni
- OemMiscLibD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
- TimerLib
+[BuildOptions]
+[Ppis]
- gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES
+[Pcd]
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
- gHisiTokenSpaceGuid.PcdIsMPBoot
- gHisiTokenSpaceGuid.PcdSocketMask
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[FixedPcd.common]
+[Guids]
+[Protocols]
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h>
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
{0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
{0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
{0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
{0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
- {// HostBridge 0
- /* Port 0 */
- {
PCI_HB0RB0_ECAM_BASE, //ecam0x80, //BusBase0x87, //BusLimitPCI_HB0RB0_PCIREGION_BASE, //MembasePCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB0_PCI_BASE),//RbPciBarPCI_HB0RB0_PCIREGION_BASE, //PciRegionbasePCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB0RB1_ECAM_BASE,//ecam0x90, //BusBase0x97, //BusLimitPCI_HB0RB1_PCIREGION_BASE, //MembasePCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB1_IO_BASE), //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimitPCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB1_PCI_BASE), //RbPciBarPCI_HB0RB1_PCIREGION_BASE, //PciRegionbasePCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB0RB2_ECAM_BASE,0x80, //BusBase0x87, //BusLimitPCI_HB0RB2_CPUMEMREGIONBASE ,//MemBasePCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB2_IO_BASE), //IOBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimitPCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB2_PCI_BASE), //RbPciBarPCI_HB0RB2_PCIREGION_BASE, //PciRegionbasePCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB0RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB0RB3_ECAM_BASE), //MemBase(PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit(PCI_HB0RB3_IO_BASE), //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimitPCI_HB0RB3_CPUMEMREGIONBASE,PCI_HB0RB3_CPUIOREGIONBASE,(PCI_HB0RB3_PCI_BASE), //RbPciBarPCI_HB0RB3_PCIREGION_BASE, //PciRegionbasePCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB0RB4_ECAM_BASE, //ecam0x88, //BusBase0x8f, //BusLimitPCI_HB0RB4_CPUMEMREGIONBASE, //MembasePCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimitPCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB4_PCI_BASE), //RbPciBarPCI_HB0RB4_PCIREGION_BASE, //PciRegionbasePCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB0RB5_ECAM_BASE,//ecam0x0, //BusBase0x7, //BusLimitPCI_HB0RB5_CPUMEMREGIONBASE, //MembasePCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB5_IO_BASE), //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimitPCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB5_PCI_BASE), //RbPciBarPCI_HB0RB5_PCIREGION_BASE, //PciRegionbasePCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB0RB6_ECAM_BASE,0xC0, //BusBase0xC7, //BusLimitPCI_HB0RB6_PCIREGION_BASE ,//MemBasePCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB6_IO_BASE), //IOBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimitPCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB6_PCI_BASE), //RbPciBarPCI_HB0RB6_PCIREGION_BASE, //PciRegionbasePCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB0RB7_ECAM_BASE,0x90, //BusBase0x97, //BusLimitPCI_HB0RB7_CPUMEMREGIONBASE, //MemBasePCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB7_IO_BASE), //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimitPCI_HB0RB7_CPUMEMREGIONBASE,PCI_HB0RB7_CPUIOREGIONBASE,(PCI_HB0RB7_PCI_BASE), //RbPciBarPCI_HB0RB7_PCIREGION_BASE, //PciRegionbasePCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- },
+{// HostBridge 1
- /* Port 0 */
- {
PCI_HB1RB0_ECAM_BASE,0x80, //BusBase0x87, //BusLimit(PCI_HB1RB0_ECAM_BASE), //MemBase(PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB0_PCI_BASE), //RbPciBarPCI_HB1RB0_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB1RB1_ECAM_BASE,0x90, //BusBase0x97, //BusLimit(PCI_HB1RB1_ECAM_BASE), //MemBase(PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB1_IO_BASE, //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB1_PCI_BASE), //RbPciBarPCI_HB1RB1_PCIREGION_BASE, //PciRegionbasePCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB1RB2_ECAM_BASE,0x10, //BusBase0x1f, //BusLimitPCI_HB1RB2_CPUMEMREGIONBASE, //MemBasePCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB2_IO_BASE, //IoBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB2_PCI_BASE), //RbPciBarPCI_HB1RB2_PCIREGION_BASE, //PciRegionbasePCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB1RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB1RB3_ECAM_BASE), //MemBase(PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB3_IO_BASE, //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB3_PCI_BASE), //RbPciBarPCI_HB1RB3_PCIREGION_BASE, //PciRegionbasePCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB1RB4_ECAM_BASE,0x20, //BusBase0x2f, //BusLimitPCI_HB1RB4_CPUMEMREGIONBASE, //MemBasePCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB4_PCI_BASE), //RbPciBarPCI_HB1RB4_PCIREGION_BASE, //PciRegionbasePCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB1RB5_ECAM_BASE,0x30, //BusBase0x3f, //BusLimitPCI_HB1RB5_CPUMEMREGIONBASE, //MemBasePCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB5_IO_BASE, //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB5_PCI_BASE), //RbPciBarPCI_HB1RB5_PCIREGION_BASE, //PciRegionbasePCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB1RB6_ECAM_BASE,0xa8, //BusBase0xaf, //BusLimit(PCI_HB1RB6_ECAM_BASE), //MemBasePCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB6_IO_BASE, //IoBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB6_PCI_BASE), //RbPciBarPCI_HB1RB6_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB1RB7_ECAM_BASE,0xb8, //BusBase0xbf, //BusLimit(PCI_HB1RB7_ECAM_BASE), //MemBasePCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB7_IO_BASE, //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB7_PCI_BASE), //RbPciBarPCI_HB1RB7_PCIREGION_BASE, //PciRegionbasePCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- }
+};
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = PlatformPciLib
- FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
+[Sources]
- PlatformPciLib.c
+[Packages]
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdHb1BaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PciHb0Rb0Base
- gHisiTokenSpaceGuid.PciHb0Rb1Base
- gHisiTokenSpaceGuid.PciHb0Rb2Base
- gHisiTokenSpaceGuid.PciHb0Rb3Base
- gHisiTokenSpaceGuid.PciHb0Rb4Base
- gHisiTokenSpaceGuid.PciHb0Rb5Base
- gHisiTokenSpaceGuid.PciHb0Rb6Base
- gHisiTokenSpaceGuid.PciHb0Rb7Base
- gHisiTokenSpaceGuid.PciHb1Rb0Base
- gHisiTokenSpaceGuid.PciHb1Rb1Base
- gHisiTokenSpaceGuid.PciHb1Rb2Base
- gHisiTokenSpaceGuid.PciHb1Rb3Base
- gHisiTokenSpaceGuid.PciHb1Rb4Base
- gHisiTokenSpaceGuid.PciHb1Rb5Base
- gHisiTokenSpaceGuid.PciHb1Rb6Base
- gHisiTokenSpaceGuid.PciHb1Rb7Base
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
-- 1.9.1
Hi Leif,
在 12/6/2016 7:48 PM, Leif Lindholm 写道:
On Tue, Dec 06, 2016 at 06:56:32PM +0800, Heyi Guo wrote:
D05 is a new Hisilicon reference hardware platform, which is a dual socket SMP system and has 32 cores on each socket.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 71 +++ Chips/Hisilicon/HisiPkg.dec | 3 + Platforms/Hisilicon/D05/D05.dsc | 674 +++++++++++++++++++++ Platforms/Hisilicon/D05/D05.fdf | 366 +++++++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 64 ++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 ++ .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 225 +++++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 ++ .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 ++++++ 12 files changed, 2136 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h new file mode 100644 index 0000000..941bb04 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -0,0 +1,71 @@ +#ifndef _SERDES_LIB_H_ +#define _SERDES_LIB_H_
+typedef enum hilink0_mode_type {
- EM_HILINK0_HCCS1_8LANE = 0,
- EM_HILINK0_PCIE1_8LANE = 2,
- EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3,
- EM_HILINK0_SAS2_8LANE = 4,
- EM_HILINK0_HCCS1_8LANE_16,
- EM_HILINK0_HCCS1_8LANE_32,
- EM_HILINK0_HCCS1_8LANE_5000,
+} hilink0_mode_type_e;
+typedef enum hilink1_mode_type {
- EM_HILINK1_SAS2_1LANE = 0,
- EM_HILINK1_HCCS0_8LANE = 1,
- EM_HILINK1_PCIE0_8LANE = 2,
- EM_HILINK1_HCCS0_8LANE_16,
- EM_HILINK1_HCCS0_8LANE_32,
- EM_HILINK1_HCCS0_8LANE_5000,
+} hilink1_mode_type_e;
+typedef enum hilink2_mode_type {
- EM_HILINK2_PCIE2_8LANE = 0,
- EM_HILINK2_HCCS2_8LANE = 1,
- EM_HILINK2_SAS0_8LANE = 2,
- EM_HILINK2_HCCS2_8LANE_16,
- EM_HILINK2_HCCS2_8LANE_32,
- EM_HILINK2_HCCS2_8LANE_5000,
+} hilink2_mode_type_e;
+typedef enum hilink5_mode_type {
- EM_HILINK5_PCIE3_4LANE = 0,
- EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1,
- EM_HILINK5_SAS1_4LANE = 2,
+} hilink5_mode_type_e;
+typedef struct serdes_param {
- hilink0_mode_type_e hilink0_mode;
- hilink1_mode_type_e hilink1_mode;
- hilink2_mode_type_e hilink2_mode;
- UINT32 hilink3_mode;
- UINT32 hilink4_mode;
- hilink5_mode_type_e hilink5_mode;
- UINT32 hilink6_mode;
- UINT32 use_ssc;
+} serdes_param_t;
So, you have fixed the indentation here, but not the rest of my comments.
None of these typedefs conform to coding style. They should start like
typedef struct {
Contain CamelCase members.
and end like
} SERDES_PARAM;
Please correct all of the structs in this file, not just the local one.
(Although there was an error in my comment - no need to name the struct, we just need the typedef. So this particular struct should look like
typedef struct { HiLink0ModeType HiLink0Mode; ... } SERDES_PARAM;
.)
Thanks for point out this. The member of Hilink0ModeType comes from the enum above:
typedef enum hilink0_mode_type { EM_HILINK0_HCCS1_8LANE = 0, EM_HILINK0_PCIE1_8LANE = 2, EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3, EM_HILINK0_SAS2_8LANE = 4, EM_HILINK0_HCCS1_8LANE_16, EM_HILINK0_HCCS1_8LANE_32, EM_HILINK0_HCCS1_8LANE_5000, } hilink0_mode_type_e;
So should i correct the enum to:
typedef enum { EmHilink0Hccs1_8Lane = 0, EmHilink0Pcie1_8Lane = 2, ..., } Hilink0ModeType;
or
typedef enum { EmHilink0Hccs1_8Lane = 0, EmHilink0Pcie1_8Lane = 2, ..., } HILINK0_MODE_TYPE;
?
Thanks and Regards, Heyi
The rest of this patch (apart from the bits that will need to change to adapt to the above) is now fine.
Please fix and resubmit this patch only.
Regards,
Leif
+#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF
+typedef struct {
- UINT32 MacroId;
- UINT32 DsNum;
- UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; +UINT32 GetEthType(UINT8 EthChannel); +VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode);
+EFI_STATUS +EfiSerdesInitWrap (VOID); +INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); +VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
+#endif diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 0faa100..2c02e14 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -104,7 +104,10 @@ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
- gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
- gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
- gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d
gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038 diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000..edaad18 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -0,0 +1,674 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#
+################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines]
- PLATFORM_NAME = D05
- PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x00010019
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64
- BUILD_TARGETS = DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
- DEFINE EDK2_SKIP_PEICORE=0
- DEFINE INCLUDE_TFTP_COMMAND=1
- DEFINE NETWORK_IP6_ENABLE = FALSE
- DEFINE HTTP_BOOT_ENABLE = FALSE
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+[LibraryClasses.common]
- ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
- BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+!endif
+!if $(HTTP_BOOT_ENABLE) == TRUE
- HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+!ifdef $(FDT_ENABLE)
- #FDTUpdateLib
- FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
- CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
- SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
- EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
- #D05 RTC hardware is same as D03
- RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
- OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
- OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
- PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
- PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
- # USB Requirements
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
- LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[LibraryClasses.common.SEC]
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[BuildOptions]
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include
+################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################
+[PcdsFeatureFlag.common]
+!if $(EDK2_SKIP_PEICORE) == 1
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
- # It could be set FALSE to save size.
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
- gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+[PcdsFixedAtBuild.common]
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"
- gArmPlatformTokenSpaceGuid.PcdCoreCount|8
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- # Stacks for MPCores in Secure World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
- # Stacks for MPCores in Monitor Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
- # Stacks for MPCores in Normal World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
- gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
- #
- # ARM Pcds
- #
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
- gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- ## SP805 Watchdog - Motherboard Watchdog
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
- ## Serial Terminal
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
- # use the TTY terminal type (which has a working backspace)
- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
- gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
- gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
- gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
- gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gHisiTokenSpaceGuid.PcdIsMPBoot|1
- gHisiTokenSpaceGuid.PcdSocketMask|0x3
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1"
- gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
- gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
- gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
- gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
- #
- # ARM Architectual Timer Frequency
- #
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
- gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
- gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
- gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
- gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
- gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
- gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
- gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
- ## DTB address at spi flash
- gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000
- gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
- gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
- gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
- gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
- gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
- gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
- gHisiTokenSpaceGuid.PcdNumaEnable|1
- gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
- gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
- gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
- gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
- gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
- gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
- gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
- gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
- gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
- gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
- gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
- gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
- gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common]
- #
- # SEC
- #
- #
- # PEI Phase modules
- #
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- MdeModulePkg/Core/Pei/PeiMain.inf
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- ArmPkg/Drivers/CpuPei/CpuPei.inf
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf- }
- #
- # DXE
- #
- MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf- }
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # Architectural Protocols
- #
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug.
- #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf- }
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>
CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf- }
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- #ACPI
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- # Usb Support
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- #
- #network
- #
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- NetworkPkg/TcpDxe/TcpDxe.inf
- NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- NetworkPkg/DnsDxe/DnsDxe.inf
- NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- NetworkPkg/HttpDxe/HttpDxe.inf
- NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Bds
- #
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+!ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #PCIe Support
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- # Memory test
- #
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.infNULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.infNULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.infNULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.infNULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.infNULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.infHandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.infPrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.infBcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf+!if $(NETWORK_IP6_ENABLE) == TRUE
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf+!endif
+!ifdef $(INCLUDE_DP)
NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf+!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND)
NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf+!endif #$(INCLUDE_TFTP_COMMAND)
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFFgEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSEgEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000- }
diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000..bdfb211 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -0,0 +1,366 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#
+[DEFINES]
+################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05]
+BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1
+# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30
+################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################
+0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
+0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT
+0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin +0x002A0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin
+0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = {
- ## This is the EFI_FIRMWARE_VOLUME_HEADER
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- # FileSystemGuid: gEfiSystemNvDataFvGuid =
- 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
- 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
- # FvLength: 0x20000
- 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- #Signature "_FVH" #Attributes
- 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
- #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
- 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
- #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
- #Blockmap[1]: End
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
- 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
- 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
- #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
- 0xB8, 0xdF, 0x00, 0x00,
- #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
- 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = {
- # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
- 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
- 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
- # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
- 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
- # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
- 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+0x002F0000|0x00010000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################
+[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI DXE {
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- }
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
- #
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- #
- # Multiple Console IO support
- #
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- INF FatBinPkg/EnhancedFatDxe/Fat.inf
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- # Usb Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
- INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- #ACPI
- #
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- #Network
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- INF NetworkPkg/TcpDxe/TcpDxe.inf
- INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- INF NetworkPkg/DnsDxe/DnsDxe.inf
- INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- INF NetworkPkg/HttpDxe/HttpDxe.inf
- INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
+!ifdef $(FDT_ENABLE)
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #
- # PCI Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
- INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- # VGA Driver
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Build Shell from latest source code instead of prebuilt binary
- #
- INF ShellPkg/Application/Shell/Shell.inf
- #
- # Bds
- #
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI PEI {
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- }
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- INF MdeModulePkg/Core/Pei/PeiMain.inf
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN- }
- }
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000..76a055c --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PiPei.h> +#include <PlatformArch.h> +#include <Uefi.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformSysCtrlLib.h>
+VOID +QResetAp (
- VOID
- )
+{
- MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
- (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
- StartupAp();
- }
+}
+EFI_STATUS +EFIAPI +EarlyConfigEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
+{
- DEBUG((DEBUG_INFO,"SMMU CONFIG........."));
- (VOID)SmmuConfigForBios();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"AP CONFIG........."));
- (VOID)QResetAp();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"MN CONFIG........."));
- (VOID)MN_CONFIG();
- DEBUG((DEBUG_INFO,"Done\n"));
- return EFI_SUCCESS;
+}
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000..5fdf555 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = EarlyConfigPeimD05
- FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = EarlyConfigEntry
+[Sources.common]
- EarlyConfigPeimD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- ArmLib
- CacheMaintenanceLib
- DebugLib
- IoLib
- PcdLib
- PeimEntryPoint
- PlatformSysCtrlLib
+[Pcd]
- gHisiTokenSpaceGuid.PcdMailBoxAddress
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[Depex] +## As we will clean mailbox in this module, need to wait memory init complete
- gEfiPeiMemoryDiscoveredPpiGuid
+[BuildOptions]
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000..473da0a --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,225 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h> +#include <IndustryStandard/SmBios.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HiiLib.h> +#include <Library/I2CLib.h> +#include <Library/IoLib.h> +#include <Library/OemMiscLib.h> +#include <Library/SerdesLib.h> +#include <Protocol/Smbios.h>
+I2C_DEVICE gDS3231RtcDevice = {
- .Socket = 0,
- .Port = 4,
- .DeviceType = DEVICE_TYPE_SPD,
- .SlaveDeviceAddress = 0x68
+};
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+serdes_param_t gSerdesParamNA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamNB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+EFI_STATUS +OemGetSerdesParam (
- OUT serdes_param_t *ParamA,
- OUT serdes_param_t *ParamB,
- IN UINT32 SocketId
- )
+{
- if (ParamA == NULL || ParamB == NULL) {
- DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
- return EFI_INVALID_PARAMETER;
- }
- if (SocketId == 0) {
- (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
- } else {
- (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
- }
- return EFI_SUCCESS;
+}
+VOID +OemPcieResetAndOffReset (
- VOID
- )
+{
- return;
+}
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
- // PCIe0 Slot 1
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0001, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- },
- // PCIe0 Slot 4
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0004, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- }
+};
+UINT8 +OemGetPcieSlotNumber (
- VOID
- )
+{
- return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+EFI_HII_HANDLE +EFIAPI +OemGetPackages (
- )
+{
- return HiiAddPackages (
&gEfiCallerIdGuid,NULL,OemMiscLibHi1616EvbStrings,NULL,NULL);+}
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/
+/=#
+#langdef en-US "English"
+// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"
+// +// DIMM Device Locator strings
+#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28"
+// +// End English Language Strings +//
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..b17eead --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h>
+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h>
+#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
- {67,0,0,0},
- {225,0,0,3},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+BOOLEAN OemIsSocketPresent (UINTN Socket) +{
- if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
- return TRUE;
- } else {
- return FALSE;
- }
+}
+UINTN OemGetSocketNumber (VOID) +{
- if(!OemIsMpBoot()) {
- return OEM_SINGLE_SOCKET;
- }
- return OEM_DUAL_SOCKET;
+}
+UINTN OemGetDdrChannel (VOID) +{
- return 4;
+}
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{
- return 2;
+}
+VOID CoreSelectBoot(VOID) +{
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
StartupAp ();- }
- return;
+}
+BOOLEAN OemIsMpBoot() +{
- return PcdGet32(PcdIsMPBoot);
+}
+VOID OemLpcInit(VOID) +{
- LpcInit();
- return;
+}
+UINT32 OemIsWarmBoot(VOID) +{
- return 0;
+}
+VOID OemBiosSwitch(UINT32 Master) +{
- (VOID)Master;
- return;
+}
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{
- return TRUE;
+} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = OemMiscLibHi1616Evb
- FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = OemMiscLib
+[Sources.common]
- BoardFeatureD05.c
- BoardFeatureD05Strings.uni
- OemMiscLibD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
- TimerLib
+[BuildOptions]
+[Ppis]
- gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES
+[Pcd]
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
- gHisiTokenSpaceGuid.PcdIsMPBoot
- gHisiTokenSpaceGuid.PcdSocketMask
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[FixedPcd.common]
+[Guids]
+[Protocols]
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h>
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
{0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
{0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
{0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
{0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
- {// HostBridge 0
- /* Port 0 */
- {
PCI_HB0RB0_ECAM_BASE, //ecam0x80, //BusBase0x87, //BusLimitPCI_HB0RB0_PCIREGION_BASE, //MembasePCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB0_PCI_BASE),//RbPciBarPCI_HB0RB0_PCIREGION_BASE, //PciRegionbasePCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB0RB1_ECAM_BASE,//ecam0x90, //BusBase0x97, //BusLimitPCI_HB0RB1_PCIREGION_BASE, //MembasePCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB1_IO_BASE), //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimitPCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB1_PCI_BASE), //RbPciBarPCI_HB0RB1_PCIREGION_BASE, //PciRegionbasePCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB0RB2_ECAM_BASE,0x80, //BusBase0x87, //BusLimitPCI_HB0RB2_CPUMEMREGIONBASE ,//MemBasePCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB2_IO_BASE), //IOBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimitPCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB2_PCI_BASE), //RbPciBarPCI_HB0RB2_PCIREGION_BASE, //PciRegionbasePCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB0RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB0RB3_ECAM_BASE), //MemBase(PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit(PCI_HB0RB3_IO_BASE), //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimitPCI_HB0RB3_CPUMEMREGIONBASE,PCI_HB0RB3_CPUIOREGIONBASE,(PCI_HB0RB3_PCI_BASE), //RbPciBarPCI_HB0RB3_PCIREGION_BASE, //PciRegionbasePCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB0RB4_ECAM_BASE, //ecam0x88, //BusBase0x8f, //BusLimitPCI_HB0RB4_CPUMEMREGIONBASE, //MembasePCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimitPCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB4_PCI_BASE), //RbPciBarPCI_HB0RB4_PCIREGION_BASE, //PciRegionbasePCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB0RB5_ECAM_BASE,//ecam0x0, //BusBase0x7, //BusLimitPCI_HB0RB5_CPUMEMREGIONBASE, //MembasePCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB5_IO_BASE), //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimitPCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB5_PCI_BASE), //RbPciBarPCI_HB0RB5_PCIREGION_BASE, //PciRegionbasePCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB0RB6_ECAM_BASE,0xC0, //BusBase0xC7, //BusLimitPCI_HB0RB6_PCIREGION_BASE ,//MemBasePCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB6_IO_BASE), //IOBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimitPCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB6_PCI_BASE), //RbPciBarPCI_HB0RB6_PCIREGION_BASE, //PciRegionbasePCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB0RB7_ECAM_BASE,0x90, //BusBase0x97, //BusLimitPCI_HB0RB7_CPUMEMREGIONBASE, //MemBasePCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB7_IO_BASE), //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimitPCI_HB0RB7_CPUMEMREGIONBASE,PCI_HB0RB7_CPUIOREGIONBASE,(PCI_HB0RB7_PCI_BASE), //RbPciBarPCI_HB0RB7_PCIREGION_BASE, //PciRegionbasePCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- },
+{// HostBridge 1
- /* Port 0 */
- {
PCI_HB1RB0_ECAM_BASE,0x80, //BusBase0x87, //BusLimit(PCI_HB1RB0_ECAM_BASE), //MemBase(PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB0_PCI_BASE), //RbPciBarPCI_HB1RB0_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB1RB1_ECAM_BASE,0x90, //BusBase0x97, //BusLimit(PCI_HB1RB1_ECAM_BASE), //MemBase(PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB1_IO_BASE, //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB1_PCI_BASE), //RbPciBarPCI_HB1RB1_PCIREGION_BASE, //PciRegionbasePCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB1RB2_ECAM_BASE,0x10, //BusBase0x1f, //BusLimitPCI_HB1RB2_CPUMEMREGIONBASE, //MemBasePCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB2_IO_BASE, //IoBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB2_PCI_BASE), //RbPciBarPCI_HB1RB2_PCIREGION_BASE, //PciRegionbasePCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB1RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB1RB3_ECAM_BASE), //MemBase(PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB3_IO_BASE, //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB3_PCI_BASE), //RbPciBarPCI_HB1RB3_PCIREGION_BASE, //PciRegionbasePCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB1RB4_ECAM_BASE,0x20, //BusBase0x2f, //BusLimitPCI_HB1RB4_CPUMEMREGIONBASE, //MemBasePCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB4_PCI_BASE), //RbPciBarPCI_HB1RB4_PCIREGION_BASE, //PciRegionbasePCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB1RB5_ECAM_BASE,0x30, //BusBase0x3f, //BusLimitPCI_HB1RB5_CPUMEMREGIONBASE, //MemBasePCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB5_IO_BASE, //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB5_PCI_BASE), //RbPciBarPCI_HB1RB5_PCIREGION_BASE, //PciRegionbasePCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB1RB6_ECAM_BASE,0xa8, //BusBase0xaf, //BusLimit(PCI_HB1RB6_ECAM_BASE), //MemBasePCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB6_IO_BASE, //IoBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB6_PCI_BASE), //RbPciBarPCI_HB1RB6_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB1RB7_ECAM_BASE,0xb8, //BusBase0xbf, //BusLimit(PCI_HB1RB7_ECAM_BASE), //MemBasePCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB7_IO_BASE, //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB7_PCI_BASE), //RbPciBarPCI_HB1RB7_PCIREGION_BASE, //PciRegionbasePCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- }
+};
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = PlatformPciLib
- FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
+[Sources]
- PlatformPciLib.c
+[Packages]
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdHb1BaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PciHb0Rb0Base
- gHisiTokenSpaceGuid.PciHb0Rb1Base
- gHisiTokenSpaceGuid.PciHb0Rb2Base
- gHisiTokenSpaceGuid.PciHb0Rb3Base
- gHisiTokenSpaceGuid.PciHb0Rb4Base
- gHisiTokenSpaceGuid.PciHb0Rb5Base
- gHisiTokenSpaceGuid.PciHb0Rb6Base
- gHisiTokenSpaceGuid.PciHb0Rb7Base
- gHisiTokenSpaceGuid.PciHb1Rb0Base
- gHisiTokenSpaceGuid.PciHb1Rb1Base
- gHisiTokenSpaceGuid.PciHb1Rb2Base
- gHisiTokenSpaceGuid.PciHb1Rb3Base
- gHisiTokenSpaceGuid.PciHb1Rb4Base
- gHisiTokenSpaceGuid.PciHb1Rb5Base
- gHisiTokenSpaceGuid.PciHb1Rb6Base
- gHisiTokenSpaceGuid.PciHb1Rb7Base
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
-- 1.9.1
Hi Heyi,
On Tue, Dec 06, 2016 at 09:29:02PM +0800, Heyi Guo wrote:
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h new file mode 100644 index 0000000..941bb04 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -0,0 +1,71 @@ +#ifndef _SERDES_LIB_H_ +#define _SERDES_LIB_H_
+typedef enum hilink0_mode_type {
- EM_HILINK0_HCCS1_8LANE = 0,
- EM_HILINK0_PCIE1_8LANE = 2,
- EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3,
- EM_HILINK0_SAS2_8LANE = 4,
- EM_HILINK0_HCCS1_8LANE_16,
- EM_HILINK0_HCCS1_8LANE_32,
- EM_HILINK0_HCCS1_8LANE_5000,
+} hilink0_mode_type_e;
+typedef enum hilink1_mode_type {
- EM_HILINK1_SAS2_1LANE = 0,
- EM_HILINK1_HCCS0_8LANE = 1,
- EM_HILINK1_PCIE0_8LANE = 2,
- EM_HILINK1_HCCS0_8LANE_16,
- EM_HILINK1_HCCS0_8LANE_32,
- EM_HILINK1_HCCS0_8LANE_5000,
+} hilink1_mode_type_e;
+typedef enum hilink2_mode_type {
- EM_HILINK2_PCIE2_8LANE = 0,
- EM_HILINK2_HCCS2_8LANE = 1,
- EM_HILINK2_SAS0_8LANE = 2,
- EM_HILINK2_HCCS2_8LANE_16,
- EM_HILINK2_HCCS2_8LANE_32,
- EM_HILINK2_HCCS2_8LANE_5000,
+} hilink2_mode_type_e;
+typedef enum hilink5_mode_type {
- EM_HILINK5_PCIE3_4LANE = 0,
- EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1,
- EM_HILINK5_SAS1_4LANE = 2,
+} hilink5_mode_type_e;
+typedef struct serdes_param {
- hilink0_mode_type_e hilink0_mode;
- hilink1_mode_type_e hilink1_mode;
- hilink2_mode_type_e hilink2_mode;
- UINT32 hilink3_mode;
- UINT32 hilink4_mode;
- hilink5_mode_type_e hilink5_mode;
- UINT32 hilink6_mode;
- UINT32 use_ssc;
+} serdes_param_t;
So, you have fixed the indentation here, but not the rest of my comments.
None of these typedefs conform to coding style. They should start like
typedef struct {
Contain CamelCase members.
and end like
} SERDES_PARAM;
Please correct all of the structs in this file, not just the local one.
(Although there was an error in my comment - no need to name the struct, we just need the typedef. So this particular struct should look like
typedef struct { HiLink0ModeType HiLink0Mode; ... } SERDES_PARAM;
.)
Thanks for point out this. The member of Hilink0ModeType comes from the enum above:
typedef enum hilink0_mode_type { EM_HILINK0_HCCS1_8LANE = 0, EM_HILINK0_PCIE1_8LANE = 2, EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3, EM_HILINK0_SAS2_8LANE = 4, EM_HILINK0_HCCS1_8LANE_16, EM_HILINK0_HCCS1_8LANE_32, EM_HILINK0_HCCS1_8LANE_5000, } hilink0_mode_type_e;
So should i correct the enum to:
typedef enum { EmHilink0Hccs1_8Lane = 0, EmHilink0Pcie1_8Lane = 2, ..., } Hilink0ModeType;
or
typedef enum { EmHilink0Hccs1_8Lane = 0, EmHilink0Pcie1_8Lane = 2, ..., } HILINK0_MODE_TYPE;
Good point, clearly I was typing that with my brain disabled.
HILINK0_MODE_TYPE would match the style used in EDK2.
Thanks!
Regards,
Leif
?
Thanks and Regards, Heyi
The rest of this patch (apart from the bits that will need to change to adapt to the above) is now fine.
Please fix and resubmit this patch only.
Regards,
Leif
+#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF
+typedef struct {
- UINT32 MacroId;
- UINT32 DsNum;
- UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; +UINT32 GetEthType(UINT8 EthChannel); +VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode);
+EFI_STATUS +EfiSerdesInitWrap (VOID); +INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); +VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
+#endif diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 0faa100..2c02e14 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -104,7 +104,10 @@ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
- gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
- gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
- gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000..edaad18 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -0,0 +1,674 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#
+################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines]
- PLATFORM_NAME = D05
- PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x00010019
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64
- BUILD_TARGETS = DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
- DEFINE EDK2_SKIP_PEICORE=0
- DEFINE INCLUDE_TFTP_COMMAND=1
- DEFINE NETWORK_IP6_ENABLE = FALSE
- DEFINE HTTP_BOOT_ENABLE = FALSE
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+[LibraryClasses.common]
- ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
- BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+!endif
+!if $(HTTP_BOOT_ENABLE) == TRUE
- HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+!ifdef $(FDT_ENABLE)
- #FDTUpdateLib
- FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
- CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
- SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
- EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
- #D05 RTC hardware is same as D03
- RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
- OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
- OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
- PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
- PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
- # USB Requirements
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
- LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[LibraryClasses.common.SEC]
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[BuildOptions]
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include
+################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################
+[PcdsFeatureFlag.common]
+!if $(EDK2_SKIP_PEICORE) == 1
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
- # It could be set FALSE to save size.
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
- gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+[PcdsFixedAtBuild.common]
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"
- gArmPlatformTokenSpaceGuid.PcdCoreCount|8
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- # Stacks for MPCores in Secure World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
- # Stacks for MPCores in Monitor Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
- # Stacks for MPCores in Normal World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
- gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
- #
- # ARM Pcds
- #
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
- gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- ## SP805 Watchdog - Motherboard Watchdog
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
- ## Serial Terminal
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
- # use the TTY terminal type (which has a working backspace)
- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
- gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
- gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
- gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
- gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gHisiTokenSpaceGuid.PcdIsMPBoot|1
- gHisiTokenSpaceGuid.PcdSocketMask|0x3
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1"
- gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
- gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
- gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
- gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
- #
- # ARM Architectual Timer Frequency
- #
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
- gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
- gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
- gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
- gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
- gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
- gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
- gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
- ## DTB address at spi flash
- gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000
- gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
- gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
- gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
- gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
- gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
- gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
- gHisiTokenSpaceGuid.PcdNumaEnable|1
- gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
- gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
- gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
- gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
- gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
- gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
- gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
- gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
- gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
- gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
- gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
- gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
- gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common]
- #
- # SEC
- #
- #
- # PEI Phase modules
- #
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- MdeModulePkg/Core/Pei/PeiMain.inf
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- ArmPkg/Drivers/CpuPei/CpuPei.inf
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf- }
- #
- # DXE
- #
- MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf- }
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # Architectural Protocols
- #
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug.
- #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf- }
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>
CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf- }
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- #ACPI
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- # Usb Support
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- #
- #network
- #
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- NetworkPkg/TcpDxe/TcpDxe.inf
- NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- NetworkPkg/DnsDxe/DnsDxe.inf
- NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- NetworkPkg/HttpDxe/HttpDxe.inf
- NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Bds
- #
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+!ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #PCIe Support
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- # Memory test
- #
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.infNULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.infNULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.infNULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.infNULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.infNULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.infHandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.infPrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.infBcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf+!if $(NETWORK_IP6_ENABLE) == TRUE
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf+!endif
+!ifdef $(INCLUDE_DP)
NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf+!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND)
NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf+!endif #$(INCLUDE_TFTP_COMMAND)
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFFgEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSEgEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000- }
diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000..bdfb211 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -0,0 +1,366 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#
+[DEFINES]
+################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05]
+BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1
+# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30
+################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################
+0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
+0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT
+0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin +0x002A0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin
+0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = {
- ## This is the EFI_FIRMWARE_VOLUME_HEADER
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- # FileSystemGuid: gEfiSystemNvDataFvGuid =
- 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
- 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
- # FvLength: 0x20000
- 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- #Signature "_FVH" #Attributes
- 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
- #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
- 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
- #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
- #Blockmap[1]: End
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
- 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
- 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
- #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
- 0xB8, 0xdF, 0x00, 0x00,
- #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
- 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = {
- # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
- 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
- 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
- # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
- 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
- # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
- 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+0x002F0000|0x00010000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################
+[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI DXE {
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- }
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
- #
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- #
- # Multiple Console IO support
- #
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- INF FatBinPkg/EnhancedFatDxe/Fat.inf
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- # Usb Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
- INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- #ACPI
- #
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- #Network
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- INF NetworkPkg/TcpDxe/TcpDxe.inf
- INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- INF NetworkPkg/DnsDxe/DnsDxe.inf
- INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- INF NetworkPkg/HttpDxe/HttpDxe.inf
- INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
+!ifdef $(FDT_ENABLE)
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #
- # PCI Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
- INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- # VGA Driver
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Build Shell from latest source code instead of prebuilt binary
- #
- INF ShellPkg/Application/Shell/Shell.inf
- #
- # Bds
- #
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI PEI {
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- }
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- INF MdeModulePkg/Core/Pei/PeiMain.inf
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN- }
- }
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000..76a055c --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PiPei.h> +#include <PlatformArch.h> +#include <Uefi.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformSysCtrlLib.h>
+VOID +QResetAp (
- VOID
- )
+{
- MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
- (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
- StartupAp();
- }
+}
+EFI_STATUS +EFIAPI +EarlyConfigEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
+{
- DEBUG((DEBUG_INFO,"SMMU CONFIG........."));
- (VOID)SmmuConfigForBios();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"AP CONFIG........."));
- (VOID)QResetAp();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"MN CONFIG........."));
- (VOID)MN_CONFIG();
- DEBUG((DEBUG_INFO,"Done\n"));
- return EFI_SUCCESS;
+}
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000..5fdf555 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = EarlyConfigPeimD05
- FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = EarlyConfigEntry
+[Sources.common]
- EarlyConfigPeimD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- ArmLib
- CacheMaintenanceLib
- DebugLib
- IoLib
- PcdLib
- PeimEntryPoint
- PlatformSysCtrlLib
+[Pcd]
- gHisiTokenSpaceGuid.PcdMailBoxAddress
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[Depex] +## As we will clean mailbox in this module, need to wait memory init complete
- gEfiPeiMemoryDiscoveredPpiGuid
+[BuildOptions]
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000..473da0a --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,225 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h> +#include <IndustryStandard/SmBios.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HiiLib.h> +#include <Library/I2CLib.h> +#include <Library/IoLib.h> +#include <Library/OemMiscLib.h> +#include <Library/SerdesLib.h> +#include <Protocol/Smbios.h>
+I2C_DEVICE gDS3231RtcDevice = {
- .Socket = 0,
- .Port = 4,
- .DeviceType = DEVICE_TYPE_SPD,
- .SlaveDeviceAddress = 0x68
+};
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+serdes_param_t gSerdesParamNA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamNB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+EFI_STATUS +OemGetSerdesParam (
- OUT serdes_param_t *ParamA,
- OUT serdes_param_t *ParamB,
- IN UINT32 SocketId
- )
+{
- if (ParamA == NULL || ParamB == NULL) {
- DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
- return EFI_INVALID_PARAMETER;
- }
- if (SocketId == 0) {
- (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
- } else {
- (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
- }
- return EFI_SUCCESS;
+}
+VOID +OemPcieResetAndOffReset (
- VOID
- )
+{
- return;
+}
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
- // PCIe0 Slot 1
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0001, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- },
- // PCIe0 Slot 4
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0004, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- }
+};
+UINT8 +OemGetPcieSlotNumber (
- VOID
- )
+{
- return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+EFI_HII_HANDLE +EFIAPI +OemGetPackages (
- )
+{
- return HiiAddPackages (
&gEfiCallerIdGuid,NULL,OemMiscLibHi1616EvbStrings,NULL,NULL);+}
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/
+/=#
+#langdef en-US "English"
+// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"
+// +// DIMM Device Locator strings
+#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28"
+// +// End English Language Strings +//
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..b17eead --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h>
+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h>
+#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
- {67,0,0,0},
- {225,0,0,3},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+BOOLEAN OemIsSocketPresent (UINTN Socket) +{
- if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
- return TRUE;
- } else {
- return FALSE;
- }
+}
+UINTN OemGetSocketNumber (VOID) +{
- if(!OemIsMpBoot()) {
- return OEM_SINGLE_SOCKET;
- }
- return OEM_DUAL_SOCKET;
+}
+UINTN OemGetDdrChannel (VOID) +{
- return 4;
+}
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{
- return 2;
+}
+VOID CoreSelectBoot(VOID) +{
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
StartupAp ();- }
- return;
+}
+BOOLEAN OemIsMpBoot() +{
- return PcdGet32(PcdIsMPBoot);
+}
+VOID OemLpcInit(VOID) +{
- LpcInit();
- return;
+}
+UINT32 OemIsWarmBoot(VOID) +{
- return 0;
+}
+VOID OemBiosSwitch(UINT32 Master) +{
- (VOID)Master;
- return;
+}
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{
- return TRUE;
+} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = OemMiscLibHi1616Evb
- FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = OemMiscLib
+[Sources.common]
- BoardFeatureD05.c
- BoardFeatureD05Strings.uni
- OemMiscLibD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
- TimerLib
+[BuildOptions]
+[Ppis]
- gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES
+[Pcd]
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
- gHisiTokenSpaceGuid.PcdIsMPBoot
- gHisiTokenSpaceGuid.PcdSocketMask
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[FixedPcd.common]
+[Guids]
+[Protocols]
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h>
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
{0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
{0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
{0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
{0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
- {// HostBridge 0
- /* Port 0 */
- {
PCI_HB0RB0_ECAM_BASE, //ecam0x80, //BusBase0x87, //BusLimitPCI_HB0RB0_PCIREGION_BASE, //MembasePCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB0_PCI_BASE),//RbPciBarPCI_HB0RB0_PCIREGION_BASE, //PciRegionbasePCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB0RB1_ECAM_BASE,//ecam0x90, //BusBase0x97, //BusLimitPCI_HB0RB1_PCIREGION_BASE, //MembasePCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB1_IO_BASE), //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimitPCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB1_PCI_BASE), //RbPciBarPCI_HB0RB1_PCIREGION_BASE, //PciRegionbasePCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB0RB2_ECAM_BASE,0x80, //BusBase0x87, //BusLimitPCI_HB0RB2_CPUMEMREGIONBASE ,//MemBasePCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB2_IO_BASE), //IOBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimitPCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB2_PCI_BASE), //RbPciBarPCI_HB0RB2_PCIREGION_BASE, //PciRegionbasePCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB0RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB0RB3_ECAM_BASE), //MemBase(PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit(PCI_HB0RB3_IO_BASE), //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimitPCI_HB0RB3_CPUMEMREGIONBASE,PCI_HB0RB3_CPUIOREGIONBASE,(PCI_HB0RB3_PCI_BASE), //RbPciBarPCI_HB0RB3_PCIREGION_BASE, //PciRegionbasePCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB0RB4_ECAM_BASE, //ecam0x88, //BusBase0x8f, //BusLimitPCI_HB0RB4_CPUMEMREGIONBASE, //MembasePCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimitPCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB4_PCI_BASE), //RbPciBarPCI_HB0RB4_PCIREGION_BASE, //PciRegionbasePCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB0RB5_ECAM_BASE,//ecam0x0, //BusBase0x7, //BusLimitPCI_HB0RB5_CPUMEMREGIONBASE, //MembasePCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB5_IO_BASE), //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimitPCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB5_PCI_BASE), //RbPciBarPCI_HB0RB5_PCIREGION_BASE, //PciRegionbasePCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB0RB6_ECAM_BASE,0xC0, //BusBase0xC7, //BusLimitPCI_HB0RB6_PCIREGION_BASE ,//MemBasePCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB6_IO_BASE), //IOBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimitPCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB6_PCI_BASE), //RbPciBarPCI_HB0RB6_PCIREGION_BASE, //PciRegionbasePCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB0RB7_ECAM_BASE,0x90, //BusBase0x97, //BusLimitPCI_HB0RB7_CPUMEMREGIONBASE, //MemBasePCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB7_IO_BASE), //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimitPCI_HB0RB7_CPUMEMREGIONBASE,PCI_HB0RB7_CPUIOREGIONBASE,(PCI_HB0RB7_PCI_BASE), //RbPciBarPCI_HB0RB7_PCIREGION_BASE, //PciRegionbasePCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- },
+{// HostBridge 1
- /* Port 0 */
- {
PCI_HB1RB0_ECAM_BASE,0x80, //BusBase0x87, //BusLimit(PCI_HB1RB0_ECAM_BASE), //MemBase(PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB0_PCI_BASE), //RbPciBarPCI_HB1RB0_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB1RB1_ECAM_BASE,0x90, //BusBase0x97, //BusLimit(PCI_HB1RB1_ECAM_BASE), //MemBase(PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB1_IO_BASE, //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB1_PCI_BASE), //RbPciBarPCI_HB1RB1_PCIREGION_BASE, //PciRegionbasePCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB1RB2_ECAM_BASE,0x10, //BusBase0x1f, //BusLimitPCI_HB1RB2_CPUMEMREGIONBASE, //MemBasePCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB2_IO_BASE, //IoBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB2_PCI_BASE), //RbPciBarPCI_HB1RB2_PCIREGION_BASE, //PciRegionbasePCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB1RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB1RB3_ECAM_BASE), //MemBase(PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB3_IO_BASE, //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB3_PCI_BASE), //RbPciBarPCI_HB1RB3_PCIREGION_BASE, //PciRegionbasePCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB1RB4_ECAM_BASE,0x20, //BusBase0x2f, //BusLimitPCI_HB1RB4_CPUMEMREGIONBASE, //MemBasePCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB4_PCI_BASE), //RbPciBarPCI_HB1RB4_PCIREGION_BASE, //PciRegionbasePCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB1RB5_ECAM_BASE,0x30, //BusBase0x3f, //BusLimitPCI_HB1RB5_CPUMEMREGIONBASE, //MemBasePCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB5_IO_BASE, //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB5_PCI_BASE), //RbPciBarPCI_HB1RB5_PCIREGION_BASE, //PciRegionbasePCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB1RB6_ECAM_BASE,0xa8, //BusBase0xaf, //BusLimit(PCI_HB1RB6_ECAM_BASE), //MemBasePCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB6_IO_BASE, //IoBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB6_PCI_BASE), //RbPciBarPCI_HB1RB6_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB1RB7_ECAM_BASE,0xb8, //BusBase0xbf, //BusLimit(PCI_HB1RB7_ECAM_BASE), //MemBasePCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB7_IO_BASE, //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB7_PCI_BASE), //RbPciBarPCI_HB1RB7_PCIREGION_BASE, //PciRegionbasePCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- }
+};
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = PlatformPciLib
- FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
+[Sources]
- PlatformPciLib.c
+[Packages]
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdHb1BaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PciHb0Rb0Base
- gHisiTokenSpaceGuid.PciHb0Rb1Base
- gHisiTokenSpaceGuid.PciHb0Rb2Base
- gHisiTokenSpaceGuid.PciHb0Rb3Base
- gHisiTokenSpaceGuid.PciHb0Rb4Base
- gHisiTokenSpaceGuid.PciHb0Rb5Base
- gHisiTokenSpaceGuid.PciHb0Rb6Base
- gHisiTokenSpaceGuid.PciHb0Rb7Base
- gHisiTokenSpaceGuid.PciHb1Rb0Base
- gHisiTokenSpaceGuid.PciHb1Rb1Base
- gHisiTokenSpaceGuid.PciHb1Rb2Base
- gHisiTokenSpaceGuid.PciHb1Rb3Base
- gHisiTokenSpaceGuid.PciHb1Rb4Base
- gHisiTokenSpaceGuid.PciHb1Rb5Base
- gHisiTokenSpaceGuid.PciHb1Rb6Base
- gHisiTokenSpaceGuid.PciHb1Rb7Base
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
-- 1.9.1
Hi Leif,
在 12/6/2016 9:42 PM, Leif Lindholm 写道:
Hi Heyi,
On Tue, Dec 06, 2016 at 09:29:02PM +0800, Heyi Guo wrote:
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h new file mode 100644 index 0000000..941bb04 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -0,0 +1,71 @@ +#ifndef _SERDES_LIB_H_ +#define _SERDES_LIB_H_
+typedef enum hilink0_mode_type {
- EM_HILINK0_HCCS1_8LANE = 0,
- EM_HILINK0_PCIE1_8LANE = 2,
- EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3,
- EM_HILINK0_SAS2_8LANE = 4,
- EM_HILINK0_HCCS1_8LANE_16,
- EM_HILINK0_HCCS1_8LANE_32,
- EM_HILINK0_HCCS1_8LANE_5000,
+} hilink0_mode_type_e;
+typedef enum hilink1_mode_type {
- EM_HILINK1_SAS2_1LANE = 0,
- EM_HILINK1_HCCS0_8LANE = 1,
- EM_HILINK1_PCIE0_8LANE = 2,
- EM_HILINK1_HCCS0_8LANE_16,
- EM_HILINK1_HCCS0_8LANE_32,
- EM_HILINK1_HCCS0_8LANE_5000,
+} hilink1_mode_type_e;
+typedef enum hilink2_mode_type {
- EM_HILINK2_PCIE2_8LANE = 0,
- EM_HILINK2_HCCS2_8LANE = 1,
- EM_HILINK2_SAS0_8LANE = 2,
- EM_HILINK2_HCCS2_8LANE_16,
- EM_HILINK2_HCCS2_8LANE_32,
- EM_HILINK2_HCCS2_8LANE_5000,
+} hilink2_mode_type_e;
+typedef enum hilink5_mode_type {
- EM_HILINK5_PCIE3_4LANE = 0,
- EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1,
- EM_HILINK5_SAS1_4LANE = 2,
+} hilink5_mode_type_e;
+typedef struct serdes_param {
- hilink0_mode_type_e hilink0_mode;
- hilink1_mode_type_e hilink1_mode;
- hilink2_mode_type_e hilink2_mode;
- UINT32 hilink3_mode;
- UINT32 hilink4_mode;
- hilink5_mode_type_e hilink5_mode;
- UINT32 hilink6_mode;
- UINT32 use_ssc;
+} serdes_param_t;
So, you have fixed the indentation here, but not the rest of my comments.
None of these typedefs conform to coding style. They should start like
typedef struct {
Contain CamelCase members.
and end like
} SERDES_PARAM;
Please correct all of the structs in this file, not just the local one.
(Although there was an error in my comment - no need to name the struct, we just need the typedef. So this particular struct should look like
typedef struct { HiLink0ModeType HiLink0Mode; ... } SERDES_PARAM;
.)
Thanks for point out this. The member of Hilink0ModeType comes from the enum above:
typedef enum hilink0_mode_type { EM_HILINK0_HCCS1_8LANE = 0, EM_HILINK0_PCIE1_8LANE = 2, EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3, EM_HILINK0_SAS2_8LANE = 4, EM_HILINK0_HCCS1_8LANE_16, EM_HILINK0_HCCS1_8LANE_32, EM_HILINK0_HCCS1_8LANE_5000, } hilink0_mode_type_e;
So should i correct the enum to:
typedef enum { EmHilink0Hccs1_8Lane = 0, EmHilink0Pcie1_8Lane = 2, ..., } Hilink0ModeType;
or
typedef enum { EmHilink0Hccs1_8Lane = 0, EmHilink0Pcie1_8Lane = 2, ..., } HILINK0_MODE_TYPE;
Good point, clearly I was typing that with my brain disabled.
HILINK0_MODE_TYPE would match the style used in EDK2.
Thanks!
Regards,
Leif
?
Thanks and Regards, Heyi
The rest of this patch (apart from the bits that will need to change to adapt to the above) is now fine.
Please fix and resubmit this patch only.
After fix the coding style of structure, we also need to modify the function UpdateSlotUsage() which will use the SERDES_PARAM and its members. If I modify the UpdateSlotUsage(), I have to modify D02 and D03 boardfeature.c file. Because this function is platform function. So I make another 3 patches. I will sent out the 4 patches, is that ok?
Thanks and Regards, Heyi
Regards,
Leif
+#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF
+typedef struct {
- UINT32 MacroId;
- UINT32 DsNum;
- UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; +UINT32 GetEthType(UINT8 EthChannel); +VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode);
+EFI_STATUS +EfiSerdesInitWrap (VOID); +INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); +VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
+#endif diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 0faa100..2c02e14 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -104,7 +104,10 @@ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
- gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
- gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
- gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000..edaad18 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -0,0 +1,674 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#
+################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines]
- PLATFORM_NAME = D05
- PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x00010019
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64
- BUILD_TARGETS = DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
- DEFINE EDK2_SKIP_PEICORE=0
- DEFINE INCLUDE_TFTP_COMMAND=1
- DEFINE NETWORK_IP6_ENABLE = FALSE
- DEFINE HTTP_BOOT_ENABLE = FALSE
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+[LibraryClasses.common]
- ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
- BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+!endif
+!if $(HTTP_BOOT_ENABLE) == TRUE
- HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+!ifdef $(FDT_ENABLE)
- #FDTUpdateLib
- FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
- CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
- SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
- EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
- #D05 RTC hardware is same as D03
- RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
- OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
- OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
- PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
- PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
- # USB Requirements
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
- LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[LibraryClasses.common.SEC]
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[BuildOptions]
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include
+################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################
+[PcdsFeatureFlag.common]
+!if $(EDK2_SKIP_PEICORE) == 1
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
- # It could be set FALSE to save size.
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
- gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+[PcdsFixedAtBuild.common]
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"
- gArmPlatformTokenSpaceGuid.PcdCoreCount|8
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- # Stacks for MPCores in Secure World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
- # Stacks for MPCores in Monitor Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
- # Stacks for MPCores in Normal World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
- gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
- #
- # ARM Pcds
- #
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
- gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- ## SP805 Watchdog - Motherboard Watchdog
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
- ## Serial Terminal
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
- # use the TTY terminal type (which has a working backspace)
- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
- gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
- gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
- gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
- gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gHisiTokenSpaceGuid.PcdIsMPBoot|1
- gHisiTokenSpaceGuid.PcdSocketMask|0x3
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1"
- gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
- gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
- gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
- gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
- #
- # ARM Architectual Timer Frequency
- #
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
- gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
- gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
- gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
- gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
- gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
- gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
- gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
- ## DTB address at spi flash
- gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000
- gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
- gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
- gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
- gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
- gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
- gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
- gHisiTokenSpaceGuid.PcdNumaEnable|1
- gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
- gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
- gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
- gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
- gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
- gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
- gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
- gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
- gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
- gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
- gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
- gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
- gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common]
- #
- # SEC
- #
- #
- # PEI Phase modules
- #
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- MdeModulePkg/Core/Pei/PeiMain.inf
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- ArmPkg/Drivers/CpuPei/CpuPei.inf
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf- }
- #
- # DXE
- #
- MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf- }
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # Architectural Protocols
- #
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug.
- #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf- }
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>
CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf- }
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- #ACPI
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- # Usb Support
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- #
- #network
- #
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- NetworkPkg/TcpDxe/TcpDxe.inf
- NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- NetworkPkg/DnsDxe/DnsDxe.inf
- NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- NetworkPkg/HttpDxe/HttpDxe.inf
- NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Bds
- #
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+!ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #PCIe Support
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- # Memory test
- #
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.infNULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.infNULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.infNULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.infNULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.infNULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.infHandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.infPrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.infBcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf+!if $(NETWORK_IP6_ENABLE) == TRUE
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf+!endif
+!ifdef $(INCLUDE_DP)
NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf+!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND)
NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf+!endif #$(INCLUDE_TFTP_COMMAND)
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFFgEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSEgEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000- }
diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000..bdfb211 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -0,0 +1,366 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#
+[DEFINES]
+################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05]
+BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1
+# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30
+################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################
+0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
+0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT
+0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin +0x002A0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin
+0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = {
- ## This is the EFI_FIRMWARE_VOLUME_HEADER
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- # FileSystemGuid: gEfiSystemNvDataFvGuid =
- 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
- 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
- # FvLength: 0x20000
- 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- #Signature "_FVH" #Attributes
- 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
- #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
- 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
- #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
- #Blockmap[1]: End
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
- 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
- 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
- #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
- 0xB8, 0xdF, 0x00, 0x00,
- #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
- 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = {
- # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
- 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
- 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
- # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
- 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
- # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
- 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+0x002F0000|0x00010000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################
+[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI DXE {
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- }
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
- #
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- #
- # Multiple Console IO support
- #
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- INF FatBinPkg/EnhancedFatDxe/Fat.inf
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- # Usb Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
- INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- #ACPI
- #
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- #Network
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- INF NetworkPkg/TcpDxe/TcpDxe.inf
- INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- INF NetworkPkg/DnsDxe/DnsDxe.inf
- INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- INF NetworkPkg/HttpDxe/HttpDxe.inf
- INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
+!ifdef $(FDT_ENABLE)
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #
- # PCI Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
- INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- # VGA Driver
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Build Shell from latest source code instead of prebuilt binary
- #
- INF ShellPkg/Application/Shell/Shell.inf
- #
- # Bds
- #
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI PEI {
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- }
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- INF MdeModulePkg/Core/Pei/PeiMain.inf
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN- }
- }
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000..76a055c --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PiPei.h> +#include <PlatformArch.h> +#include <Uefi.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformSysCtrlLib.h>
+VOID +QResetAp (
- VOID
- )
+{
- MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
- (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
- StartupAp();
- }
+}
+EFI_STATUS +EFIAPI +EarlyConfigEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
+{
- DEBUG((DEBUG_INFO,"SMMU CONFIG........."));
- (VOID)SmmuConfigForBios();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"AP CONFIG........."));
- (VOID)QResetAp();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"MN CONFIG........."));
- (VOID)MN_CONFIG();
- DEBUG((DEBUG_INFO,"Done\n"));
- return EFI_SUCCESS;
+}
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000..5fdf555 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = EarlyConfigPeimD05
- FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = EarlyConfigEntry
+[Sources.common]
- EarlyConfigPeimD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- ArmLib
- CacheMaintenanceLib
- DebugLib
- IoLib
- PcdLib
- PeimEntryPoint
- PlatformSysCtrlLib
+[Pcd]
- gHisiTokenSpaceGuid.PcdMailBoxAddress
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[Depex] +## As we will clean mailbox in this module, need to wait memory init complete
- gEfiPeiMemoryDiscoveredPpiGuid
+[BuildOptions]
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000..473da0a --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,225 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h> +#include <IndustryStandard/SmBios.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HiiLib.h> +#include <Library/I2CLib.h> +#include <Library/IoLib.h> +#include <Library/OemMiscLib.h> +#include <Library/SerdesLib.h> +#include <Protocol/Smbios.h>
+I2C_DEVICE gDS3231RtcDevice = {
- .Socket = 0,
- .Port = 4,
- .DeviceType = DEVICE_TYPE_SPD,
- .SlaveDeviceAddress = 0x68
+};
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+serdes_param_t gSerdesParamNA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamNB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+EFI_STATUS +OemGetSerdesParam (
- OUT serdes_param_t *ParamA,
- OUT serdes_param_t *ParamB,
- IN UINT32 SocketId
- )
+{
- if (ParamA == NULL || ParamB == NULL) {
- DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
- return EFI_INVALID_PARAMETER;
- }
- if (SocketId == 0) {
- (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
- } else {
- (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
- }
- return EFI_SUCCESS;
+}
+VOID +OemPcieResetAndOffReset (
- VOID
- )
+{
- return;
+}
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
- // PCIe0 Slot 1
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0001, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- },
- // PCIe0 Slot 4
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0004, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- }
+};
+UINT8 +OemGetPcieSlotNumber (
- VOID
- )
+{
- return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+EFI_HII_HANDLE +EFIAPI +OemGetPackages (
- )
+{
- return HiiAddPackages (
&gEfiCallerIdGuid,NULL,OemMiscLibHi1616EvbStrings,NULL,NULL);+}
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/
+/=#
+#langdef en-US "English"
+// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"
+// +// DIMM Device Locator strings
+#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28"
+// +// End English Language Strings +//
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..b17eead --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h>
+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h>
+#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
- {67,0,0,0},
- {225,0,0,3},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+BOOLEAN OemIsSocketPresent (UINTN Socket) +{
- if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
- return TRUE;
- } else {
- return FALSE;
- }
+}
+UINTN OemGetSocketNumber (VOID) +{
- if(!OemIsMpBoot()) {
- return OEM_SINGLE_SOCKET;
- }
- return OEM_DUAL_SOCKET;
+}
+UINTN OemGetDdrChannel (VOID) +{
- return 4;
+}
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{
- return 2;
+}
+VOID CoreSelectBoot(VOID) +{
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
StartupAp ();- }
- return;
+}
+BOOLEAN OemIsMpBoot() +{
- return PcdGet32(PcdIsMPBoot);
+}
+VOID OemLpcInit(VOID) +{
- LpcInit();
- return;
+}
+UINT32 OemIsWarmBoot(VOID) +{
- return 0;
+}
+VOID OemBiosSwitch(UINT32 Master) +{
- (VOID)Master;
- return;
+}
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{
- return TRUE;
+} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = OemMiscLibHi1616Evb
- FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = OemMiscLib
+[Sources.common]
- BoardFeatureD05.c
- BoardFeatureD05Strings.uni
- OemMiscLibD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
- TimerLib
+[BuildOptions]
+[Ppis]
- gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES
+[Pcd]
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
- gHisiTokenSpaceGuid.PcdIsMPBoot
- gHisiTokenSpaceGuid.PcdSocketMask
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[FixedPcd.common]
+[Guids]
+[Protocols]
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h>
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
{0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
{0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
{0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
{0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
- {// HostBridge 0
- /* Port 0 */
- {
PCI_HB0RB0_ECAM_BASE, //ecam0x80, //BusBase0x87, //BusLimitPCI_HB0RB0_PCIREGION_BASE, //MembasePCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB0_PCI_BASE),//RbPciBarPCI_HB0RB0_PCIREGION_BASE, //PciRegionbasePCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB0RB1_ECAM_BASE,//ecam0x90, //BusBase0x97, //BusLimitPCI_HB0RB1_PCIREGION_BASE, //MembasePCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB1_IO_BASE), //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimitPCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB1_PCI_BASE), //RbPciBarPCI_HB0RB1_PCIREGION_BASE, //PciRegionbasePCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB0RB2_ECAM_BASE,0x80, //BusBase0x87, //BusLimitPCI_HB0RB2_CPUMEMREGIONBASE ,//MemBasePCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB2_IO_BASE), //IOBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimitPCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB2_PCI_BASE), //RbPciBarPCI_HB0RB2_PCIREGION_BASE, //PciRegionbasePCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB0RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB0RB3_ECAM_BASE), //MemBase(PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit(PCI_HB0RB3_IO_BASE), //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimitPCI_HB0RB3_CPUMEMREGIONBASE,PCI_HB0RB3_CPUIOREGIONBASE,(PCI_HB0RB3_PCI_BASE), //RbPciBarPCI_HB0RB3_PCIREGION_BASE, //PciRegionbasePCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB0RB4_ECAM_BASE, //ecam0x88, //BusBase0x8f, //BusLimitPCI_HB0RB4_CPUMEMREGIONBASE, //MembasePCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimitPCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB4_PCI_BASE), //RbPciBarPCI_HB0RB4_PCIREGION_BASE, //PciRegionbasePCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB0RB5_ECAM_BASE,//ecam0x0, //BusBase0x7, //BusLimitPCI_HB0RB5_CPUMEMREGIONBASE, //MembasePCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB5_IO_BASE), //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimitPCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB5_PCI_BASE), //RbPciBarPCI_HB0RB5_PCIREGION_BASE, //PciRegionbasePCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB0RB6_ECAM_BASE,0xC0, //BusBase0xC7, //BusLimitPCI_HB0RB6_PCIREGION_BASE ,//MemBasePCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB6_IO_BASE), //IOBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimitPCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB6_PCI_BASE), //RbPciBarPCI_HB0RB6_PCIREGION_BASE, //PciRegionbasePCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB0RB7_ECAM_BASE,0x90, //BusBase0x97, //BusLimitPCI_HB0RB7_CPUMEMREGIONBASE, //MemBasePCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB7_IO_BASE), //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimitPCI_HB0RB7_CPUMEMREGIONBASE,PCI_HB0RB7_CPUIOREGIONBASE,(PCI_HB0RB7_PCI_BASE), //RbPciBarPCI_HB0RB7_PCIREGION_BASE, //PciRegionbasePCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- },
+{// HostBridge 1
- /* Port 0 */
- {
PCI_HB1RB0_ECAM_BASE,0x80, //BusBase0x87, //BusLimit(PCI_HB1RB0_ECAM_BASE), //MemBase(PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB0_PCI_BASE), //RbPciBarPCI_HB1RB0_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB1RB1_ECAM_BASE,0x90, //BusBase0x97, //BusLimit(PCI_HB1RB1_ECAM_BASE), //MemBase(PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB1_IO_BASE, //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB1_PCI_BASE), //RbPciBarPCI_HB1RB1_PCIREGION_BASE, //PciRegionbasePCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB1RB2_ECAM_BASE,0x10, //BusBase0x1f, //BusLimitPCI_HB1RB2_CPUMEMREGIONBASE, //MemBasePCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB2_IO_BASE, //IoBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB2_PCI_BASE), //RbPciBarPCI_HB1RB2_PCIREGION_BASE, //PciRegionbasePCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB1RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB1RB3_ECAM_BASE), //MemBase(PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB3_IO_BASE, //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB3_PCI_BASE), //RbPciBarPCI_HB1RB3_PCIREGION_BASE, //PciRegionbasePCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB1RB4_ECAM_BASE,0x20, //BusBase0x2f, //BusLimitPCI_HB1RB4_CPUMEMREGIONBASE, //MemBasePCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB4_PCI_BASE), //RbPciBarPCI_HB1RB4_PCIREGION_BASE, //PciRegionbasePCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB1RB5_ECAM_BASE,0x30, //BusBase0x3f, //BusLimitPCI_HB1RB5_CPUMEMREGIONBASE, //MemBasePCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB5_IO_BASE, //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB5_PCI_BASE), //RbPciBarPCI_HB1RB5_PCIREGION_BASE, //PciRegionbasePCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB1RB6_ECAM_BASE,0xa8, //BusBase0xaf, //BusLimit(PCI_HB1RB6_ECAM_BASE), //MemBasePCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB6_IO_BASE, //IoBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB6_PCI_BASE), //RbPciBarPCI_HB1RB6_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB1RB7_ECAM_BASE,0xb8, //BusBase0xbf, //BusLimit(PCI_HB1RB7_ECAM_BASE), //MemBasePCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB7_IO_BASE, //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB7_PCI_BASE), //RbPciBarPCI_HB1RB7_PCIREGION_BASE, //PciRegionbasePCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- }
+};
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = PlatformPciLib
- FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
+[Sources]
- PlatformPciLib.c
+[Packages]
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdHb1BaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PciHb0Rb0Base
- gHisiTokenSpaceGuid.PciHb0Rb1Base
- gHisiTokenSpaceGuid.PciHb0Rb2Base
- gHisiTokenSpaceGuid.PciHb0Rb3Base
- gHisiTokenSpaceGuid.PciHb0Rb4Base
- gHisiTokenSpaceGuid.PciHb0Rb5Base
- gHisiTokenSpaceGuid.PciHb0Rb6Base
- gHisiTokenSpaceGuid.PciHb0Rb7Base
- gHisiTokenSpaceGuid.PciHb1Rb0Base
- gHisiTokenSpaceGuid.PciHb1Rb1Base
- gHisiTokenSpaceGuid.PciHb1Rb2Base
- gHisiTokenSpaceGuid.PciHb1Rb3Base
- gHisiTokenSpaceGuid.PciHb1Rb4Base
- gHisiTokenSpaceGuid.PciHb1Rb5Base
- gHisiTokenSpaceGuid.PciHb1Rb6Base
- gHisiTokenSpaceGuid.PciHb1Rb7Base
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
-- 1.9.1
On Wed, Dec 07, 2016 at 04:33:18PM +0800, Heyi Guo wrote:
The rest of this patch (apart from the bits that will need to change to adapt to the above) is now fine.
Please fix and resubmit this patch only.
After fix the coding style of structure, we also need to modify the function UpdateSlotUsage() which will use the SERDES_PARAM and its members. If I modify the UpdateSlotUsage(), I have to modify D02 and D03 boardfeature.c file. Because this function is platform function. So I make another 3 patches. I will sent out the 4 patches, is that ok?
Yes, that makes sense.
Oh, one more thing - can you add a standard license/copyright header to Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h? The other files added by this patch all have one.
Regards,
Leif
Thanks and Regards, Heyi
Regards,
Leif
+#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF
+typedef struct {
- UINT32 MacroId;
- UINT32 DsNum;
- UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; +UINT32 GetEthType(UINT8 EthChannel); +VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode);
+EFI_STATUS +EfiSerdesInitWrap (VOID); +INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); +VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
+#endif diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 0faa100..2c02e14 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -104,7 +104,10 @@ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
- gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
- gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
- gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000..edaad18 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -0,0 +1,674 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#
+################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines]
- PLATFORM_NAME = D05
- PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x00010019
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64
- BUILD_TARGETS = DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
- DEFINE EDK2_SKIP_PEICORE=0
- DEFINE INCLUDE_TFTP_COMMAND=1
- DEFINE NETWORK_IP6_ENABLE = FALSE
- DEFINE HTTP_BOOT_ENABLE = FALSE
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+[LibraryClasses.common]
- ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
- BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+!endif
+!if $(HTTP_BOOT_ENABLE) == TRUE
- HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+!ifdef $(FDT_ENABLE)
- #FDTUpdateLib
- FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
- CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
- SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
- EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
- #D05 RTC hardware is same as D03
- RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
- OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
- OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
- PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
- PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
- # USB Requirements
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
- LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[LibraryClasses.common.SEC]
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[BuildOptions]
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include
+################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################
+[PcdsFeatureFlag.common]
+!if $(EDK2_SKIP_PEICORE) == 1
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
- # It could be set FALSE to save size.
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
- gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+[PcdsFixedAtBuild.common]
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"
- gArmPlatformTokenSpaceGuid.PcdCoreCount|8
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- # Stacks for MPCores in Secure World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
- # Stacks for MPCores in Monitor Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
- # Stacks for MPCores in Normal World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
- gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
- #
- # ARM Pcds
- #
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
- gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15- ## SP805 Watchdog - Motherboard Watchdog
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
- ## Serial Terminal
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
- # use the TTY terminal type (which has a working backspace)
- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
- gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
- gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
- gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
- gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gHisiTokenSpaceGuid.PcdIsMPBoot|1
- gHisiTokenSpaceGuid.PcdSocketMask|0x3
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1"
- gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
- gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
- gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
- gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
- #
- # ARM Architectual Timer Frequency
- #
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
- gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
- gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
- gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
- gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
- gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
- gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
- gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
- ## DTB address at spi flash
- gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000
- gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
- gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
- gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
- gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
- gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
- gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
- gHisiTokenSpaceGuid.PcdNumaEnable|1
- gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
- gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
- gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
- gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
- gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
- gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
- gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
- gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
- gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
- gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
- gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
- gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
- gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common]
- #
- # SEC
- #
- #
- # PEI Phase modules
- #
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- MdeModulePkg/Core/Pei/PeiMain.inf
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- ArmPkg/Drivers/CpuPei/CpuPei.inf
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf- }
- #
- # DXE
- #
- MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf- }
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # Architectural Protocols
- #
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug.
- #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf- }
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>
CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf- }
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- #ACPI
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- # Usb Support
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- #
- #network
- #
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- NetworkPkg/TcpDxe/TcpDxe.inf
- NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- NetworkPkg/DnsDxe/DnsDxe.inf
- NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- NetworkPkg/HttpDxe/HttpDxe.inf
- NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Bds
- #
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+!ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #PCIe Support
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf- }
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- # Memory test
- #
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.infNULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.infNULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.infNULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.infNULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.infNULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.infNULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.infHandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.infPrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.infBcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf+!if $(NETWORK_IP6_ENABLE) == TRUE
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf+!endif
+!ifdef $(INCLUDE_DP)
NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf+!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND)
NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf+!endif #$(INCLUDE_TFTP_COMMAND)
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFFgEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSEgEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000- }
diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000..bdfb211 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -0,0 +1,366 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#
+[DEFINES]
+################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05]
+BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1
+# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30
+################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################
+0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
+0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT
+0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin +0x002A0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin
+0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = {
- ## This is the EFI_FIRMWARE_VOLUME_HEADER
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- # FileSystemGuid: gEfiSystemNvDataFvGuid =
- 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
- 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
- # FvLength: 0x20000
- 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- #Signature "_FVH" #Attributes
- 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
- #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
- 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
- #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
- #Blockmap[1]: End
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
- 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
- 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
- #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
- 0xB8, 0xdF, 0x00, 0x00,
- #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
- 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = {
- # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
- 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
- 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
- # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
- 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
- # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
- 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+0x002F0000|0x00010000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################
+[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI DXE {
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- }
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
- #
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- #
- # Multiple Console IO support
- #
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- INF FatBinPkg/EnhancedFatDxe/Fat.inf
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- # Usb Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
- INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- #ACPI
- #
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- #Network
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- INF NetworkPkg/TcpDxe/TcpDxe.inf
- INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- INF NetworkPkg/DnsDxe/DnsDxe.inf
- INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- INF NetworkPkg/HttpDxe/HttpDxe.inf
- INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
+!ifdef $(FDT_ENABLE)
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #
- # PCI Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
- INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- # VGA Driver
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Build Shell from latest source code instead of prebuilt binary
- #
- INF ShellPkg/Application/Shell/Shell.inf
- #
- # Bds
- #
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI PEI {
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- }
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- INF MdeModulePkg/Core/Pei/PeiMain.inf
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN- }
- }
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000..76a055c --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PiPei.h> +#include <PlatformArch.h> +#include <Uefi.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformSysCtrlLib.h>
+VOID +QResetAp (
- VOID
- )
+{
- MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
- (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
- StartupAp();
- }
+}
+EFI_STATUS +EFIAPI +EarlyConfigEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
+{
- DEBUG((DEBUG_INFO,"SMMU CONFIG........."));
- (VOID)SmmuConfigForBios();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"AP CONFIG........."));
- (VOID)QResetAp();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"MN CONFIG........."));
- (VOID)MN_CONFIG();
- DEBUG((DEBUG_INFO,"Done\n"));
- return EFI_SUCCESS;
+}
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000..5fdf555 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = EarlyConfigPeimD05
- FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = EarlyConfigEntry
+[Sources.common]
- EarlyConfigPeimD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- ArmLib
- CacheMaintenanceLib
- DebugLib
- IoLib
- PcdLib
- PeimEntryPoint
- PlatformSysCtrlLib
+[Pcd]
- gHisiTokenSpaceGuid.PcdMailBoxAddress
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[Depex] +## As we will clean mailbox in this module, need to wait memory init complete
- gEfiPeiMemoryDiscoveredPpiGuid
+[BuildOptions]
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000..473da0a --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,225 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h> +#include <IndustryStandard/SmBios.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HiiLib.h> +#include <Library/I2CLib.h> +#include <Library/IoLib.h> +#include <Library/OemMiscLib.h> +#include <Library/SerdesLib.h> +#include <Protocol/Smbios.h>
+I2C_DEVICE gDS3231RtcDevice = {
- .Socket = 0,
- .Port = 4,
- .DeviceType = DEVICE_TYPE_SPD,
- .SlaveDeviceAddress = 0x68
+};
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+serdes_param_t gSerdesParamNA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamNB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
+};
+serdes_param_t gSerdesParamS1NB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
+};
+EFI_STATUS +OemGetSerdesParam (
- OUT serdes_param_t *ParamA,
- OUT serdes_param_t *ParamB,
- IN UINT32 SocketId
- )
+{
- if (ParamA == NULL || ParamB == NULL) {
- DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
- return EFI_INVALID_PARAMETER;
- }
- if (SocketId == 0) {
- (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
- } else {
- (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
- }
- return EFI_SUCCESS;
+}
+VOID +OemPcieResetAndOffReset (
- VOID
- )
+{
- return;
+}
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
- // PCIe0 Slot 1
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0001, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- },
- // PCIe0 Slot 4
- {
- { // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,0, // Length,0 // Handle- },
- 1, // SlotDesignation
- SlotTypePciExpressX8, // SlotType
- SlotDataBusWidth8X, // SlotDataBusWidth
- SlotUsageAvailable, // SlotUsage
- SlotLengthOther, // SlotLength
- 0x0004, // SlotId
- { // SlotCharacteristics1
0, // CharacteristicsUnknown :1;0, // Provides50Volts :1;0, // Provides33Volts :1;0, // SharedSlot :1;0, // PcCard16Supported :1;0, // CardBusSupported :1;0, // ZoomVideoSupported :1;0 // ModemRingResumeSupported:1;- },
- { // SlotCharacteristics2
0, // PmeSignalSupported :1;0, // HotPlugDevicesSupported :1;0, // SmbusSignalSupported :1;0 // Reserved :5;- },
- 0x00, // SegmentGroupNum
- 0x00, // BusNum
- 0 // DevFuncNum
- }
+};
+UINT8 +OemGetPcieSlotNumber (
- VOID
- )
+{
- return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+EFI_HII_HANDLE +EFIAPI +OemGetPackages (
- )
+{
- return HiiAddPackages (
&gEfiCallerIdGuid,NULL,OemMiscLibHi1616EvbStrings,NULL,NULL);+}
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/
+/=#
+#langdef en-US "English"
+// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"
+// +// DIMM Device Locator strings
+#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28"
+// +// End English Language Strings +//
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..b17eead --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h>
+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h>
+#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
- {67,0,0,0},
- {225,0,0,3},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+BOOLEAN OemIsSocketPresent (UINTN Socket) +{
- if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
- return TRUE;
- } else {
- return FALSE;
- }
+}
+UINTN OemGetSocketNumber (VOID) +{
- if(!OemIsMpBoot()) {
- return OEM_SINGLE_SOCKET;
- }
- return OEM_DUAL_SOCKET;
+}
+UINTN OemGetDdrChannel (VOID) +{
- return 4;
+}
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{
- return 2;
+}
+VOID CoreSelectBoot(VOID) +{
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
StartupAp ();- }
- return;
+}
+BOOLEAN OemIsMpBoot() +{
- return PcdGet32(PcdIsMPBoot);
+}
+VOID OemLpcInit(VOID) +{
- LpcInit();
- return;
+}
+UINT32 OemIsWarmBoot(VOID) +{
- return 0;
+}
+VOID OemBiosSwitch(UINT32 Master) +{
- (VOID)Master;
- return;
+}
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{
- return TRUE;
+} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = OemMiscLibHi1616Evb
- FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = OemMiscLib
+[Sources.common]
- BoardFeatureD05.c
- BoardFeatureD05Strings.uni
- OemMiscLibD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
- TimerLib
+[BuildOptions]
+[Ppis]
- gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES
+[Pcd]
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
- gHisiTokenSpaceGuid.PcdIsMPBoot
- gHisiTokenSpaceGuid.PcdSocketMask
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[FixedPcd.common]
+[Guids]
+[Protocols]
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h>
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
{0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
{0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
{0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
{0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
- {// HostBridge 0
- /* Port 0 */
- {
PCI_HB0RB0_ECAM_BASE, //ecam0x80, //BusBase0x87, //BusLimitPCI_HB0RB0_PCIREGION_BASE, //MembasePCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB0_PCI_BASE),//RbPciBarPCI_HB0RB0_PCIREGION_BASE, //PciRegionbasePCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB0RB1_ECAM_BASE,//ecam0x90, //BusBase0x97, //BusLimitPCI_HB0RB1_PCIREGION_BASE, //MembasePCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB1_IO_BASE), //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimitPCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB1_PCI_BASE), //RbPciBarPCI_HB0RB1_PCIREGION_BASE, //PciRegionbasePCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB0RB2_ECAM_BASE,0x80, //BusBase0x87, //BusLimitPCI_HB0RB2_CPUMEMREGIONBASE ,//MemBasePCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB2_IO_BASE), //IOBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimitPCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB2_PCI_BASE), //RbPciBarPCI_HB0RB2_PCIREGION_BASE, //PciRegionbasePCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB0RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB0RB3_ECAM_BASE), //MemBase(PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit(PCI_HB0RB3_IO_BASE), //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimitPCI_HB0RB3_CPUMEMREGIONBASE,PCI_HB0RB3_CPUIOREGIONBASE,(PCI_HB0RB3_PCI_BASE), //RbPciBarPCI_HB0RB3_PCIREGION_BASE, //PciRegionbasePCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB0RB4_ECAM_BASE, //ecam0x88, //BusBase0x8f, //BusLimitPCI_HB0RB4_CPUMEMREGIONBASE, //MembasePCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //MemlimitPCI_HB0RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimitPCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB4_PCI_BASE), //RbPciBarPCI_HB0RB4_PCIREGION_BASE, //PciRegionbasePCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB0RB5_ECAM_BASE,//ecam0x0, //BusBase0x7, //BusLimitPCI_HB0RB5_CPUMEMREGIONBASE, //MembasePCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB5_IO_BASE), //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimitPCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB5_PCI_BASE), //RbPciBarPCI_HB0RB5_PCIREGION_BASE, //PciRegionbasePCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB0RB6_ECAM_BASE,0xC0, //BusBase0xC7, //BusLimitPCI_HB0RB6_PCIREGION_BASE ,//MemBasePCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB6_IO_BASE), //IOBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimitPCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB0RB6_PCI_BASE), //RbPciBarPCI_HB0RB6_PCIREGION_BASE, //PciRegionbasePCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB0RB7_ECAM_BASE,0x90, //BusBase0x97, //BusLimitPCI_HB0RB7_CPUMEMREGIONBASE, //MemBasePCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit(PCI_HB0RB7_IO_BASE), //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimitPCI_HB0RB7_CPUMEMREGIONBASE,PCI_HB0RB7_CPUIOREGIONBASE,(PCI_HB0RB7_PCI_BASE), //RbPciBarPCI_HB0RB7_PCIREGION_BASE, //PciRegionbasePCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- },
+{// HostBridge 1
- /* Port 0 */
- {
PCI_HB1RB0_ECAM_BASE,0x80, //BusBase0x87, //BusLimit(PCI_HB1RB0_ECAM_BASE), //MemBase(PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB0_IO_BASE, //IoBase(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB0_PCI_BASE), //RbPciBarPCI_HB1RB0_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 1 */
- {
PCI_HB1RB1_ECAM_BASE,0x90, //BusBase0x97, //BusLimit(PCI_HB1RB1_ECAM_BASE), //MemBase(PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB1_IO_BASE, //IoBase(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB1_PCI_BASE), //RbPciBarPCI_HB1RB1_PCIREGION_BASE, //PciRegionbasePCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 2 */
- {
PCI_HB1RB2_ECAM_BASE,0x10, //BusBase0x1f, //BusLimitPCI_HB1RB2_CPUMEMREGIONBASE, //MemBasePCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB2_IO_BASE, //IoBase(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB2_PCI_BASE), //RbPciBarPCI_HB1RB2_PCIREGION_BASE, //PciRegionbasePCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 3 */
- {
PCI_HB1RB3_ECAM_BASE,0xb0, //BusBase0xb7, //BusLimit(PCI_HB1RB3_ECAM_BASE), //MemBase(PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimitPCI_HB1RB3_IO_BASE, //IoBase(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB3_PCI_BASE), //RbPciBarPCI_HB1RB3_PCIREGION_BASE, //PciRegionbasePCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 4 */
- {
PCI_HB1RB4_ECAM_BASE,0x20, //BusBase0x2f, //BusLimitPCI_HB1RB4_CPUMEMREGIONBASE, //MemBasePCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB4_IO_BASE, //IoBase(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB4_PCI_BASE), //RbPciBarPCI_HB1RB4_PCIREGION_BASE, //PciRegionbasePCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 5 */
- {
PCI_HB1RB5_ECAM_BASE,0x30, //BusBase0x3f, //BusLimitPCI_HB1RB5_CPUMEMREGIONBASE, //MemBasePCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB5_IO_BASE, //IoBase(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB5_PCI_BASE), //RbPciBarPCI_HB1RB5_PCIREGION_BASE, //PciRegionbasePCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 6 */
- {
PCI_HB1RB6_ECAM_BASE,0xa8, //BusBase0xaf, //BusLimit(PCI_HB1RB6_ECAM_BASE), //MemBasePCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB6_IO_BASE, //IoBase(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB6_PCI_BASE), //RbPciBarPCI_HB1RB6_PCIREGION_BASE, //PciRegionbasePCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit- },
- /* Port 7 */
- {
PCI_HB1RB7_ECAM_BASE,0xb8, //BusBase0xbf, //BusLimit(PCI_HB1RB7_ECAM_BASE), //MemBasePCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimitPCI_HB1RB7_IO_BASE, //IoBase(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimitPCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBasePCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase(PCI_HB1RB7_PCI_BASE), //RbPciBarPCI_HB1RB7_PCIREGION_BASE, //PciRegionbasePCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit- }
- }
+};
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = PlatformPciLib
- FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
+[Sources]
- PlatformPciLib.c
+[Packages]
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdHb1BaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PciHb0Rb0Base
- gHisiTokenSpaceGuid.PciHb0Rb1Base
- gHisiTokenSpaceGuid.PciHb0Rb2Base
- gHisiTokenSpaceGuid.PciHb0Rb3Base
- gHisiTokenSpaceGuid.PciHb0Rb4Base
- gHisiTokenSpaceGuid.PciHb0Rb5Base
- gHisiTokenSpaceGuid.PciHb0Rb6Base
- gHisiTokenSpaceGuid.PciHb0Rb7Base
- gHisiTokenSpaceGuid.PciHb1Rb0Base
- gHisiTokenSpaceGuid.PciHb1Rb1Base
- gHisiTokenSpaceGuid.PciHb1Rb2Base
- gHisiTokenSpaceGuid.PciHb1Rb3Base
- gHisiTokenSpaceGuid.PciHb1Rb4Base
- gHisiTokenSpaceGuid.PciHb1Rb5Base
- gHisiTokenSpaceGuid.PciHb1Rb6Base
- gHisiTokenSpaceGuid.PciHb1Rb7Base
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
-- 1.9.1
We would get incorrect data when accessing multiple bytes at one time and going across EEPROM page boundary, so we split data when the length greater than page boundary.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 45 +++++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c index 994ed6a..dcaf3aa 100644 --- a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c @@ -26,6 +26,7 @@ #include <Library/I2CLib.h>
#define EEPROM_I2C_PORT 6 +#define EEPROM_PAGE_SIZE 0x40
EFI_STATUS EFIAPI OemGetMac2P (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port); @@ -110,6 +111,8 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) UINT16 I2cOffset; UINT16 crc16; NIC_MAC_ADDRESS stMacDesc = {0}; + UINT16 RemainderMacOffset; + UINT16 LessSizeOfPage;
Status = I2CInit(0, EEPROM_I2C_PORT, Normal); if (EFI_ERROR(Status)) @@ -124,7 +127,25 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0; - Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; + LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; + //The length of NIC_MAC_ADDRESS is 10 bytes long, + //It surly less than EEPROM page size, so we could + //code as bellow, check the address whether across the page boundary, + //and split the data when across page boundary. + if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { + Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + } else { + Status = I2CRead(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); + if (!(EFI_ERROR(Status))) { + Status |= I2CRead( + &stI2cDev, + I2cOffset + LessSizeOfPage, + sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, + (UINT8 *)&stMacDesc + LessSizeOfPage + ); + } + } if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); @@ -153,6 +174,8 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr)
stMacDesc.MacLen = MAC_ADDR_LEN; + UINT16 RemainderMacOffset; + UINT16 LessSizeOfPage; gBS->CopyMem((VOID *)(stMacDesc.Mac), (VOID *)pucAddr, MAC_ADDR_LEN);
stMacDesc.Crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + MAC_ADDR_LEN); @@ -170,7 +193,25 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0; - Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; + LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; + //The length of NIC_MAC_ADDRESS is 10 bytes long, + //It surly less than EEPROM page size, so we could + //code as bellow, check the address whether across the page boundary, + //and split the data when across page boundary. + if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { + Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + } else { + Status = I2CWrite(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); + if (!(EFI_ERROR(Status))) { + Status |= I2CWrite( + &stI2cDev, + I2cOffset + LessSizeOfPage, + sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, + (UINT8 *)&stMacDesc + LessSizeOfPage + ); + } + } if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
The default FirmwareVender pcd is defined at Chips/Hisilicon/Hisipkg.dec,and the value is 'Huawei corp.', so the FirmwareVendor pcd at the dsc file useless, remove them.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/Hisilicon/D02/Pv660D02.dsc | 1 - Platforms/Hisilicon/D03/D03.dsc | 1 - 2 files changed, 2 deletions(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 9c23fa7..55e7ad5 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -102,7 +102,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
[PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D02"
gArmPlatformTokenSpaceGuid.PcdCoreCount|8 diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index e7b8bdd..d8d8be1 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -115,7 +115,6 @@ gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE
[PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03"
gArmPlatformTokenSpaceGuid.PcdCoreCount|8
The original size of FVMAIN_COMPACT is not enough for clang DEBUG version, so we enlarge FVMAIN_COMPACT and move variable store and Trusted Firmware binaries accordingly
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/Hisilicon/D02/Pv660D02.fdf | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.fdf b/Platforms/Hisilicon/D02/Pv660D02.fdf index 34f2368..406b501 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.fdf +++ b/Platforms/Hisilicon/D02/Pv660D02.fdf @@ -58,11 +58,18 @@ NumBlocks = 0x30 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Sec/FVMAIN_SEC.Fv
-0x00040000|0x00190000 +0x00040000|0x00240000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT
-0x001e0000|0x0000e000 +## Place for Trusted Firmware +0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/bl1.bin +0x002a0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/fip.bin + +0x002e0000|0x0000e000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize DATA = { ## This is the EFI_FIRMWARE_VOLUME_HEADER @@ -90,7 +97,7 @@ DATA = { 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
-0x001ee000|0x00002000 +0x002ee000|0x00002000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize #NV_FTW_WORKING DATA = { @@ -103,16 +110,9 @@ DATA = { 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
-0x001f0000|0x00010000 +0x002f0000|0x00010000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
-## Place for Trusted Firmware -0x00200000|0x00020000 -gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base -FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/bl1.bin -0x00220000|0x000e0000 -FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/fip.bin - ################################################################################ # # FV Section
The `psci_plat_pm_ops` global pointer is initialized during cold boot by the primary CPU and will be accessed by the secondary CPUs before enabling data cache during warm boot. This patch adds a missing data cache flush of `psci_plat_psci_ops` after initialization during psci_setup() so that secondaries can see the updated `psci_plat_psci_ops` pointer. Fixes ARM-software/tf-issues#424
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/Hisilicon/Binary/D02/bl1.bin | Bin 14344 -> 12296 bytes Platforms/Hisilicon/Binary/D02/fip.bin | Bin 45621 -> 45621 bytes 2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platforms/Hisilicon/Binary/D02/bl1.bin b/Platforms/Hisilicon/Binary/D02/bl1.bin index f11a0a0..d64bfd8 100644 Binary files a/Platforms/Hisilicon/Binary/D02/bl1.bin and b/Platforms/Hisilicon/Binary/D02/bl1.bin differ diff --git a/Platforms/Hisilicon/Binary/D02/fip.bin b/Platforms/Hisilicon/Binary/D02/fip.bin index d8f85d0..7cdd9db 100644 Binary files a/Platforms/Hisilicon/Binary/D02/fip.bin and b/Platforms/Hisilicon/Binary/D02/fip.bin differ
The original size of FVMAIN_COMPACT is not enough for clang DEBUG version, so we enlarge FVMAIN_COMPACT and move Trusted Firmware binaries accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/Hisilicon/D03/D03.fdf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index d4a0049..38a5ef9 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -58,14 +58,14 @@ NumBlocks = 0x30 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv
-0x00040000|0x001C0000 +0x00040000|0x00240000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT
-0x00200000|0x00020000 +0x00280000|0x00020000 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/bl1.bin -0x00220000|0x00020000 +0x002A0000|0x00020000 FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/fip.bin
0x002D0000|0x0000E000
Update D03 binaries fix below issues:
1. Update ebl.efi to solve can not get IP address through DHCP 2. Update D03 binaries to adapt new D03 board, this include LpcLib,LpcSerialPortLib and Ipmi related lib, and the Lpc hardware is different to old D03 board. 3. Update Snp net driver,inlcude some code refine modification. 4. Update SerdesLib for structure and function definition changes 5. Update ATF binaries to fix a bug in ATF code The `psci_plat_pm_ops` global pointer is initialized during cold boot by the primary CPU and will be accessed by the secondary CPUs before enabling data cache during warm boot. This patch adds a missing data cache flush of `psci_plat_psci_ops` after initialization during psci_setup() so that secondaries can see the updated `psci_plat_psci_ops` pointer. Fixes ARM-software/tf-issues#424 6. Update ReportPciePlugDidVidToBmc.efi to fix a wrong pci slot num issue. 7. Update NativeOhci and SfcDriver.efi for structure definition changes. 8. Update Sm750 driver for code refine modification. 9. Update OemaddressMap2P.lib to adapt new address allocation.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Library/Hi1610Serdes/Hi1610SerdesLib.lib | Bin 601828 -> 603524 bytes .../Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib | Bin 253328 -> 247176 bytes .../Binary/Hi1610/Library/LpcLib/LpcLib.lib | Bin 13870 -> 13998 bytes .../Uart/LpcSerialPortLib/LpcSerialPortLib.lib | Bin 17086 -> 17022 bytes .../D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 22304 -> 21696 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 22240 -> 22208 bytes .../Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 26720 -> 25440 bytes .../D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 24704 -> 23712 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 18368 -> 18080 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 63648 -> 56832 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 63648 -> 56832 bytes .../Binary/D03/Drivers/OhciDxe/NativeOhci.efi | Bin 55488 -> 48352 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 22752 -> 22112 bytes .../Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi | Bin 262144 -> 262144 bytes .../D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 38624 -> 36480 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 22112 -> 21408 bytes Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi | Bin 159744 -> 134240 bytes .../Library/OemAddressMap2P/OemAddressMap2P.lib | Bin 19568 -> 19486 bytes Platforms/Hisilicon/Binary/D03/bl1.bin | Bin 14336 -> 14336 bytes Platforms/Hisilicon/Binary/D03/fip.bin | Bin 45601 -> 45601 bytes 22 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.lib index b64e871..c55d678 100644 Binary files a/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.lib and b/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.lib differ diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib index 3e8c8e1..1b02db1 100644 Binary files a/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib and b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib differ diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.lib index b47d026..f74d98d 100644 Binary files a/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.lib and b/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.lib differ diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.lib index 0c9f0e4..6f88fc1 100644 Binary files a/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.lib and b/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.lib differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi index f125211..0b17045 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi index cf62305..c3347c1 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi index 8352d01..f6a2333 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi index 29989b5..2c064c1 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi index 7528087..048ac5c 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi index b898237..d88b511 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi index c93b96e..40eceb1 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi index de69e98..9fff194 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi index 007b61f..709bcb6 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi index ffe8cc0..9abddfc 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi index a49c89f..251c786 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi index d33e7ce..e1e04eb 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi index c2c2ef0..a8241c1 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi index 6efc751..53edeba 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi index 266d8ea..914370a 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi and b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib index 77d8023..fe23d93 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib and b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib differ diff --git a/Platforms/Hisilicon/Binary/D03/bl1.bin b/Platforms/Hisilicon/Binary/D03/bl1.bin index 3d57440..7bf0698 100644 Binary files a/Platforms/Hisilicon/Binary/D03/bl1.bin and b/Platforms/Hisilicon/Binary/D03/bl1.bin differ diff --git a/Platforms/Hisilicon/Binary/D03/fip.bin b/Platforms/Hisilicon/Binary/D03/fip.bin index 94b2c2e..913d40d 100644 Binary files a/Platforms/Hisilicon/Binary/D03/fip.bin and b/Platforms/Hisilicon/Binary/D03/fip.bin differ
Add Spd mirror mode related registers definition, this is used by memoryinit binary code,base this definition it could support spd mirror mode to have diffrent configuration about MR register.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index c24930f..2663cad 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize; + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM]; }DDR_DIMM;
@@ -337,6 +338,7 @@ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest; UINT8 Config1[5]; + UINT8 ErrorBypass; //register of spd mirror mode UINT32 Config2; }MEMORY;
@@ -789,6 +791,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM
#define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte
It is PORT_TP type if the service port is GE mode. It is wrong to judge the port type by using if it is service port. Adding the media type to know port type.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan yankejian@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 4 ++++ Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index aa83489..b62ee45 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -466,6 +466,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0}, + Package () {"media-type", "fiber"}, } }) } @@ -476,6 +477,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1}, + Package () {"media-type", "fiber"}, } }) } @@ -489,6 +491,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } @@ -502,6 +505,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 5945fc3..2b08a1f 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -439,6 +439,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0}, + Package () {"media-type", "fiber"}, } }) } @@ -449,6 +450,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1}, + Package () {"media-type", "fiber"}, } }) } @@ -462,6 +464,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } @@ -475,6 +478,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) }
The register of Hilink needs to be configed, but the current procedure does not do that. The temporary variable to be set to register is wrong, it must be Local0 instead of Local1.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan yankejian@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 20 ++++++++++---------- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 12 ++++++------ 2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index b62ee45..d8d453a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -126,16 +126,16 @@ Scope(_SB) OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) Field(H4LR, DWordAcc, NoLock, Preserve) { H4L0, 16, // port0 - H4R0, 16, //RESERVED + , 16, //RESERVED Offset (0x400), H4L1, 16, // port1 - H4R1, 16, //RESERVED + , 16, //RESERVED Offset (0x800), H4L2, 16, // port2 - H4R2, 16, //RESERVED + , 16, //RESERVED Offset (0xc00), H4L3, 16, // port3 - H4R3, 16, //RESERVED + , 16, //RESERVED } OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) Field(H3LR, DWordAcc, NoLock, Preserve) { @@ -266,42 +266,42 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L0) + Store (Local0, H4L0) } case (0x1){ Store (0, HSEL) Store (H4L1, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L1) + Store (Local0, H4L1) } case (0x2){ Store (0, HSEL) Store (H4L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L2) + Store (Local0, H4L2) } case (0x3){ Store (0, HSEL) Store (H4L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L3) + Store (Local0, H4L3) } case (0x4){ Store (3, HSEL) Store (H3L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L2) + Store (Local0, H3L2) } case (0x5){ Store (3, HSEL) Store (H3L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L3) + Store (Local0, H3L3) } } } diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 2b08a1f..881aa14 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -250,37 +250,37 @@ Scope(_SB) Store (H4L0, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L0) + Store (Local0, H4L0) } case (0x1){ Store (H4L1, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L1) + Store (Local0, H4L1) } case (0x2){ Store (H4L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L2) + Store (Local0, H4L2) } case (0x3){ Store (H4L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H4L3) + Store (Local0, H4L3) } case (0x4){ Store (H3L2, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L2) + Store (Local0, H3L2) } case (0x5){ Store (H3L3, Local1) And (Local1, 0xfffffbff, Local1) Or (Local0, Local1, Local0) - Store (Local1, H3L3) + Store (Local0, H3L3) } } }
The UART on Hip05 soc is not 16550 compatible, use appropriate ACPI ID for Hisi uart instead of APM one, and delete the wrong comments.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kefeng Wang wangkefeng.wang@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl index d7350cf..e3fc0d3 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl @@ -18,13 +18,12 @@
Scope(_SB) { - // UART 8250 Device(COM0) { - Name(_HID, "APMC0D08") //Or AMD0020, trick to use dw8250 serial driver + Name(_HID, "HISI0031") //it is not 16550 compatible Name(_CID, "8250dw") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0x80300000, 0x1000) //0x7FF80000, 0x1000 + Memory32Fixed(ReadWrite, 0x80300000, 0x1000) Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 } }) Name (_DSD, Package () {
Set all ACPI tables' ID as below:
EFI_ACPI_ARM_OEM_ID HISI EFI_ACPI_ARM_OEM_TABLE_ID HISI0660 EFI_ACPI_ARM_OEM_REVISION 0x00000000 EFI_ACPI_ARM_CREATOR_ID INTL EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
Note that D02 SATASSDT/SASSSDT tables are not updated because we need different SSDT OEM TABLE ID uesed for UninstallACPI driver
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 6 +++--- Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl index ce5a085..f156e1b 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl @@ -18,7 +18,7 @@
#include "Pv660Platform.h"
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI-D02", EFI_ACPI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI0660", EFI_ACPI_ARM_OEM_REVISION) { include ("Mbig.asl") include ("CPU.asl") include ("Com.asl") diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index 44056b5..9ba3d55 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -10,11 +10,11 @@ [0004] Table Length : 0000010C [0001] Revision : 00 [0001] Checksum : BC -[0006] Oem ID : "INTEL " -[0008] Oem Table ID : "TEMPLATE" +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HISI0660" [0004] Oem Revision : 00000000 [0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20150410 +[0004] Asl Compiler Revision : 20151124
[0004] Node Count : 0000000A [0004] Node Offset : 00000034 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h index 5af8f1a..3d69d96 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h @@ -24,10 +24,10 @@ // ACPI table information used to initialize tables. // #define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','-','D','0','2') // OEM table id 8 bytes long -#define EFI_ACPI_ARM_OEM_REVISION 0x20140727 -#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('H','I','S','I') -#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099 +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','0','6','6','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
// A macro to initialise the common header part of EFI ACPI tables as defined by // EFI_ACPI_DESCRIPTION_HEADER structure.
D02 ACPI related files locate in Chips/Hisilicon/Pv660/Pv660Acpitables D03 ACPI related files will be moved to Chips/Hisilicon/Hi1610/Hi1610AcpiTables
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm Lefi.Lindholm@linaro.org --- .../Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf | 56 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl | 337 ------------ Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc | 85 ---- .../Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 562 --------------------- .../Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl | 125 ----- .../Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl | 261 ---------- .../Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl | 247 --------- .../Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl | 136 ----- .../Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl | 29 -- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl | 25 - .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 128 ----- 11 files changed, 1991 deletions(-) delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl delete mode 100644 Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf b/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf deleted file mode 100644 index b6be3d9..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf +++ /dev/null @@ -1,56 +0,0 @@ -## @file -# -# ACPI table data and ASL sources required to boot the platform. -# -# Copyright (c) 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -# -## - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = Hi1610AcpiTables - FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD - MODULE_TYPE = USER_DEFINED - VERSION_STRING = 1.0 - -[Sources] - Dsdt/DsdtHi1610.asl - Facs.aslc - Fadt.aslc - Gtdt.aslc - MadtHi1610.aslc - D03Mcfg.aslc - D03Iort.asl - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - - OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdCoreCount - gArmTokenSpaceGuid.PcdGicDistributorBase - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - - gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum - gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl deleted file mode 100644 index 07660df..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Iort.asl +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Intel ACPI Component Architecture - * iASL Compiler/Disassembler version 20151124-64 - * Copyright (c) 2000 - 2015 Intel Corporation - * - * Template for [IORT] ACPI Table (static data table) - * Format: [ByteLength] FieldName : HexFieldValue - */ -[0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 0000029e -[0001] Revision : 00 -[0001] Checksum : BC -[0006] Oem ID : "HISI " -[0008] Oem Table ID : "D03" -[0004] Oem Revision : 00000000 -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20150410 - -[0004] Node Count : 00000008 -[0004] Node Offset : 00000034 -[0004] Reserved : 00000000 -[0004] Optional Padding : 00 00 00 00 - -/* ITS 0, for dsa */ -[0001] Type : 00 -[0002] Length : 0018 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000000 -[0004] Mapping Offset : 00000000 - -[0004] ItsCount : 00000001 -[0004] Identifiers : 00000000 - -/* mbi-gen dsa mbi0 - usb, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0017] Device Name : "_SB_.MBI0" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040080 // device id -[0004] Output Reference : 00000034 // point to its dsa -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi1 - sas1, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI1" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi2 - sas2, named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI2" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040040 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi3 - dsa0, srv named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI3" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040800 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI4" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1c -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI5" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040b1d -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* mbi-gen dsa mbi6 - dsa sas0 named component */ -[0001] Type : 01 -[0002] Length : 0046 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000032 - -[0004] Node Flags : 00000000 -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000000 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0001] Memory Size Limit : 00 -[0016] Device Name : "_SB_.MBI6" -[0004] Padding : 00 00 00 00 - -[0004] Input base : 00000000 -[0004] ID Count : 00000001 -[0004] Output Base : 00040900 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 1 - -/* RC 0 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000000 - -[0004] Input base : 00000000 -[0004] ID Count : 00002000 -[0004] Output Base : 00000000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* RC 1 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000001 - -[0004] Input base : 0000e000 -[0004] ID Count : 00002000 -[0004] Output Base : 0000e000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -/* RC 2 */ -[0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 - -[0008] Memory Properties : [IORT Memory Access Properties] -[0004] Cache Coherency : 00000001 -[0001] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[0004] ATS Attribute : 00000000 -[0004] PCI Segment Number : 00000002 - -[0004] Input base : 00008000 -[0004] ID Count : 00002000 -[0004] Output Base : 00008000 -[0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc deleted file mode 100644 index 9f60803..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/D03Mcfg.aslc +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2016 Hisilicon Limited - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the BSD License which accompanies - * this distribution, and is available at - * http://opensource.org/licenses/bsd-license.php - * - */ - -#include <IndustryStandard/Acpi.h> -#include "Pv660Platform.h" - -#define ACPI_5_0_MCFG_VERSION 0x1 - -#pragma pack(1) -typedef struct -{ - UINT64 ullBaseAddress; - UINT16 usSegGroupNum; - UINT8 ucStartBusNum; - UINT8 ucEndBusNum; - UINT32 Reserved2; -}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; - -typedef struct -{ - EFI_ACPI_DESCRIPTION_HEADER Header; - UINT64 Reserved1; -}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; - -typedef struct -{ - EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3]; -}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; -#pragma pack() - -EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= -{ - { - { - EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - ACPI_5_0_MCFG_VERSION, - 0x00, // Checksum will be updated at runtime - {EFI_ACPI_ARM_OEM_ID}, - EFI_ACPI_ARM_OEM_TABLE_ID, - EFI_ACPI_ARM_OEM_REVISION, - EFI_ACPI_ARM_CREATOR_ID, - EFI_ACPI_ARM_CREATOR_REVISION - }, - 0x0000000000000000, //Reserved - }, - { - - { - 0xb0000000, //Base Address - 0x0, //Segment Group Number - 0x0, //Start Bus Number - 0x1f, //End Bus Number - 0x00000000, //Reserved - }, - { - 0xb0000000, //Base Address - 0x1, //Segment Group Number - 0xe0, //Start Bus Number - 0xff, //End Bus Number - 0x00000000, //Reserved - }, - { - 0xa0000000, //Base Address - 0x2, //Segment Group Number - 0x80, //Start Bus Number - 0x9f, //End Bus Number - 0x00000000, //Reserved - }, - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl deleted file mode 100644 index d8d453a..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ /dev/null @@ -1,562 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -Scope(_SB) -{ - Device (MDIO) - { - OperationRegion(CLKR, SystemMemory, 0x60000338, 8) - Field(CLKR, DWordAcc, NoLock, Preserve) { - CLKE, 1, // clock enable - , 31, - CLKD, 1, // clode disable - , 31, - } - OperationRegion(RSTR, SystemMemory, 0x60000A38, 8) - Field(RSTR, DWordAcc, NoLock, Preserve) { - RSTE, 1, // reset - , 31, - RSTD, 1, // de-reset - , 31, - } - - Name(_HID, "HISI0141") - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000) - }) - - Method(_RST, 0, Serialized) { - Store (0x1, RSTE) - Sleep (10) - Store (0x1, CLKD) - Sleep (10) - Store (0x1, RSTD) - Sleep (10) - Store (0x1, CLKE) - Sleep (10) - } - } - - Device (DSF0) - { - OperationRegion(H3SR, SystemMemory, 0xC0000184, 4) - Field(H3SR, DWordAcc, NoLock, Preserve) { - H3ST, 1, - , 31, //RESERVED - } - OperationRegion(H4SR, SystemMemory, 0xC0000194, 4) - Field(H4SR, DWordAcc, NoLock, Preserve) { - H4ST, 1, - , 31, //RESERVED - } - // DSAF RESET - OperationRegion(DRER, SystemMemory, 0xC0000A00, 8) - Field(DRER, DWordAcc, NoLock, Preserve) { - DRTE, 1, - , 31, //RESERVED - DRTD, 1, - , 31, //RESERVED - } - // NT RESET - OperationRegion(NRER, SystemMemory, 0xC0000A08, 8) - Field(NRER, DWordAcc, NoLock, Preserve) { - NRTE, 1, - , 31, //RESERVED - NRTD, 1, - , 31, //RESERVED - } - // XGE RESET - OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) - Field(XRER, DWordAcc, NoLock, Preserve) { - XRTE, 31, - , 1, //RESERVED - XRTD, 31, - , 1, //RESERVED - } - - // GE RESET - OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) - Field(GRTR, DWordAcc, NoLock, Preserve) { - GR0E, 30, - , 2, //RESERVED - GR0D, 30, - , 2, //RESERVED - GR1E, 18, - , 14, //RESERVED - GR1D, 18, - , 14, //RESERVED - } - // PPE RESET - OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) - Field(PRTR, DWordAcc, NoLock, Preserve) { - PRTE, 10, - , 22, //RESERVED - PRTD, 10, - , 22, //RESERVED - } - - // RCB PPE COM RESET - OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8) - Field(RRTR, DWordAcc, NoLock, Preserve) { - RRTE, 1, - , 31, //RESERVED - RRTD, 1, - , 31, //RESERVED - } - - // Hilink access sel cfg reg - OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) - Field(HSER, DWordAcc, NoLock, Preserve) { - HSEL, 2, // hilink_access_sel & hilink_access_wr_pul - , 30, // RESERVED - } - - // Serdes - OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) - Field(H4LR, DWordAcc, NoLock, Preserve) { - H4L0, 16, // port0 - , 16, //RESERVED - Offset (0x400), - H4L1, 16, // port1 - , 16, //RESERVED - Offset (0x800), - H4L2, 16, // port2 - , 16, //RESERVED - Offset (0xc00), - H4L3, 16, // port3 - , 16, //RESERVED - } - OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) - Field(H3LR, DWordAcc, NoLock, Preserve) { - H3L2, 16, // port4 - , 16, //RESERVED - Offset (0x400), - H3L3, 16, // port5 - , 16, //RESERVED - } - Name (_HID, "HISI00B2") - Name (_CCA, 1) // Cache-coherent controller - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) - Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"mode", "6port-16rss"}, - Package () {"buf-size", 4096}, - Package () {"desc-num", 1024}, - Package () {"interrupt-parent", Package() {_SB.MBI3}}, - } - }) - - //reset XGE port - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XRST, 2, Serialized) { - ShiftLeft (0x2082082, Arg0, Local0) - Or (Local0, 0x1, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset XGE core - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XCRT, 2, Serialized) { - ShiftLeft (0x2080, Arg0, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset GE port - //Arg0 : GE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(GRST, 2, Serialized) { - If (LLessEqual (Arg0, 5)) { - //Service port - ShiftLeft (0x2082082, Arg0, Local0) - ShiftLeft (0x1, Arg0, Local1) - - If (LEqual (Arg1, 0)) { - Store(Local1, GR1E) - Store(Local0, GR0E) - } Else { - Store(Local0, GR0D) - Store(Local1, GR1D) - } - } - } - - //reset PPE port - //Arg0 : PPE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(PRST, 2, Serialized) { - ShiftLeft (0x1, Arg0, Local0) - If (LEqual (Arg1, 0)) { - Store(Local0, PRTE) - } Else { - Store(Local0, PRTD) - } - } - - // Set Serdes Loopback - //Arg0 : port - //Arg1 : 0 disable, 1 enable - Method(SRLP, 2, Serialized) { - ShiftLeft (Arg1, 10, Local0) - Switch (ToInteger(Arg0)) - { - case (0x0){ - Store (0, HSEL) - Store (H4L0, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L0) - } - case (0x1){ - Store (0, HSEL) - Store (H4L1, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L1) - } - case (0x2){ - Store (0, HSEL) - Store (H4L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L2) - } - case (0x3){ - Store (0, HSEL) - Store (H4L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L3) - } - case (0x4){ - Store (3, HSEL) - Store (H3L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L2) - } - case (0x5){ - Store (3, HSEL) - Store (H3L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L3) - } - } - } - - //Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) - //Arg1 : port - //Arg2 : 0 disable, 1 enable - Method(DRST, 3, Serialized) - { - Switch (ToInteger(Arg0)) - { - //DSAF reset - case (0x1) - { - Store (Arg2, Local0) - If (LEqual (Local0, 0)) - { - Store (0x1, DRTE) - Store (0x1, NRTE) - Sleep (10) - Store (0x1, RRTE) - } - Else - { - Store (0x1, DRTD) - Store (0x1, NRTD) - Sleep (10) - Store (0x1, RRTD) - } - } - //Reset PPE port - case (0x2) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - PRST (Local0, Local1) - } - - //Reset XGE core - case (0x3) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XCRT (Local0, Local1) - } - //Reset XGE port - case (0x4) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XRST (Local0, Local1) - } - - //Reset GE port - case (0x5) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - GRST (Local0, Local1) - } - } - } - - // _DSM Device Specific Method - // - // Arg0: UUID Unique function identifier - // Arg1: Integer Revision Level - // Arg2: Integer Function Index - // 0 : Return Supported Functions bit mask - // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) - // Arg3[1] : port index in dsaf - // Arg3[2] : 0 reset, 1 cancle reset - // 2 : Set Serdes Loopback - // Arg3[0] : port - // Arg3[1] : 0 disable, 1 enable - // 3 : LED op set - // Arg3[0] : op type - // Arg3[1] : port - // Arg3[2] : para - // 4 : Get port type (GE or XGE) - // Arg3[0] : port index in dsaf - // Return : 0 GE, 1 XGE - // 5 : Get sfp status - // Arg3[0] : port index in dsaf - // Return : 0 no sfp, 1 have sfp - // Arg3: Package Parameters - Method (_DSM, 4, Serialized) - { - If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) - { - If (LEqual (Arg1, 0x00)) - { - Switch (ToInteger(Arg2)) - { - case (0x0) - { - Return (Buffer () {0x3F}) - } - - //Reset Sequence - case (0x1) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - Store (DeRefOf (Index (Arg3, 2)), Local2) - DRST (Local0, Local1, Local2) - } - - //Set Serdes Loopback - case (0x2) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - SRLP (Local0, Local1) - } - - //LED op set - case (0x3) - { - - } - - // Get port type (GE or XGE) - case (0x4) - { - Store (0, Local1) - Store (DeRefOf (Index (Arg3, 0)), Local0) - If (LLessEqual (Local0, 3)) - { - // mac0: Hilink4 Lane0 - // mac1: Hilink4 Lane1 - // mac2: Hilink4 Lane2 - // mac3: Hilink4 Lane3 - Store (H4ST, Local1) - } - ElseIf (LLessEqual (Local0, 5)) - { - // mac4: Hilink3 Lane2 - // mac5: Hilink3 Lane3 - Store (H3ST, Local1) - } - - Return (Local1) - } - - //Get sfp status - case (0x5) - { - - } - } - } - } - Return (Buffer() {0x00}) - } - Device (PRT0) - { - Name (_ADR, 0x0) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 0}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT1) - { - Name (_ADR, 0x1) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 1}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT4) - { - Name (_ADR, 0x4) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 4}, - Package () {"phy-mode", "sgmii"}, - Package () {"phy-addr", 0}, - Package () {"mdio-node", Package (){_SB.MDIO}}, - Package () {"media-type", "copper"}, - } - }) - } - Device (PRT5) - { - Name (_ADR, 0x5) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 5}, - Package () {"phy-mode", "sgmii"}, - Package () {"phy-addr", 1}, - Package () {"mdio-node", Package (){_SB.MDIO}}, - Package () {"media-type", "copper"}, - } - }) - } - } - Device (ETH4) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){_SB.DSF0}}, - Package () {"port-idx-in-ae", 4}, - } - }) - } - Device (ETH5) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){_SB.DSF0}}, - Package () {"port-idx-in-ae", 5}, - } - }) - } - Device (ETH0) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){_SB.DSF0}}, - Package () {"port-idx-in-ae", 0}, - } - }) - } - Device (ETH1) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){_SB.DSF0}}, - Package () {"port-idx-in-ae", 1}, - } - }) - } - -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl deleted file mode 100644 index 4eaa073..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Mbig.asl +++ /dev/null @@ -1,125 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -Scope(_SB) -{ - // Mbi-gen pcie subsys - Device(MBI0) { - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 2} - } - }) - } - - // Mbi-gen sas1 intc - Device(MBI1) { - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - - Device(MBI2) { // Mbi-gen sas2 intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - - Device(MBI3) { // Mbi-gen dsa0 srv intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 409} - } - }) - } - - Device(MBI4) { // Mbi-gen dsa1 dbg0 intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 9} - } - }) - } - - Device(MBI5) { // Mbi-gen dsa2 dbg1 intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 9} - } - }) - } - - Device(MBI6) { // Mbi-gen dsa sas0 intc - Name(_HID, "HISI0152") - Name(_CID, "MBIGen") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) - }) - Name(_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"num-pins", 128} - } - }) - } - -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl deleted file mode 100644 index 573c0a3..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Pci.asl +++ /dev/null @@ -1,261 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -//#include "ArmPlatform.h" -Scope(_SB) -{ - // PCIe Root bus - Device (PCI0) - { - Name (_HID, "HISI0080") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 0) // Segment of this Root complex - Name(_BBN, 0) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x1f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xb2000000, // Min Base Address pci address - 0xb7feffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xb7ff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - - Device (RES0) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000) - }) - } - - OperationRegion(SCTR, SystemMemory, 0xa009131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } - } // Device(PCI0) - - // PCIe Root bus - Device (PCI1) - { - Name (_HID, "HISI0080") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 1) // Segment of this Root complex - Name(_BBN, 0xe0) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0xe0, // AddressMinimum - Minimum Bus Number - 0xff, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xb8000000, // Min Base Address pci address - 0xbdfeffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xbdff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - - Device (RES1) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) - }) - } - - OperationRegion(SCTR, SystemMemory, 0xa020131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { - - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } - } // Device(PCI1) - - // PCIe Root bus - Device (PCI2) - { - Name (_HID, "HISI0080") // PCI Express Root Bridge - Name (_CID, "PNP0A03") // Compatible PCI Root Bridge - Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number - Name(_CCA, 1) - Method (_CRS, 0, Serialized) { // Root complex resources - Name (RBUF, ResourceTemplate () { - WordBusNumber ( // Bus numbers assigned to this root - ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x9f, // AddressMaximum - Maximum Bus Number - 0, // AddressTranslation - Set to 0 - 0x20 // RangeLength - Number of Busses - ) - QWordMemory ( // 64-bit BAR Windows - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - Cacheable, - ReadWrite, - 0x0, // Granularity - 0xaa000000, // Min Base Address - 0xaffeffff, // Max Base Address - 0x0, // Translate - 0x5ff0000 // Length - ) - QWordIO ( - ResourceProducer, - MinFixed, - MaxFixed, - PosDecode, - EntireRange, - 0x0, // Granularity - 0x0, // Min Base Address - 0xffff, // Max Base Address - 0xafff0000, // Translate - 0x10000 // Length - ) - }) // Name(RBUF) - Return (RBUF) - } // Method(_CRS) - - Device (RES2) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) - }) - } - - OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) - { - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } - } // Device(PCI2) -} - diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl deleted file mode 100644 index ce8ccd6..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Sas.asl +++ /dev/null @@ -1,247 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> - Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -Scope(_SB) -{ - Device(SAS0) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 64,65,66,67,68, - 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) - { - 601,602,603,604, - 605,606,607,608,609, - 610,611,612,613,614, - 615,616,617,618,619, - 620,621,622,623,624, - 625,626,627,628,629, - 630,631,632, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI6}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x338), - CLK, 32, - CLKD, 32, - Offset (0xa60), - RST, 32, - DRST, 32, - Offset (0x5a30), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - } - - Device(SAS1) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 64,65,66,67,68, - 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) - { - 576,577,578,579,580, - 581,582,583,584,585, - 586,587,588,589,590, - 591,592,593,594,595, - 596,597,598,599,600, - 601,602,603,604,605, - 606,607, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI1}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - Package () {"hip06-sas-v2-quirk-amt", 1}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x318), - CLK, 32, - CLKD, 32, - Offset (0xa18), - RST, 32, - DRST, 32, - Offset (0x5a0c), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - } - - Device(SAS2) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) - - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 192,193,194,195,196, - 197,198,199,200,201, - 202,203,204,205,206, - 207,208,209,210,211, - 212,213,214,215,216, - 217,218,219,220,221, - 222,223,224,225,226, - 227,228,229,230,231, - 232,233,234,235,236, - 237,238,239,240,241, - 242,243,244,245,246, - 247,248,249,250,251, - 252,253,254,255,256, - 257,258,259,260,261, - 262,263,264,265,266, - 267,268,269,270,271, - 272,273,274,275,276, - 277,278,279,280,281, - 282,283,284,285,286, - 287, - } - - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) - { - 608,609,610,611, - 612,613,614,615,616, - 617,618,619,620,621, - 622,623,624,625,626, - 627,628,629,630,631, - 632,633,634,635,636, - 637,638,639, - } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI2}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) - - OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) - Field (CTL, AnyAcc, NoLock, Preserve) - { - Offset (0x3a8), - CLK, 32, - CLKD, 32, - Offset (0xae0), - RST, 32, - DRST, 32, - Offset (0x5a70), - STS, 32, - } - - Method (_RST, 0x0, Serialized) - { - Store(0x7ffff, RST) - Store(0x7ffff, CLKD) - Sleep(1) - Store(0x7ffff, DRST) - Store(0x7ffff, CLK) - Sleep(1) - } - } - -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl deleted file mode 100644 index 28ba03d..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Usb.asl +++ /dev/null @@ -1,136 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> - Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -//#include "ArmPlatform.h" -Scope(_SB) -{ - Device (USB0) - { - Name (_HID, "PNP0D20") // _HID: Hardware ID - Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID - Name (_CCA, One) // _CCA: Cache Coherency Attribute - Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings - { - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, - 0xa7020000, // Address Base - 0x00010000, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { - 0x00000041, - } - }) - Return (RBUF) /* _SB_.USB0._CRS.RBUF */ - } - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () {"interrupt-parent",Package() {_SB.MBI0}} - } - }) - - Device (RHUB) - { - Name (_ADR, Zero) // _ADR: Address - Device (PRT1) - { - Name (_ADR, One) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - Zero, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0, - PLD_VerticalOffset = 0x0, - PLD_HorizontalOffset = 0x0) - - }) - } - - Device (PRT2) - { - Name (_ADR, 0x02) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - - Device (PRT3) - { - Name (_ADR, 0x03) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - - Device (PRT4) - { - Name (_ADR, 0x04) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - 0xFF, - Zero, - Zero - }) - } - } - } -} - diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl deleted file mode 100644 index 06c05aa..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/DsdtHi1610.asl +++ /dev/null @@ -1,29 +0,0 @@ -/** @file - Differentiated System Description Table Fields (DSDT) - - Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> - Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> - Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ - -**/ - -#include "Pv660Platform.h" - -DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI-EVB", EFI_ACPI_ARM_OEM_REVISION) { - include ("Lpc.asl") - include ("D03Mbig.asl") - include ("CPU.asl") - include ("D03Usb.asl") - include ("D03Hns.asl") - include ("D03Sas.asl") - include ("D03Pci.asl") -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl deleted file mode 100644 index 0965afc..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Lpc.asl +++ /dev/null @@ -1,25 +0,0 @@ -/** @file -* -* Copyright (c) 2016 Hisilicon Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -// -// LPC -// - -Device (LPC0) -{ - Name(_HID, "HISI0191") // HiSi LPC - Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) - }) -} diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc deleted file mode 100644 index 6e8557e..0000000 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc +++ /dev/null @@ -1,128 +0,0 @@ -/** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ -* -**/ - -#include "Pv660Platform.h" - -#include <Library/AcpiLib.h> -#include <Library/ArmLib.h> -#include <Library/PcdLib.h> -#include <IndustryStandard/Acpi.h> -#include <Library/AcpiNextLib.h> - -// Differs from Juno, we have another affinity level beyond cluster and core -// 0x20000 is only for socket 0 -#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) - -// -// Multiple APIC Description Table -// -#pragma pack (1) - -typedef struct { - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1]; -} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; - -#pragma pack () - -EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { - { - ARM_ACPI_HEADER ( - EFI_ACPI_1_0_APIC_SIGNATURE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION - ), - // - // MADT specific fields - // - 0, // LocalApicAddress - 0, // Flags - }, - { - // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, - // GsivId, GicRBase, Mpidr) - // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of - // ACPI v5.1). - // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses - // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), - }, - - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), - { - EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000), - } -}; - -// -// Reference the table being generated to prevent the optimizer from removing the -// data structure from the executable -// -VOID* CONST ReferenceAcpiTable = &Madt;
Move D03 ACPI tables from Hisilicon/Pv660/Pv660AcpiTables/ to Hisilicon/Hi1610/Hi1610AcpiTables/
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf | 56 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 337 ++++++++++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 85 ++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl | 88 ++++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 36 ++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 562 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 125 +++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 261 ++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 247 +++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 136 +++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 29 ++ .../Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 67 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 91 ++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 96 ++++ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 48 ++ .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 128 +++++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc | 81 +++ Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc | 115 +++++ Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- 21 files changed, 2615 insertions(+), 2 deletions(-) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf new file mode 100644 index 0000000..b6be3d9 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf @@ -0,0 +1,56 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Hi1610AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt/DsdtHi1610.asl + Facs.aslc + Fadt.aslc + Gtdt.aslc + MadtHi1610.aslc + D03Mcfg.aslc + D03Iort.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl new file mode 100644 index 0000000..e02b4d5 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -0,0 +1,337 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20151124-64 + * Copyright (c) 2000 - 2015 Intel Corporation + * + * Template for [IORT] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 0000029e +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HISI1610" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124 + +[0004] Node Count : 00000008 +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00 + +/* ITS 0, for dsa */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 + +/* mbi-gen dsa mbi0 - usb, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0017] Device Name : "_SB_.MBI0" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040080 // device id +[0004] Output Reference : 00000034 // point to its dsa +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi1 - sas1, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI1" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi2 - sas2, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI2" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040040 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi3 - dsa0, srv named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI3" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040800 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI4" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1c +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI5" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1d +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa mbi6 - dsa sas0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI6" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040900 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* RC 0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000000 + +[0004] Input base : 00000000 +[0004] ID Count : 00002000 +[0004] Output Base : 00000000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* RC 1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000001 + +[0004] Input base : 0000e000 +[0004] ID Count : 00002000 +[0004] Output Base : 0000e000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* RC 2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002 + +[0004] Input base : 00008000 +[0004] ID Count : 00002000 +[0004] Output Base : 00008000 +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc new file mode 100644 index 0000000..ed47a44 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2016 Hisilicon Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + */ + +#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h" + +#define ACPI_5_0_MCFG_VERSION 0x1 + +#pragma pack(1) +typedef struct +{ + UINT64 ullBaseAddress; + UINT16 usSegGroupNum; + UINT8 ucStartBusNum; + UINT8 ucEndBusNum; + UINT32 Reserved2; +}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; + +typedef struct +{ + EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3]; +}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack() + +EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{ + { + { + EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_5_0_MCFG_VERSION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION + }, + 0x0000000000000000, //Reserved + }, + { + + { + 0xb0000000, //Base Address + 0x0, //Segment Group Number + 0x0, //Start Bus Number + 0x1f, //End Bus Number + 0x00000000, //Reserved + }, + { + 0xb0000000, //Base Address + 0x1, //Segment Group Number + 0xe0, //Start Bus Number + 0xff, //End Bus Number + 0x00000000, //Reserved + }, + { + 0xa0000000, //Base Address + 0x2, //Segment Group Number + 0x80, //Start Bus Number + 0x9f, //End Bus Number + 0x00000000, //Reserved + }, + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000..e995295 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,88 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + // + // A57x16 Processor declaration + // + Device(CPU0) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + Device(CPU1) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + Device(CPU2) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + Device(CPU3) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + Device(CPU4) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + Device(CPU5) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + Device(CPU6) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + Device(CPU7) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } + Device(CPU8) { + Name(_HID, "ACPI0007") + Name(_UID, 8) + } + Device(CPU9) { + Name(_HID, "ACPI0007") + Name(_UID, 9) + } + Device(CP10) { + Name(_HID, "ACPI0007") + Name(_UID, 10) + } + Device(CP11) { + Name(_HID, "ACPI0007") + Name(_UID, 11) + } + Device(CP12) { + Name(_HID, "ACPI0007") + Name(_UID, 12) + } + Device(CP13) { + Name(_HID, "ACPI0007") + Name(_UID, 13) + } + Device(CP14) { + Name(_HID, "ACPI0007") + Name(_UID, 14) + } + Device(CP15) { + Name(_HID, "ACPI0007") + Name(_UID, 15) + } +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000..3bcc5fb --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl @@ -0,0 +1,36 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + Device(COM0) { + Name(_HID, "HISI0031") //it is not 16550 compatible + Name(_CID, "8250dw") + Name(_UID, Zero) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x80300000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-frequency", 200000000}, + } + }) + } +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl new file mode 100644 index 0000000..d8d453a --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -0,0 +1,562 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + Device (MDIO) + { + OperationRegion(CLKR, SystemMemory, 0x60000338, 8) + Field(CLKR, DWordAcc, NoLock, Preserve) { + CLKE, 1, // clock enable + , 31, + CLKD, 1, // clode disable + , 31, + } + OperationRegion(RSTR, SystemMemory, 0x60000A38, 8) + Field(RSTR, DWordAcc, NoLock, Preserve) { + RSTE, 1, // reset + , 31, + RSTD, 1, // de-reset + , 31, + } + + Name(_HID, "HISI0141") + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000) + }) + + Method(_RST, 0, Serialized) { + Store (0x1, RSTE) + Sleep (10) + Store (0x1, CLKD) + Sleep (10) + Store (0x1, RSTD) + Sleep (10) + Store (0x1, CLKE) + Sleep (10) + } + } + + Device (DSF0) + { + OperationRegion(H3SR, SystemMemory, 0xC0000184, 4) + Field(H3SR, DWordAcc, NoLock, Preserve) { + H3ST, 1, + , 31, //RESERVED + } + OperationRegion(H4SR, SystemMemory, 0xC0000194, 4) + Field(H4SR, DWordAcc, NoLock, Preserve) { + H4ST, 1, + , 31, //RESERVED + } + // DSAF RESET + OperationRegion(DRER, SystemMemory, 0xC0000A00, 8) + Field(DRER, DWordAcc, NoLock, Preserve) { + DRTE, 1, + , 31, //RESERVED + DRTD, 1, + , 31, //RESERVED + } + // NT RESET + OperationRegion(NRER, SystemMemory, 0xC0000A08, 8) + Field(NRER, DWordAcc, NoLock, Preserve) { + NRTE, 1, + , 31, //RESERVED + NRTD, 1, + , 31, //RESERVED + } + // XGE RESET + OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) + Field(XRER, DWordAcc, NoLock, Preserve) { + XRTE, 31, + , 1, //RESERVED + XRTD, 31, + , 1, //RESERVED + } + + // GE RESET + OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) + Field(GRTR, DWordAcc, NoLock, Preserve) { + GR0E, 30, + , 2, //RESERVED + GR0D, 30, + , 2, //RESERVED + GR1E, 18, + , 14, //RESERVED + GR1D, 18, + , 14, //RESERVED + } + // PPE RESET + OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) + Field(PRTR, DWordAcc, NoLock, Preserve) { + PRTE, 10, + , 22, //RESERVED + PRTD, 10, + , 22, //RESERVED + } + + // RCB PPE COM RESET + OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8) + Field(RRTR, DWordAcc, NoLock, Preserve) { + RRTE, 1, + , 31, //RESERVED + RRTD, 1, + , 31, //RESERVED + } + + // Hilink access sel cfg reg + OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) + Field(HSER, DWordAcc, NoLock, Preserve) { + HSEL, 2, // hilink_access_sel & hilink_access_wr_pul + , 30, // RESERVED + } + + // Serdes + OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) + Field(H4LR, DWordAcc, NoLock, Preserve) { + H4L0, 16, // port0 + , 16, //RESERVED + Offset (0x400), + H4L1, 16, // port1 + , 16, //RESERVED + Offset (0x800), + H4L2, 16, // port2 + , 16, //RESERVED + Offset (0xc00), + H4L3, 16, // port3 + , 16, //RESERVED + } + OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) + Field(H3LR, DWordAcc, NoLock, Preserve) { + H3L2, 16, // port4 + , 16, //RESERVED + Offset (0x400), + H3L3, 16, // port5 + , 16, //RESERVED + } + Name (_HID, "HISI00B2") + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) + Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"mode", "6port-16rss"}, + Package () {"buf-size", 4096}, + Package () {"desc-num", 1024}, + Package () {"interrupt-parent", Package() {_SB.MBI3}}, + } + }) + + //reset XGE port + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XRST, 2, Serialized) { + ShiftLeft (0x2082082, Arg0, Local0) + Or (Local0, 0x1, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset XGE core + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XCRT, 2, Serialized) { + ShiftLeft (0x2080, Arg0, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset GE port + //Arg0 : GE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(GRST, 2, Serialized) { + If (LLessEqual (Arg0, 5)) { + //Service port + ShiftLeft (0x2082082, Arg0, Local0) + ShiftLeft (0x1, Arg0, Local1) + + If (LEqual (Arg1, 0)) { + Store(Local1, GR1E) + Store(Local0, GR0E) + } Else { + Store(Local0, GR0D) + Store(Local1, GR1D) + } + } + } + + //reset PPE port + //Arg0 : PPE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(PRST, 2, Serialized) { + ShiftLeft (0x1, Arg0, Local0) + If (LEqual (Arg1, 0)) { + Store(Local0, PRTE) + } Else { + Store(Local0, PRTD) + } + } + + // Set Serdes Loopback + //Arg0 : port + //Arg1 : 0 disable, 1 enable + Method(SRLP, 2, Serialized) { + ShiftLeft (Arg1, 10, Local0) + Switch (ToInteger(Arg0)) + { + case (0x0){ + Store (0, HSEL) + Store (H4L0, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L0) + } + case (0x1){ + Store (0, HSEL) + Store (H4L1, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L1) + } + case (0x2){ + Store (0, HSEL) + Store (H4L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L2) + } + case (0x3){ + Store (0, HSEL) + Store (H4L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L3) + } + case (0x4){ + Store (3, HSEL) + Store (H3L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L2) + } + case (0x5){ + Store (3, HSEL) + Store (H3L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L3) + } + } + } + + //Reset + //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) + //Arg1 : port + //Arg2 : 0 disable, 1 enable + Method(DRST, 3, Serialized) + { + Switch (ToInteger(Arg0)) + { + //DSAF reset + case (0x1) + { + Store (Arg2, Local0) + If (LEqual (Local0, 0)) + { + Store (0x1, DRTE) + Store (0x1, NRTE) + Sleep (10) + Store (0x1, RRTE) + } + Else + { + Store (0x1, DRTD) + Store (0x1, NRTD) + Sleep (10) + Store (0x1, RRTD) + } + } + //Reset PPE port + case (0x2) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + PRST (Local0, Local1) + } + + //Reset XGE core + case (0x3) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XCRT (Local0, Local1) + } + //Reset XGE port + case (0x4) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XRST (Local0, Local1) + } + + //Reset GE port + case (0x5) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + GRST (Local0, Local1) + } + } + } + + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // 0 : Return Supported Functions bit mask + // 1 : Reset Sequence + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) + // Arg3[1] : port index in dsaf + // Arg3[2] : 0 reset, 1 cancle reset + // 2 : Set Serdes Loopback + // Arg3[0] : port + // Arg3[1] : 0 disable, 1 enable + // 3 : LED op set + // Arg3[0] : op type + // Arg3[1] : port + // Arg3[2] : para + // 4 : Get port type (GE or XGE) + // Arg3[0] : port index in dsaf + // Return : 0 GE, 1 XGE + // 5 : Get sfp status + // Arg3[0] : port index in dsaf + // Return : 0 no sfp, 1 have sfp + // Arg3: Package Parameters + Method (_DSM, 4, Serialized) + { + If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) + { + If (LEqual (Arg1, 0x00)) + { + Switch (ToInteger(Arg2)) + { + case (0x0) + { + Return (Buffer () {0x3F}) + } + + //Reset Sequence + case (0x1) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + Store (DeRefOf (Index (Arg3, 2)), Local2) + DRST (Local0, Local1, Local2) + } + + //Set Serdes Loopback + case (0x2) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + SRLP (Local0, Local1) + } + + //LED op set + case (0x3) + { + + } + + // Get port type (GE or XGE) + case (0x4) + { + Store (0, Local1) + Store (DeRefOf (Index (Arg3, 0)), Local0) + If (LLessEqual (Local0, 3)) + { + // mac0: Hilink4 Lane0 + // mac1: Hilink4 Lane1 + // mac2: Hilink4 Lane2 + // mac3: Hilink4 Lane3 + Store (H4ST, Local1) + } + ElseIf (LLessEqual (Local0, 5)) + { + // mac4: Hilink3 Lane2 + // mac5: Hilink3 Lane3 + Store (H3ST, Local1) + } + + Return (Local1) + } + + //Get sfp status + case (0x5) + { + + } + } + } + } + Return (Buffer() {0x00}) + } + Device (PRT0) + { + Name (_ADR, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 0}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT1) + { + Name (_ADR, 0x1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 1}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT4) + { + Name (_ADR, 0x4) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 4}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 0}, + Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, + } + }) + } + Device (PRT5) + { + Name (_ADR, 0x5) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 5}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 1}, + Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, + } + }) + } + } + Device (ETH4) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 4}, + } + }) + } + Device (ETH5) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 5}, + } + }) + } + Device (ETH0) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 0}, + } + }) + } + Device (ETH1) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 1}, + } + }) + } + +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl new file mode 100644 index 0000000..4eaa073 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -0,0 +1,125 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + // Mbi-gen pcie subsys + Device(MBI0) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 2} + } + }) + } + + // Mbi-gen sas1 intc + Device(MBI1) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + + Device(MBI2) { // Mbi-gen sas2 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + + Device(MBI3) { // Mbi-gen dsa0 srv intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 409} + } + }) + } + + Device(MBI4) { // Mbi-gen dsa1 dbg0 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 9} + } + }) + } + + Device(MBI5) { // Mbi-gen dsa2 dbg1 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 9} + } + }) + } + + Device(MBI6) { // Mbi-gen dsa sas0 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl new file mode 100644 index 0000000..573c0a3 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl @@ -0,0 +1,261 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +//#include "ArmPlatform.h" +Scope(_SB) +{ + // PCIe Root bus + Device (PCI0) + { + Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 0) // Segment of this Root complex + Name(_BBN, 0) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x0, // AddressMinimum - Minimum Bus Number + 0x1f, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x20 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xb2000000, // Min Base Address pci address + 0xb7feffff, // Max Base Address + 0x0, // Translate + 0x5ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0xb7ff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000) + }) + } + + OperationRegion(SCTR, SystemMemory, 0xa009131c, 4) + Field(SCTR, AnyAcc, NoLock, Preserve) { + LSTA, 32, + } + Method(_DSM, 0x4, Serialized) { + If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { + switch(ToInteger(Arg2)) + { + // Function 0: Return LinkStatus + case(0) { + Store (0, Local0) + Store (LSTA, Local0) + Return (Local0) + } + default { + } + } + } + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return(Buffer(){0}) + } + } // Device(PCI0) + + // PCIe Root bus + Device (PCI1) + { + Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 1) // Segment of this Root complex + Name(_BBN, 0xe0) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0xe0, // AddressMinimum - Minimum Bus Number + 0xff, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x20 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xb8000000, // Min Base Address pci address + 0xbdfeffff, // Max Base Address + 0x0, // Translate + 0x5ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0xbdff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + + Device (RES1) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) + }) + } + + OperationRegion(SCTR, SystemMemory, 0xa020131c, 4) + Field(SCTR, AnyAcc, NoLock, Preserve) { + LSTA, 32, + } + Method(_DSM, 0x4, Serialized) { + If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { + + switch(ToInteger(Arg2)) + { + // Function 0: Return LinkStatus + case(0) { + Store (0, Local0) + Store (LSTA, Local0) + Return (Local0) + } + default { + } + } + } + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return(Buffer(){0}) + } + } // Device(PCI1) + + // PCIe Root bus + Device (PCI2) + { + Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 2) // Segment of this Root complex + Name(_BBN, 0x80) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x80, // AddressMinimum - Minimum Bus Number + 0x9f, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x20 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xaa000000, // Min Base Address + 0xaffeffff, // Max Base Address + 0x0, // Translate + 0x5ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0xafff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) + }) + } + + OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4) + Field(SCTR, AnyAcc, NoLock, Preserve) { + LSTA, 32, + } + Method(_DSM, 0x4, Serialized) { + If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) + { + switch(ToInteger(Arg2)) + { + // Function 0: Return LinkStatus + case(0) { + Store (0, Local0) + Store (LSTA, Local0) + Return (Local0) + } + default { + } + } + } + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return(Buffer(){0}) + } + } // Device(PCI2) +} + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl new file mode 100644 index 0000000..ce8ccd6 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -0,0 +1,247 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + Device(SAS0) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI6}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x338), + CLK, 32, + CLKD, 32, + Offset (0xa60), + RST, 32, + DRST, 32, + Offset (0x5a30), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + + Device(SAS1) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) + + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI1}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + Package () {"hip06-sas-v2-quirk-amt", 1}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x318), + CLK, 32, + CLKD, 32, + Offset (0xa18), + RST, 32, + DRST, 32, + Offset (0x5a0c), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + + Device(SAS2) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) + + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI2}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x3a8), + CLK, 32, + CLKD, 32, + Offset (0xae0), + RST, 32, + DRST, 32, + Offset (0x5a70), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl new file mode 100644 index 0000000..28ba03d --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -0,0 +1,136 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +//#include "ArmPlatform.h" +Scope(_SB) +{ + Device (USB0) + { + Name (_HID, "PNP0D20") // _HID: Hardware ID + Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xa7020000, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + Return (RBUF) /* _SB_.USB0._CRS.RBUF */ + } + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"interrupt-parent",Package() {_SB.MBI0}} + } + }) + + Device (RHUB) + { + Name (_ADR, Zero) // _ADR: Address + Device (PRT1) + { + Name (_ADR, One) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + Zero, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0x0, + PLD_HorizontalOffset = 0x0) + + }) + } + + Device (PRT2) + { + Name (_ADR, 0x02) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + + Device (PRT3) + { + Name (_ADR, 0x03) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + + Device (PRT4) + { + Name (_ADR, 0x04) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + } + } +} + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl new file mode 100644 index 0000000..ca8b2dc --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -0,0 +1,29 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include "Hi1610Platform.h" + +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI1610", EFI_ACPI_ARM_OEM_REVISION) { + include ("Lpc.asl") + include ("D03Mbig.asl") + include ("CPU.asl") + include ("D03Usb.asl") + include ("D03Hns.asl") + include ("D03Sas.asl") + include ("D03Pci.asl") +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl new file mode 100644 index 0000000..0965afc --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl @@ -0,0 +1,25 @@ +/** @file +* +* Copyright (c) 2016 Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +// +// LPC +// + +Device (LPC0) +{ + Name(_HID, "HISI0191") // HiSi LPC + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) + }) +} diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc new file mode 100644 index 0000000..72cc66c --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc @@ -0,0 +1,67 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length + 0xA152, // UINT32 HardwareSignature + 0, // UINT32 FirmwareWakingVector + 0, // UINT32 GlobalLock + 0, // UINT32 Flags + 0, // UINT64 XFirmwareWakingVector + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] + EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] + 0, // UINT32 OspmFlags "Platform firmware must + // initialize this field to zero." + { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] + EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23] +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs; + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc new file mode 100644 index 0000000..5307041 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc @@ -0,0 +1,91 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Hi1610Platform.h" + +#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..4032382 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -0,0 +1,96 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Hi1610Platform.h" + +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT]; +} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + ARM_ACPI_HEADER( + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress +#ifdef notyet + PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, + { + EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), + 0, 0, 0, 0), + EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + 0, 0, 0, 0) + } +#else /* !notyet */ + 0, 0 + } +#endif + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h new file mode 100644 index 0000000..e8a1577 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + + +#ifndef _HI1610_PLATFORM_H_ +#define _HI1610_PLATFORM_H_ + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','1','6','1','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define HI1610_WATCHDOG_COUNT 2 + +#endif diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc new file mode 100644 index 0000000..7bebe8f --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc @@ -0,0 +1,128 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Hi1610Platform.h" + +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiNextLib.h> + +// Differs from Juno, we have another affinity level beyond cluster and core +// 0x20000 is only for socket 0 +#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) + +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1]; +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_1_0_APIC_SIGNATURE, + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // GsivId, GicRBase, Mpidr) + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of + // ACPI v5.1). + // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses + // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), + }, + + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), + { + EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000), + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc new file mode 100644 index 0000000..8b7aee4 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013 Linaro Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org +*/ + +#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h" + +#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014 + +#pragma pack(1) +typedef struct { + UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; +} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; + +typedef struct { + EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; + EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; + +} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE; +#pragma pack() + +// +// System Locality Information Table +// Please modify all values in Slit.h only. +// +EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { + { + { + EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE), + EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION, + }, + // + // Beginning of SLIT specific fields + // + EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, + }, + { + {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality 0 + {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality 1 + {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality 2 + {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality 3 + {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality 4 + {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality 5 + {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality 6 + {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality 7 + {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality 8 + {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality 9 + {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality 10 + {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality 11 + {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality 12 + {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality 13 + {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality 14 + {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality 15 + {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality 16 + {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality 17 + {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality 18 + {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality 19 + }, +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Slit; + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc new file mode 100644 index 0000000..99df1a4 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2013 Linaro Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org + * + * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +*/ + +#include <IndustryStandard/Acpi.h> +#include "Hi1610Platform.h" +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h> + + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT 4 +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 4 + + +#pragma pack(1) +typedef struct { + EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE Apic; + EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE Memory[2]; + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE GICC[16]; +} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE; + +#pragma pack() + + +// +// Static Resource Affinity Table definition +// +EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = { + { + {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE), + EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION}, + /*Reserved*/ + 0x00000001, // Reserved to be 1 for backward compatibility + EFI_ACPI_RESERVED_QWORD + }, + /**/ + { + 0x00, // Subtable Type:Processor Local APIC/SAPIC Affinity + sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE), //Length + 0x00, //Proximity Domain Low(8) + 0x00, //Apic ID + 0x00000001, //Flags + 0x00, //Local Sapic EID + {0,0,0}, //Proximity Domain High(24) + 0x00000000, //ClockDomain + }, + // + // + // Memory Affinity + // + { + EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001), + EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001), + }, + + /*Processor Local x2APIC Affinity*/ + //{ + // 0x02, // Subtable Type:Processor Local x2APIC Affinity + // sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE), + // {0,0}, //Reserved1 + // 0x00000000, //Proximity Domain + // 0x00000000, //Apic ID + // 0x00000001, //Flags + // 0x00000000, //Clock Domain + // {0,0,0,0}, //Reserved2 + //}, + + { + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 + EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000) //GICC Affinity Processor 15 + }, +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Srat; + diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index d8d8be1..80fdad4 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -414,7 +414,7 @@ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf + OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
# diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 38a5ef9..d101abb 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -235,7 +235,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf + INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
Use irq producer/consumer to represent the topology of device and mbi-gen:
We are using _PRS methd to indicate number of irq pins instead of num_pins in DT.
For mbi-gen, Device(MBI0) { Name(_HID, "HISI0152") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
Name (_PRS, ResourceTemplate() { Interrupt(ResourceProducer,...) {12,14,....} }) }
For devices,
Device(COM0) { Name(_HID, "ACPIIDxx") Name(_UID, Zero) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xb0030000, 0x10000) Interrupt(ResourceConsumer,..., "_SB.MBI0") {12} }) }
Update the DSDT as above.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hanjun Guo hanjun.guo@linaro.org Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 6 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 163 ++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 18 +-- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 4 files changed, 174 insertions(+), 15 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index d8d453a..9a7fdb0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -150,12 +150,12 @@ Scope(_SB) Name (_CRS, ResourceTemplate (){ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI3") { 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI3") { 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, @@ -170,7 +170,7 @@ Scope(_SB) 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI3") { 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 4eaa073..5456bd8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -22,6 +22,10 @@ Scope(_SB) Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) })
+ Name(_PRS, ResourceTemplate() { + Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42} + }) + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () @@ -38,6 +42,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, + } + }) + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () @@ -53,6 +95,44 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ) + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } + }) + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () @@ -68,6 +148,45 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) }) + +Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } +}) + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () @@ -76,7 +195,7 @@ Scope(_SB) } }) } - +/* Device(MBI4) { // Mbi-gen dsa1 dbg0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") @@ -106,13 +225,53 @@ Scope(_SB) } }) } - +*/ Device(MBI6) { // Mbi-gen dsa sas0 intc Name(_HID, "HISI0152") Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) }) + + Name(_PRS, ResourceTemplate() { + Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } + }) + + + Name(_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index ce8ccd6..de21b2d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -21,8 +21,8 @@ Scope(_SB) Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI6") + { 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79, @@ -45,7 +45,7 @@ Scope(_SB) 160, }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI6" ) { 601,602,603,604, 605,606,607,608,609, @@ -93,12 +93,12 @@ Scope(_SB)
Device(SAS1) { Name(_HID, "HISI0162") - Name(_CCA, 1) + Name(_CCA, 1) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) - { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI1") + { 64,65,66,67,68, 69,70,71,72,73, 75,76,77,78,79, @@ -121,7 +121,7 @@ Scope(_SB) 160, }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") { 576,577,578,579,580, 581,582,583,584,585, @@ -174,7 +174,7 @@ Scope(_SB) Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI2") { 192,193,194,195,196, 197,198,199,200,201, @@ -198,7 +198,7 @@ Scope(_SB) 287, }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI2") { 608,609,610,611, 612,613,614,615,616, diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 28ba03d..8429a4b 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -32,7 +32,7 @@ Scope(_SB) 0xa7020000, // Address Base 0x00010000, // Address Length ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI0") { 0x00000041, }
This patch adds the support of RoCE to the DSDT and IORT ACPI Tables. Following are the changes: 1. adds the support of a RoCE device to the HNS DSDT file. RoCE DEVICE node properties added are: * eth-handle * dsaf-handle * interrupt-parent * interrupt-names 2. Interrupt node 3. Addition of MbiGen RoCE "named-component" node in the IORT Table.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta salil.mehta@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 33 ++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 55 +++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 23 ++++++++- 3 files changed, 108 insertions(+), 3 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index e02b4d5..db98305 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -7,7 +7,7 @@ * Format: [ByteLength] FieldName : HexFieldValue */ [0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 0000029e +[0004] Table Length : 000002e4 [0001] Revision : 00 [0001] Checksum : BC [0006] Oem ID : "HISI " @@ -249,6 +249,37 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 1
+/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI7" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + /* RC 0 */ [0001] Type : 02 [0002] Length : 0034 diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 9a7fdb0..5997910 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -558,5 +558,58 @@ Scope(_SB) } }) } - + Device (ROCE) { + Name(_HID, "HISI00D1") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"eth-handle", Package () {_SB.ETH0, _SB.ETH1, 0, 0, _SB.ETH4, _SB.ETH5}}, + Package () {"dsaf-handle", Package (){_SB.DSF0}}, + Package () {"interrupt-names", Package() {"hns-roce-comp-0", + "hns-roce-comp-1", + "hns-roce-comp-2", + "hns-roce-comp-3", + "hns-roce-comp-4", + "hns-roce-comp-5", + "hns-roce-comp-6", + "hns-roce-comp-7", + "hns-roce-comp-8", + "hns-roce-comp-9", + "hns-roce-comp-10", + "hns-roce-comp-11", + "hns-roce-comp-12", + "hns-roce-comp-13", + "hns-roce-comp-14", + "hns-roce-comp-15", + "hns-roce-comp-16", + "hns-roce-comp-17", + "hns-roce-comp-18", + "hns-roce-comp-19", + "hns-roce-comp-20", + "hns-roce-comp-21", + "hns-roce-comp-22", + "hns-roce-comp-23", + "hns-roce-comp-24", + "hns-roce-comp-25", + "hns-roce-comp-26", + "hns-roce-comp-27", + "hns-roce-comp-28", + "hns-roce-comp-29", + "hns-roce-comp-30", + "hns-roce-comp-31", + "hns-roce-async", + "hns-roce-common"}}, + } + }) + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI7") + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) + } } diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 5456bd8..afd6b47 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -280,5 +280,26 @@ Name(_PRS, ResourceTemplate() { } }) } - + Device(MBI7) { // Mbi-gen roce intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name (_PRS, ResourceTemplate (){ + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 34} + } + }) + } }
In the Hip06 SoC, the RoCE Engine is part of the HiSilicon Network Subsystem and is dependent upon DSAF module. Therefore, certain functions like RESET are exposed through the common registers of HNS module which are memory-mapped by the HNS driver and currently can only be accessed through DT/syscon interface.
This patch adds the support of the RoCE Reset functionality through ACPI interface. This functionality would be exposed to the HiSilicon HNS Driver using the _DSM() ACPI Method. This method shall be called by the wrapper API in HNS driver. Further, HiSilicon RoCE driver shall call the HNS Driver exported RoCE Reset API.
In this patch, DSDT ACPI Table have been amended to facilitate such support.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta salil.mehta@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 79 +++++++++++++++++++++- 1 file changed, 77 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 5997910..57d28cf 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -115,6 +115,33 @@ Scope(_SB) , 31, //RESERVED }
+ // DSAF Channel RESET + OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8) + Field(DCRR, DWordAcc, NoLock, Preserve) { + DCRE, 1, + , 31, //RESERVED + DCRD, 1, + , 31, //RESERVED + } + + // RoCE RESET + OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8) + Field(RKRR, DWordAcc, NoLock, Preserve) { + RKRE, 1, + , 31, //RESERVED + RKRD, 1, + , 31, //RESERVED + } + + // RoCE Clock enable/disable + OperationRegion(RKCR, SystemMemory, 0xC0000328, 8) + Field(RKCR, DWordAcc, NoLock, Preserve) { + RCLE, 1, + , 31, //RESERVED + RCLD, 1, + , 31, //RESERVED + } + // Hilink access sel cfg reg OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) Field(HSER, DWordAcc, NoLock, Preserve) { @@ -254,6 +281,30 @@ Scope(_SB) } }
+ //reset DSAF channels + //Arg0 : mask + //Arg1 : 0 reset, 1 de-reset + Method(DCRT, 2, Serialized) { + If (LEqual (Arg1, 0)) { + Store(Arg0, DCRE) + } Else { + Store(Arg0, DCRD) + } + } + + //reset RoCE + //Arg0 : 0 reset, 1 de-reset + Method(RRST, 1, Serialized) { + If (LEqual (Arg0, 0)) { + Store(0x1, RKRE) + } Else { + Store(0x1, RCLD) + Store(0x1, RKRD) + sleep(20) + Store(0x1, RCLE) + } + } + // Set Serdes Loopback //Arg0 : port //Arg1 : 0 disable, 1 enable @@ -307,7 +358,7 @@ Scope(_SB) }
//Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) + //Arg0 : reset type (1: dsaf; 2: ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce) //Arg1 : port //Arg2 : 0 disable, 1 enable Method(DRST, 3, Serialized) @@ -363,6 +414,22 @@ Scope(_SB) Store (Arg2, Local1) GRST (Local0, Local1) } + + //Reset DSAF Channels + case (0x6) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + DCRT (Local0, Local1) + } + + //Reset RoCE + case (0x7) + { + // Discarding Arg1 as it is always 0 + Store (Arg2, Local0) + RRST (Local0) + } } }
@@ -373,7 +440,7 @@ Scope(_SB) // Arg2: Integer Function Index // 0 : Return Supported Functions bit mask // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce) // Arg3[1] : port index in dsaf // Arg3[2] : 0 reset, 1 cancle reset // 2 : Set Serdes Loopback @@ -611,5 +678,13 @@ Scope(_SB) 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, } }) + Name (_PRS, ResourceTemplate (){ + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) } }
This patch adds new "node-guid" parameter in ACPI DSDT Table. This is required for RoCE CM(Conenction Mode) feature.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta salil.mehta@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 1 + 1 file changed, 1 insertion(+)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 57d28cf..765ca19 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -633,6 +633,7 @@ Scope(_SB) Package () { Package () {"eth-handle", Package () {_SB.ETH0, _SB.ETH1, 0, 0, _SB.ETH4, _SB.ETH5}}, Package () {"dsaf-handle", Package (){_SB.DSF0}}, + Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes Package () {"interrupt-names", Package() {"hns-roce-comp-0", "hns-roce-comp-1", "hns-roce-comp-2",
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 4 ++-- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 2 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index db98305..09245b8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -10,8 +10,8 @@ [0004] Table Length : 000002e4 [0001] Revision : 00 [0001] Checksum : BC -[0006] Oem ID : "HISI " -[0008] Oem Table ID : "HISI1610" +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HIP06 " [0004] Oem Revision : 00000000 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20151124 diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl index ca8b2dc..4185f80 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -18,7 +18,7 @@
#include "Hi1610Platform.h"
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI1610", EFI_ACPI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP06 ", EFI_ACPI_ARM_OEM_REVISION) { include ("Lpc.asl") include ("D03Mbig.asl") include ("CPU.asl") diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h index e8a1577..5a95b02 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h @@ -23,8 +23,8 @@ // // ACPI table information used to initialize tables. // -#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','1','6','1','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long #define EFI_ACPI_ARM_OEM_REVISION 0x00000000 #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') #define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h | 4 ++-- Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl index f156e1b..c0cc6d2 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl @@ -18,7 +18,7 @@
#include "Pv660Platform.h"
-DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI", "HISI0660", EFI_ACPI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP05 ", EFI_ACPI_ARM_OEM_REVISION) { include ("Mbig.asl") include ("CPU.asl") include ("Com.asl") diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index 9ba3d55..bcd31d6 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -11,7 +11,7 @@ [0001] Revision : 00 [0001] Checksum : BC [0006] Oem ID : "HISI " -[0008] Oem Table ID : "HISI0660" +[0008] Oem Table ID : "HIP05 " [0004] Oem Revision : 00000000 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20151124 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h index 3d69d96..5c5b0f1 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h @@ -23,8 +23,8 @@ // // ACPI table information used to initialize tables. // -#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I' // OEMID 6 bytes long -#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','S','I','0','6','6','0') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','5',' ',' ',' ') // OEM table id 8 bytes long #define EFI_ACPI_ARM_OEM_REVISION 0x00000000 #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') #define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL index 29b3ff4..fa2c2d8 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL @@ -20,7 +20,7 @@ DefinitionBlock ( "SASSSDT.aml", // Output Filename "SSDT", // Signature 0x01, // SSDT Compliance Revision - "HISI", // OEM ID + "HISI ", // OEM ID "SAS0", // Table ID EFI_ACPI_ARM_OEM_REVISION // OEM Revision ) diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL index e82ee4c..f00664c 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL @@ -21,7 +21,7 @@ DefinitionBlock ( "SATASSDT.aml", // Output Filename "SSDT", // Signature 0x01, // DSDT Compliance Revision - "HISI", // OEM ID + "HISI ", // OEM ID "SATA", // Table ID EFI_ACPI_ARM_OEM_REVISION // OEM Revision )
The length field of GTDT table should be the whole length of entire Generic Timer Description Table.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kefeng Wang wangkefeng.wang@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 2 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc index 4032382..922f5c3 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -56,7 +56,7 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc index 3caf144..f677feb 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc @@ -56,7 +56,7 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 55e7ad5..1d89aa6 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -155,7 +155,7 @@ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Estuary v2.2 D02 UEFI" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D02 UEFI 16.08 RC1"
gHisiTokenSpaceGuid.PcdSystemProductName|L"D02" gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 80fdad4..aa085da 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -182,7 +182,7 @@ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Estuary v2.2 D03 UEFI" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.08 RC1"
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
There is no register restore processor id at ARM Platform,we talked with ARM Charles and made a agreement that we can use MIDR instead,maybe there will be a specific register to read the processor id in future.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Charles Garcia-Tobin charles.garcia-tobin@arm.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 07dae5f..005d28f 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -490,6 +490,7 @@ AddSmbiosProcessorTypeTable ( CHAR16 *CpuVersion; STRING_REF TokenToUpdate;
+ UINT64 *ProcessorId; Type4Record = NULL; ProcessorManuStr = NULL; ProcessorVersionStr = NULL; @@ -614,6 +615,8 @@ AddSmbiosProcessorTypeTable ( Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data;
Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000); + ProcessorId = (UINT64 *)&(Type4Record->ProcessorId); + *ProcessorId = ArmReadMidr();
OptionalStrStart = (CHAR8 *) (Type4Record + 1); UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart);
The variable will be initialized in the function code, so it is not nesseary to be filled a data in the definition.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 005d28f..61473e8 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -226,7 +226,7 @@ GetCacheSocketStr ( OUT CHAR16 *CacheSocketStr ) { - UINTN CacheSocketStrLen = 0; + UINTN CacheSocketStrLen;
if(CacheLevel == CPU_CACHE_L1_Instruction) { @@ -258,7 +258,6 @@ UpdateSmbiosCacheTable ( CACHE_SRAM_TYPE_DATA CacheSramType = {0};
CoreCount = 16; // Default value is 16 Core - CacheSize = 0;
// // Set Cache Configuration
Read reference clock from ARCH timer frequency and set it into DT.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 60 ++++++++++++++++++++++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 + 2 files changed, 62 insertions(+)
diff --git a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c index b8b9503..d00cb9b 100755 --- a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c +++ b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c @@ -14,6 +14,7 @@ **/
#include <Uefi.h> +#include <Library/ArmArchTimer.h> #include <Library/BaseLib.h> #include <libfdt.h> #include <Library/IoLib.h> @@ -183,6 +184,61 @@ DelPhyhandleUpdateMacAddress(IN VOID* Fdt) return Status; }
+STATIC +EFI_STATUS +UpdateRefClk (IN VOID* Fdt) +{ + INTN node; + INTN Error; + struct fdt_property *m_prop; + int m_oldlen; + UINTN ArchTimerFreq = 0; + UINT32 Data; + CONST CHAR8 *Property = "clock-frequency"; + + ArmArchTimerReadReg (CntFrq, &ArchTimerFreq); + if (!ArchTimerFreq) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Get timer frequency failed!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + node = fdt_subnode_offset(Fdt, 0, "soc"); + if (node < 0) { + DEBUG ((DEBUG_ERROR, "can not find soc node\n")); + return EFI_INVALID_PARAMETER; + } + + node = fdt_subnode_offset(Fdt, node, "refclk"); + if (node < 0) { + DEBUG ((DEBUG_ERROR, "can not find refclk node\n")); + return EFI_INVALID_PARAMETER; + } + + m_prop = fdt_get_property_w(Fdt, node, Property, &m_oldlen); + if(!m_prop) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Can't find property %a\n", __FUNCTION__, __LINE__, Property)); + return EFI_INVALID_PARAMETER; + } + + Error = fdt_delprop(Fdt, node, Property); + if (Error) { + DEBUG ((DEBUG_ERROR, "ERROR: fdt_delprop() %a: %a\n", Property, fdt_strerror (Error))); + return EFI_INVALID_PARAMETER; + } + + // UINT32 is enough for refclk data length + Data = (UINT32) ArchTimerFreq; + Data = cpu_to_fdt32 (Data); + Error = fdt_setprop(Fdt, node, Property, &Data, sizeof(Data)); + if (Error) { + DEBUG ((DEBUG_ERROR, "ERROR:fdt_setprop() %a: %a\n", Property, fdt_strerror (Error))); + return EFI_INVALID_PARAMETER; + } + + DEBUG ((DEBUG_INFO, "Update refclk successfully.\n")); + return EFI_SUCCESS; +} + INTN GetMemoryNode(VOID* Fdt) { @@ -401,6 +457,10 @@ EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr) Status = EFI_SUCCESS; }
+ Status = UpdateRefClk (Fdt); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UpdateiRefClk fail.\n")); + }
Status = UpdateMemoryNode(Fdt); if (EFI_ERROR (Status)) diff --git a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf index b885eae..9569b91 100755 --- a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf +++ b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -27,12 +27,14 @@
[Packages] + ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec EmbeddedPkg/EmbeddedPkg.dec OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] + ArmLib FdtLib PlatformSysCtrlLib OemMiscLib
Refine SAS ASL code indention to EDK2 style.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 276 ++++++++++----------- 1 file changed, 138 insertions(+), 138 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index de21b2d..e19ea18 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -16,56 +16,56 @@
Scope(_SB) { - Device(SAS0) { - Name(_HID, "HISI0162") + Device(SAS0) { + Name(_HID, "HISI0162") Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI6") - { - 64,65,66,67,68, - 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI6") + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI6" ) - { - 601,602,603,604, - 605,606,607,608,609, - 610,611,612,613,614, - 615,616,617,618,619, - 620,621,622,623,624, - 625,626,627,628,629, - 630,631,632, + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI6}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI6}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) + })
OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -89,60 +89,60 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } - } + }
- Device(SAS1) { - Name(_HID, "HISI0162") - Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) + Device(SAS1) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI1") { - 64,65,66,67,68, - 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") - { - 576,577,578,579,580, - 581,582,583,584,585, - 586,587,588,589,590, - 591,592,593,594,595, - 596,597,598,599,600, - 601,602,603,604,605, - 606,607, + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI1}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - Package () {"hip06-sas-v2-quirk-amt", 1}, - } - }) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI1}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + Package () {"hip06-sas-v2-quirk-amt", 1}, + } + })
OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -166,59 +166,59 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } - } + }
- Device(SAS2) { - Name(_HID, "HISI0162") + Device(SAS2) { + Name(_HID, "HISI0162") Name(_CCA, 1) - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI2") - { - 192,193,194,195,196, - 197,198,199,200,201, - 202,203,204,205,206, - 207,208,209,210,211, - 212,213,214,215,216, - 217,218,219,220,221, - 222,223,224,225,226, - 227,228,229,230,231, - 232,233,234,235,236, - 237,238,239,240,241, - 242,243,244,245,246, - 247,248,249,250,251, - 252,253,254,255,256, - 257,258,259,260,261, - 262,263,264,265,266, - 267,268,269,270,271, - 272,273,274,275,276, - 277,278,279,280,281, - 282,283,284,285,286, - 287, + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, }
- Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI2") - { - 608,609,610,611, - 612,613,614,615,616, - 617,618,619,620,621, - 622,623,624,625,626, - 627,628,629,630,631, - 632,633,634,635,636, - 637,638,639, + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI2") + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI2}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, } - }) - - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"interrupt-parent",Package() {_SB.MBI2}}, - Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, - Package () {"queue-count", 16}, - Package () {"phy-count", 8}, - } - }) + })
OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) Field (CTL, AnyAcc, NoLock, Preserve) @@ -242,6 +242,6 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } - } + }
}
1. Check the value of register(0xD000E014) to decide whether this is 50MHZ or 66MHZ board attached. Configure register PHY_CTRL to support 50MHZ or 66MHZ. Default Configure of PHY_CTRL is the configure of 50MHZ, if 66MHZ board attached, change the value of PHY_CTRL.
2. D03 have 66M and 50M two types boards, they refer the different reference clock, set the PCD to 0 so that the code will read frequency from register and be adapted to 66M and 50M boards, so also update FVMAIN_SEC binary to adapt different configuration about 50MHZ and 66MHZ boards.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiang Chen chenxiang66@Hisilicon.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 122 ++++++++++++++++++++- Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/D03/D03.dsc | 4 +- 3 files changed, 124 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index e19ea18..9944a50 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -80,6 +80,32 @@ Scope(_SB) STS, 32, }
+ OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -88,6 +114,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + } } }
@@ -157,6 +196,32 @@ Scope(_SB) STS, 32, }
+ OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -165,6 +230,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + } } }
@@ -216,7 +294,7 @@ Scope(_SB) Package () {"interrupt-parent",Package() {_SB.MBI2}}, Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, Package () {"queue-count", 16}, - Package () {"phy-count", 8}, + Package () {"phy-count", 9}, } })
@@ -233,6 +311,34 @@ Scope(_SB) STS, 32, }
+ OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + offset (0x2014), + PHY8, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -241,6 +347,20 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + Store(Local1, PHY8) + } } }
diff --git a/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv index 1050b92..1830a6a 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv and b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv differ diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index aa085da..850b16b 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -218,7 +218,9 @@ # # ARM Architectual Timer Frequency # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|66000000 + # Set it to 0 so that the code will read frequence from register and be + # adapted to 66M and 50M boards + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
The defination of OHCI and EHCI hardware pins are wrong, the OHCI pin number is 640, and the EHCI hardware pin number is 641, correct them.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kefeng Wang wangkefeng@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 2 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index afd6b47..7265ac8 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -23,7 +23,7 @@ Scope(_SB) })
Name(_PRS, ResourceTemplate() { - Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {0x41, 0x42} + Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {640, 641} //OHCI: 640, EHCI 641 })
Name(_DSD, Package () { diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl index 8429a4b..9132965 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl @@ -34,7 +34,7 @@ Scope(_SB) ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI0") { - 0x00000041, + 641, //EHCI } }) Return (RBUF) /* _SB_.USB0._CRS.RBUF */
The flag should be set to 1 when the single mapping property is 1, correct them.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: MaJun majun258@huawei.com Reviewed-by: Graeme Gregory graeme.gregory@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index 09245b8..9a045b7 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -60,7 +60,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040080 // device id [0004] Output Reference : 00000034 // point to its dsa -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi1 - sas1, named component */ @@ -91,7 +91,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040000 [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi2 - sas2, named component */ @@ -122,7 +122,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040040 [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi3 - dsa0, srv named component */ @@ -153,7 +153,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040800 [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */ @@ -184,7 +184,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040b1c [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi5 - dsa2, dbg1 named component */ @@ -215,7 +215,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040b1d [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen dsa mbi6 - dsa sas0 named component */ @@ -246,7 +246,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040900 [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* mbi-gen mbi7 - RoCE named component */ @@ -277,7 +277,7 @@ [0004] ID Count : 00000001 [0004] Output Base : 00040b1e [0004] Output Reference : 00000034 -[0004] Flags (decoded below) : 00000000 +[0004] Flags (decoded below) : 00000001 Single Mapping : 1
/* RC 0 */
The NullMemoryTestDxe and GenericMemoryTestDxe both have one function, which is switching the untested memory of type EfiGcdMemoryTypeReserved to EfiGcdMemoryTypeSystemMemory.
The above 4GB memory is not reported as system memory in UEFI memory map before BDS on hisilicon platforms. After running memory test protocol, whether it is from NullMemoryTestDxe or GenericMemoryTestDxe, memory space above 4GB will be switched to EfiGcdMemoryTypeSystemMemory and reported in UEFI memory map.
There are 8 DIMM slots at D03 platform, it takes about 2 minutes to do memory test when inserting full memory(16G*8), so we switch to NullMemoryTest to promote boot time.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 850b16b..40aec5c 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -506,7 +506,7 @@ # # Memory test # - MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index d101abb..3302ec9 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -290,7 +290,7 @@ READ_LOCK_STATUS = TRUE # INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
On Tue, Dec 06, 2016 at 06:57:01PM +0800, Heyi Guo wrote:
The NullMemoryTestDxe and GenericMemoryTestDxe both have one function, which is switching the untested memory of type EfiGcdMemoryTypeReserved to EfiGcdMemoryTypeSystemMemory.
The above 4GB memory is not reported as system memory in UEFI memory map before BDS on hisilicon platforms. After running memory test protocol, whether it is from NullMemoryTestDxe or GenericMemoryTestDxe, memory space above 4GB will be switched to EfiGcdMemoryTypeSystemMemory and reported in UEFI memory map.
There are 8 DIMM slots at D03 platform, it takes about 2 minutes to do memory test when inserting full memory(16G*8), so we switch to NullMemoryTest to promote boot time.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 850b16b..40aec5c 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -506,7 +506,7 @@ # # Memory test #
- MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index d101abb..3302ec9 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -290,7 +290,7 @@ READ_LOCK_STATUS = TRUE # INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
-- 1.9.1
The images not from FV are treated as 3rd party images, and will be dispatched after EndOfDxe event due to EDK2 commit 8be37a5cee, so we signal a EndOfDxe event or the bootloader application will not be executed.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org --- Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c | 2 ++ Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf | 1 + 2 files changed, 3 insertions(+)
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c index 43a4385..efefeb6 100644 --- a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c +++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c @@ -157,6 +157,8 @@ PlatformBdsInit ( VOID ) { + //Signal EndofDxe Event + EfiEventGroupSignal(&gEfiEndOfDxeEventGroupGuid); }
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf index 236e314..baceb57 100644 --- a/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf +++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf @@ -67,6 +67,7 @@ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
[Guids] + gEfiEndOfDxeEventGroupGuid gEfiFileInfoGuid gEfiFileSystemInfoGuid gEfiFileSystemVolumeLabelInfoIdGuid
On Tue, Dec 06, 2016 at 06:57:02PM +0800, Heyi Guo wrote:
The images not from FV are treated as 3rd party images, and will be dispatched after EndOfDxe event due to EDK2 commit 8be37a5cee, so we signal a EndOfDxe event or the bootloader application will not be executed.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c | 2 ++ Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf | 1 + 2 files changed, 3 insertions(+)
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c index 43a4385..efefeb6 100644 --- a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c +++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c @@ -157,6 +157,8 @@ PlatformBdsInit ( VOID ) {
- //Signal EndofDxe Event
- EfiEventGroupSignal(&gEfiEndOfDxeEventGroupGuid);
} diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf index 236e314..baceb57 100644 --- a/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf +++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf @@ -67,6 +67,7 @@ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut [Guids]
- gEfiEndOfDxeEventGroupGuid gEfiFileInfoGuid gEfiFileSystemInfoGuid gEfiFileSystemVolumeLabelInfoIdGuid
-- 1.9.1
The BaseMemoryLib has switch to use BaseMemoryLibOptDxe at OPP, but the flash module is device attributes and have to be alignment accessed. so we change the flash related drivers to use generic BaseMemoryLib which is alignment access.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D05/D05.dsc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index edaad18..3242b29 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -494,6 +494,7 @@ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf @@ -608,7 +609,10 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
!ifdef $(FDT_ENABLE) - OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf { + <LibraryClasses> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } !endif #$(FDT_ENABLE)
#PCIe Support
On 6 December 2016 at 10:57, Heyi Guo heyi.guo@linaro.org wrote:
The BaseMemoryLib has switch to use BaseMemoryLibOptDxe at OPP, but the flash module is device attributes and have to be alignment accessed. so we change the flash related drivers to use generic BaseMemoryLib which is alignment access.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
In the longer term, I would like to fix these drivers so they don't use generic CopyMem() functionality on flash regions, but for now, this is the best workaround
For this patch and the two following ones
Reviewed-by: Ard Biesheuvel ard.biesheuvel@linaro.org
Platforms/Hisilicon/D05/D05.dsc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index edaad18..3242b29 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -494,6 +494,7 @@ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf@@ -608,7 +609,10 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
!ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf {
<LibraryClasses>
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf- }
!endif #$(FDT_ENABLE)
#PCIe Support
1.9.1
On Tue, Dec 06, 2016 at 06:57:03PM +0800, Heyi Guo wrote:
The BaseMemoryLib has switch to use BaseMemoryLibOptDxe at OPP, but the flash module is device attributes and have to be alignment accessed. so we change the flash related drivers to use generic BaseMemoryLib which is alignment access.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
With Ard's R-b: Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Platforms/Hisilicon/D05/D05.dsc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index edaad18..3242b29 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -494,6 +494,7 @@ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf@@ -608,7 +609,10 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf !ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf {
<LibraryClasses>
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf- }
!endif #$(FDT_ENABLE)
#PCIe Support
1.9.1
The BaseMemoryLib has switch to use BaseMemoryLibOptDxe at OPP, but the flash module is device attributes and have to be alignment accessed. so we change the flash related drivers to use generic BaseMemoryLib which is alignment access.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D03/D03.dsc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 40aec5c..b6ce299 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -380,6 +380,7 @@ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf @@ -478,7 +479,10 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
!ifdef $(FDT_ENABLE) - OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf { + <LibraryClasses> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } !endif #$(FDT_ENABLE)
#PCIe Support
On Tue, Dec 06, 2016 at 06:57:04PM +0800, Heyi Guo wrote:
The BaseMemoryLib has switch to use BaseMemoryLibOptDxe at OPP, but the flash module is device attributes and have to be alignment accessed. so we change the flash related drivers to use generic BaseMemoryLib which is alignment access.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Platforms/Hisilicon/D03/D03.dsc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 40aec5c..b6ce299 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -380,6 +380,7 @@ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf@@ -478,7 +479,10 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf !ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf {
<LibraryClasses>
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf- }
!endif #$(FDT_ENABLE)
#PCIe Support
1.9.1
The BaseMemoryLib has switch to use BaseMemoryLibOptDxe at OPP, but the flash module is device attributes and have to be alignment accessed. so we change the flash related drivers to use generic BaseMemoryLib which is alignment access.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D02/Pv660D02.dsc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 1d89aa6..2f5fbe5 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -324,6 +324,7 @@ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf @@ -422,7 +423,10 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
!ifdef $(FDT_ENABLE) - OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf { + <LibraryClasses> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } !endif #$(FDT_ENABLE)
#
On Tue, Dec 06, 2016 at 06:57:05PM +0800, Heyi Guo wrote:
The BaseMemoryLib has switch to use BaseMemoryLibOptDxe at OPP, but the flash module is device attributes and have to be alignment accessed. so we change the flash related drivers to use generic BaseMemoryLib which is alignment access.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Platforms/Hisilicon/D02/Pv660D02.dsc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 1d89aa6..2f5fbe5 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -324,6 +324,7 @@ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { <LibraryClasses> NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf@@ -422,7 +423,10 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf !ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf {
<LibraryClasses>
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf- }
!endif #$(FDT_ENABLE)
#
1.9.1
We would acquire I2C lock only when I2C status in CPLD shows idle, however, acquiring lock will still fail for BMC might acquire the lock at exactly the same time. So we add additional check to see if we really get the lock. Timeout process is also added to avoid system hang due to possible deadlock or device error. Code style is improved as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D03/Include/Library/CpldD03.h | 4 ++ .../DS3231RealTimeClockLib.c | 83 +++++++++++++++++----- .../DS3231RealTimeClockLib.inf | 2 + 3 files changed, 70 insertions(+), 19 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h index 78aec2f..456bf4b 100644 --- a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h +++ b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h @@ -17,5 +17,9 @@ #define __CPLD_D03_H__
#define CPLD_BIOSINDICATE_FLAG 0x09 +#define CPLD_I2C_SWITCH_FLAG 0x17 +#define CPU_GET_I2C_CONTROL BIT2 +#define BMC_I2C_STATUS BIT3 +
#endif diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c index fa63027..3d4a624 100644 --- a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c +++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c @@ -38,6 +38,7 @@ #include <Protocol/RealTimeClock.h> #include <Library/I2CLib.h> #include "DS3231RealTimeClock.h" +#include <Library/CpldD03.h> #include <Library/CpldIoLib.h>
extern I2C_DEVICE gDS3231RtcDevice; @@ -56,6 +57,48 @@ IdentifyDS3231 ( }
EFI_STATUS +SwitchRtcI2cChannelAndLock(VOID) +{ + UINT8 Temp; + UINT8 Count; + + for (Count = 0; Count < 20; Count++){ + Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG); + + if ((Temp & BMC_I2C_STATUS) != 0){ + //The I2C channel is shared with BMC, + //and we need some time to get the idle status, + //we only switch I2C channel to RTC when it is not busy + MicroSecondDelay(30000); + + continue; + } + + Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG); + Temp = Temp | CPU_GET_I2C_CONTROL; + WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp); + //This is empirical value,give cpld some time to make sure the + //value is wrote in + MicroSecondDelay(2); + Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG); + + if ((Temp & CPU_GET_I2C_CONTROL) == CPU_GET_I2C_CONTROL){ + return EFI_SUCCESS; + } + //There need 30ms to keep consistent with the previous loops if the CPU failed + //to get control of I2C + MicroSecondDelay(30000); + } + + Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG); + Temp = Temp & ~CPU_GET_I2C_CONTROL; + WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp); + + return EFI_NOT_READY; +} + + +EFI_STATUS InitializeDS3231 ( VOID ) @@ -136,19 +179,17 @@ LibGetTime ( return EFI_INVALID_PARAMETER; }
- - - Temp = ReadCpldReg(0x17); - while( (Temp & BIT3) != 0) - { - Temp = ReadCpldReg(0x17); + Status = SwitchRtcI2cChannelAndLock(); + if(EFI_ERROR (Status)) { + return Status; } - WriteCpldReg(0x17,0x4); + // Initialize the hardware if not already done if (!mDS3231Initialized) { Status = InitializeDS3231 (); if (EFI_ERROR (Status)) { - return EFI_NOT_READY; + Status = EFI_NOT_READY; + goto GExit; } }
@@ -175,7 +216,8 @@ LibGetTime (
BaseHour = 0; if((Temp&0x30) == 0x30){ - return EFI_DEVICE_ERROR; + Status = EFI_DEVICE_ERROR; + goto GExit; }else if(Temp&0x20){ BaseHour = 20; }else if(Temp&0x10){ @@ -196,11 +238,15 @@ LibGetTime ( Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) { - return EFI_DEVICE_ERROR; + Status = EFI_UNSUPPORTED; }
- WriteCpldReg(0x17,0x0); - return EFI_SUCCESS; +GExit: + Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG); + Temp = Temp & ~CPU_GET_I2C_CONTROL; + WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp); + + return Status;
}
@@ -234,13 +280,10 @@ LibSetTime ( return EFI_INVALID_PARAMETER; }
- - Temp = ReadCpldReg(0x17); - while( (Temp & BIT3) != 0) - { - Temp = ReadCpldReg(0x17); + Status = SwitchRtcI2cChannelAndLock(); + if(EFI_ERROR (Status)) { + return Status; } - WriteCpldReg(0x17,0x4);
// Initialize the hardware if not already done if (!mDS3231Initialized) { @@ -313,7 +356,9 @@ LibSetTime (
EXIT:
- WriteCpldReg(0x17,0x0); + Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG); + Temp = Temp & ~CPU_GET_I2C_CONTROL; + WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
return Status; } diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf index 8121f37..ae1b9b8 100644 --- a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf +++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf @@ -30,6 +30,7 @@ MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec OpenPlatformPkg/OpenPlatformPkg.dec + OpenPlatformPkg/Platforms/Hisilicon/D03/D03.dec OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] @@ -41,6 +42,7 @@ TimerLib # Use EFiAtRuntime to check stage UefiRuntimeLib + CpldIoLib EfiTimeBaseLib
[Pcd]
On Tue, Dec 06, 2016 at 06:57:06PM +0800, Heyi Guo wrote:
We would acquire I2C lock only when I2C status in CPLD shows idle, however, acquiring lock will still fail for BMC might acquire the lock at exactly the same time. So we add additional check to see if we really get the lock. Timeout process is also added to avoid system hang due to possible deadlock or device error. Code style is improved as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
Platforms/Hisilicon/D03/Include/Library/CpldD03.h | 4 ++ .../DS3231RealTimeClockLib.c | 83 +++++++++++++++++----- .../DS3231RealTimeClockLib.inf | 2 + 3 files changed, 70 insertions(+), 19 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h index 78aec2f..456bf4b 100644 --- a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h +++ b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h @@ -17,5 +17,9 @@ #define __CPLD_D03_H__ #define CPLD_BIOSINDICATE_FLAG 0x09 +#define CPLD_I2C_SWITCH_FLAG 0x17 +#define CPU_GET_I2C_CONTROL BIT2 +#define BMC_I2C_STATUS BIT3
#endif diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c index fa63027..3d4a624 100644 --- a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c +++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c @@ -38,6 +38,7 @@ #include <Protocol/RealTimeClock.h> #include <Library/I2CLib.h> #include "DS3231RealTimeClock.h" +#include <Library/CpldD03.h> #include <Library/CpldIoLib.h> extern I2C_DEVICE gDS3231RtcDevice; @@ -56,6 +57,48 @@ IdentifyDS3231 ( } EFI_STATUS +SwitchRtcI2cChannelAndLock(VOID)
Coding style:
SwitchRtcI2cChannelAndLock ( VOID )
+{
- UINT8 Temp;
- UINT8 Count;
- for (Count = 0; Count < 20; Count++){
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
- if ((Temp & BMC_I2C_STATUS) != 0){
if ((Temp & BMC_I2C_STATUS) != 0) {
//The I2C channel is shared with BMC,//and we need some time to get the idle status,//we only switch I2C channel to RTC when it is not busy
So, what I am seeing here is an arbitration scheme designed such that: - Check if BMC has taken ownership of I2C. - If so, wait 30us. - Try again. - If not, start using I2C.
What prevents the BMC from starting a transaction after this CPU has started this transaction?
MicroSecondDelay(30000);
MicroSecondDelay (30000);
continue;- }
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
Another missing space. Please review and adjust consistently.
- Temp = Temp | CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
Add a blank line please.
- //This is empirical value,give cpld some time to make sure the
- //value is wrote in
- MicroSecondDelay(2);
This probably needs a barrier. Please check whether the delay is still needed after adding a barrier.
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- if ((Temp & CPU_GET_I2C_CONTROL) == CPU_GET_I2C_CONTROL){
return EFI_SUCCESS;- }
Blank line please.
The rest of the file has further minor style issues, but nothing further.
By the way - I appreciate the code improvements done as part of this modification.
Regards,
Leif
- //There need 30ms to keep consistent with the previous loops if the CPU failed
- //to get control of I2C
- MicroSecondDelay(30000);
- }
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
- return EFI_NOT_READY;
+}
+EFI_STATUS InitializeDS3231 ( VOID ) @@ -136,19 +179,17 @@ LibGetTime ( return EFI_INVALID_PARAMETER; }
- Temp = ReadCpldReg(0x17);
- while( (Temp & BIT3) != 0)
- {
Temp = ReadCpldReg(0x17);
- Status = SwitchRtcI2cChannelAndLock();
- if(EFI_ERROR (Status)) {
- return Status; }
- WriteCpldReg(0x17,0x4);
- // Initialize the hardware if not already done if (!mDS3231Initialized) { Status = InitializeDS3231 (); if (EFI_ERROR (Status)) {
return EFI_NOT_READY;
Status = EFI_NOT_READY;goto GExit;@@ -175,7 +216,8 @@ LibGetTime ( BaseHour = 0; if((Temp&0x30) == 0x30){
- return EFI_DEVICE_ERROR;
- Status = EFI_DEVICE_ERROR;
- goto GExit; }else if(Temp&0x20){ BaseHour = 20; }else if(Temp&0x10){
@@ -196,11 +238,15 @@ LibGetTime ( Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE; if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) {
- return EFI_DEVICE_ERROR;
- Status = EFI_UNSUPPORTED; }
- WriteCpldReg(0x17,0x0);
- return EFI_SUCCESS;
+GExit:
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
- return Status;
} @@ -234,13 +280,10 @@ LibSetTime ( return EFI_INVALID_PARAMETER; }
- Temp = ReadCpldReg(0x17);
- while( (Temp & BIT3) != 0)
- {
Temp = ReadCpldReg(0x17);
- Status = SwitchRtcI2cChannelAndLock();
- if(EFI_ERROR (Status)) {
- return Status; }
- WriteCpldReg(0x17,0x4);
// Initialize the hardware if not already done if (!mDS3231Initialized) { @@ -313,7 +356,9 @@ LibSetTime ( EXIT:
- WriteCpldReg(0x17,0x0);
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
return Status; } diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf index 8121f37..ae1b9b8 100644 --- a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf +++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf @@ -30,6 +30,7 @@ MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec OpenPlatformPkg/OpenPlatformPkg.dec
- OpenPlatformPkg/Platforms/Hisilicon/D03/D03.dec OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] @@ -41,6 +42,7 @@ TimerLib # Use EFiAtRuntime to check stage UefiRuntimeLib
- CpldIoLib EfiTimeBaseLib
[Pcd] -- 1.9.1
Hi Leif,
在 12/6/2016 8:42 PM, Leif Lindholm 写道:
On Tue, Dec 06, 2016 at 06:57:06PM +0800, Heyi Guo wrote:
We would acquire I2C lock only when I2C status in CPLD shows idle, however, acquiring lock will still fail for BMC might acquire the lock at exactly the same time. So we add additional check to see if we really get the lock. Timeout process is also added to avoid system hang due to possible deadlock or device error. Code style is improved as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
Platforms/Hisilicon/D03/Include/Library/CpldD03.h | 4 ++ .../DS3231RealTimeClockLib.c | 83 +++++++++++++++++----- .../DS3231RealTimeClockLib.inf | 2 + 3 files changed, 70 insertions(+), 19 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h index 78aec2f..456bf4b 100644 --- a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h +++ b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h @@ -17,5 +17,9 @@ #define __CPLD_D03_H__ #define CPLD_BIOSINDICATE_FLAG 0x09 +#define CPLD_I2C_SWITCH_FLAG 0x17 +#define CPU_GET_I2C_CONTROL BIT2 +#define BMC_I2C_STATUS BIT3
#endif diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c index fa63027..3d4a624 100644 --- a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c +++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c @@ -38,6 +38,7 @@ #include <Protocol/RealTimeClock.h> #include <Library/I2CLib.h> #include "DS3231RealTimeClock.h" +#include <Library/CpldD03.h> #include <Library/CpldIoLib.h> extern I2C_DEVICE gDS3231RtcDevice; @@ -56,6 +57,48 @@ IdentifyDS3231 ( } EFI_STATUS +SwitchRtcI2cChannelAndLock(VOID)
Coding style:
SwitchRtcI2cChannelAndLock ( VOID )
+{
- UINT8 Temp;
- UINT8 Count;
- for (Count = 0; Count < 20; Count++){
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
- if ((Temp & BMC_I2C_STATUS) != 0){
if ((Temp & BMC_I2C_STATUS) != 0) {
//The I2C channel is shared with BMC,//and we need some time to get the idle status,//we only switch I2C channel to RTC when it is not busySo, what I am seeing here is an arbitration scheme designed such that:
- Check if BMC has taken ownership of I2C.
- If so, wait 30us.
- Try again.
- If not, start using I2C.
What prevents the BMC from starting a transaction after this CPU has started this transaction?
MicroSecondDelay(30000);MicroSecondDelay (30000);
continue;- }
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
Another missing space. Please review and adjust consistently.
- Temp = Temp | CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
Add a blank line please.
- //This is empirical value,give cpld some time to make sure the
- //value is wrote in
- MicroSecondDelay(2);
This probably needs a barrier. Please check whether the delay is still needed after adding a barrier.
It is not a barrier problem, the CPU can operate the command one by one, but the cpld is a independent hardware, it has its own firmware and need some time to process data.
Thanks, Heyi
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- if ((Temp & CPU_GET_I2C_CONTROL) == CPU_GET_I2C_CONTROL){
return EFI_SUCCESS;- }
Blank line please.
The rest of the file has further minor style issues, but nothing further.
By the way - I appreciate the code improvements done as part of this modification.
Regards,
Leif
- //There need 30ms to keep consistent with the previous loops if the CPU failed
- //to get control of I2C
- MicroSecondDelay(30000);
- }
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
- return EFI_NOT_READY;
+}
+EFI_STATUS InitializeDS3231 ( VOID ) @@ -136,19 +179,17 @@ LibGetTime ( return EFI_INVALID_PARAMETER; }
- Temp = ReadCpldReg(0x17);
- while( (Temp & BIT3) != 0)
- {
Temp = ReadCpldReg(0x17);
- Status = SwitchRtcI2cChannelAndLock();
- if(EFI_ERROR (Status)) {
- return Status; }
- WriteCpldReg(0x17,0x4);
- // Initialize the hardware if not already done if (!mDS3231Initialized) { Status = InitializeDS3231 (); if (EFI_ERROR (Status)) {
return EFI_NOT_READY;
Status = EFI_NOT_READY;goto GExit; }@@ -175,7 +216,8 @@ LibGetTime ( BaseHour = 0; if((Temp&0x30) == 0x30){
- return EFI_DEVICE_ERROR;
- Status = EFI_DEVICE_ERROR;
- goto GExit; }else if(Temp&0x20){ BaseHour = 20; }else if(Temp&0x10){
@@ -196,11 +238,15 @@ LibGetTime ( Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE; if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) {
- return EFI_DEVICE_ERROR;
- Status = EFI_UNSUPPORTED; }
- WriteCpldReg(0x17,0x0);
- return EFI_SUCCESS;
+GExit:
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
- return Status;
} @@ -234,13 +280,10 @@ LibSetTime ( return EFI_INVALID_PARAMETER; }
- Temp = ReadCpldReg(0x17);
- while( (Temp & BIT3) != 0)
- {
Temp = ReadCpldReg(0x17);
- Status = SwitchRtcI2cChannelAndLock();
- if(EFI_ERROR (Status)) {
- return Status; }
- WriteCpldReg(0x17,0x4);
// Initialize the hardware if not already done if (!mDS3231Initialized) { @@ -313,7 +356,9 @@ LibSetTime ( EXIT:
- WriteCpldReg(0x17,0x0);
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
return Status; } diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf index 8121f37..ae1b9b8 100644 --- a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf +++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf @@ -30,6 +30,7 @@ MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec OpenPlatformPkg/OpenPlatformPkg.dec
- OpenPlatformPkg/Platforms/Hisilicon/D03/D03.dec OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] @@ -41,6 +42,7 @@ TimerLib # Use EFiAtRuntime to check stage UefiRuntimeLib
- CpldIoLib EfiTimeBaseLib
[Pcd] -- 1.9.1
On Wed, Dec 07, 2016 at 04:51:52PM +0800, Heyi Guo wrote:
Hi Leif,
在 12/6/2016 8:42 PM, Leif Lindholm 写道:
On Tue, Dec 06, 2016 at 06:57:06PM +0800, Heyi Guo wrote:
We would acquire I2C lock only when I2C status in CPLD shows idle, however, acquiring lock will still fail for BMC might acquire the lock at exactly the same time. So we add additional check to see if we really get the lock. Timeout process is also added to avoid system hang due to possible deadlock or device error. Code style is improved as well.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
Platforms/Hisilicon/D03/Include/Library/CpldD03.h | 4 ++ .../DS3231RealTimeClockLib.c | 83 +++++++++++++++++----- .../DS3231RealTimeClockLib.inf | 2 + 3 files changed, 70 insertions(+), 19 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h index 78aec2f..456bf4b 100644 --- a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h +++ b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h @@ -17,5 +17,9 @@ #define __CPLD_D03_H__ #define CPLD_BIOSINDICATE_FLAG 0x09 +#define CPLD_I2C_SWITCH_FLAG 0x17 +#define CPU_GET_I2C_CONTROL BIT2 +#define BMC_I2C_STATUS BIT3
#endif diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c index fa63027..3d4a624 100644 --- a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c +++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c @@ -38,6 +38,7 @@ #include <Protocol/RealTimeClock.h> #include <Library/I2CLib.h> #include "DS3231RealTimeClock.h" +#include <Library/CpldD03.h> #include <Library/CpldIoLib.h> extern I2C_DEVICE gDS3231RtcDevice; @@ -56,6 +57,48 @@ IdentifyDS3231 ( } EFI_STATUS +SwitchRtcI2cChannelAndLock(VOID)
Coding style:
SwitchRtcI2cChannelAndLock ( VOID )
+{
- UINT8 Temp;
- UINT8 Count;
- for (Count = 0; Count < 20; Count++){
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
- if ((Temp & BMC_I2C_STATUS) != 0){
if ((Temp & BMC_I2C_STATUS) != 0) {
//The I2C channel is shared with BMC,//and we need some time to get the idle status,//we only switch I2C channel to RTC when it is not busySo, what I am seeing here is an arbitration scheme designed such that:
- Check if BMC has taken ownership of I2C.
- If so, wait 30us.
- Try again.
- If not, start using I2C.
What prevents the BMC from starting a transaction after this CPU has started this transaction?
MicroSecondDelay(30000);MicroSecondDelay (30000);
continue;- }
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
Another missing space. Please review and adjust consistently.
- Temp = Temp | CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
Add a blank line please.
- //This is empirical value,give cpld some time to make sure the
- //value is wrote in
- MicroSecondDelay(2);
This probably needs a barrier. Please check whether the delay is still needed after adding a barrier.
It is not a barrier problem, the CPU can operate the command one by one, but the cpld is a independent hardware, it has its own firmware and need some time to process data.
OK.
/ Leif
Thanks, Heyi
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- if ((Temp & CPU_GET_I2C_CONTROL) == CPU_GET_I2C_CONTROL){
return EFI_SUCCESS;- }
Blank line please.
The rest of the file has further minor style issues, but nothing further.
By the way - I appreciate the code improvements done as part of this modification.
Regards,
Leif
- //There need 30ms to keep consistent with the previous loops if the CPU failed
- //to get control of I2C
- MicroSecondDelay(30000);
- }
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
- return EFI_NOT_READY;
+}
+EFI_STATUS InitializeDS3231 ( VOID ) @@ -136,19 +179,17 @@ LibGetTime ( return EFI_INVALID_PARAMETER; }
- Temp = ReadCpldReg(0x17);
- while( (Temp & BIT3) != 0)
- {
Temp = ReadCpldReg(0x17);
- Status = SwitchRtcI2cChannelAndLock();
- if(EFI_ERROR (Status)) {
- return Status; }
- WriteCpldReg(0x17,0x4);
- // Initialize the hardware if not already done if (!mDS3231Initialized) { Status = InitializeDS3231 (); if (EFI_ERROR (Status)) {
return EFI_NOT_READY;
Status = EFI_NOT_READY;goto GExit;@@ -175,7 +216,8 @@ LibGetTime ( BaseHour = 0; if((Temp&0x30) == 0x30){
- return EFI_DEVICE_ERROR;
- Status = EFI_DEVICE_ERROR;
- goto GExit; }else if(Temp&0x20){ BaseHour = 20; }else if(Temp&0x10){
@@ -196,11 +238,15 @@ LibGetTime ( Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE; if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) {
- return EFI_DEVICE_ERROR;
- Status = EFI_UNSUPPORTED; }
- WriteCpldReg(0x17,0x0);
- return EFI_SUCCESS;
+GExit:
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp);
- return Status;
} @@ -234,13 +280,10 @@ LibSetTime ( return EFI_INVALID_PARAMETER; }
- Temp = ReadCpldReg(0x17);
- while( (Temp & BIT3) != 0)
- {
Temp = ReadCpldReg(0x17);
- Status = SwitchRtcI2cChannelAndLock();
- if(EFI_ERROR (Status)) {
- return Status; }
- WriteCpldReg(0x17,0x4); // Initialize the hardware if not already done if (!mDS3231Initialized) {
@@ -313,7 +356,9 @@ LibSetTime ( EXIT:
- WriteCpldReg(0x17,0x0);
- Temp = ReadCpldReg(CPLD_I2C_SWITCH_FLAG);
- Temp = Temp & ~CPU_GET_I2C_CONTROL;
- WriteCpldReg(CPLD_I2C_SWITCH_FLAG, Temp); return Status;
} diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf index 8121f37..ae1b9b8 100644 --- a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf +++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf @@ -30,6 +30,7 @@ MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec OpenPlatformPkg/OpenPlatformPkg.dec
- OpenPlatformPkg/Platforms/Hisilicon/D03/D03.dec OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] @@ -41,6 +42,7 @@ TimerLib # Use EFiAtRuntime to check stage UefiRuntimeLib
- CpldIoLib EfiTimeBaseLib
[Pcd]
1.9.1
The pcie device should be disable for chip's reason before EC and the pcie device should be enable after EC for OS. Enable all the pcie device, because it is ok for bios.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 33 ++++++++++++++++++---- Platforms/Hisilicon/D05/D05.dsc | 3 +- 2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 8574648..f9b4722 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -19,6 +19,27 @@ //#include "ArmPlatform.h" Scope(_SB) { + /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */ + OperationRegion (ECRA, SystemMemory, 0xD000E014, 0x4) + Field (ECRA, AnyAcc, NoLock, Preserve) + { + VECA, 32, + } + + /* RBYV:Return by chip version + * the pcie device should be disable for chip's reason before EC, + * and the pcie device should be enable after EC for OS */ + Method (RBYV) + { + Store(VECA, local0) + And (local0, 0xFFF00, local1) + If (LEqual (local1, 0x10200)) { + Return (0xf) + } Else { + Return (0x0) + } + } + // 1P NA PCIe2 Device (PCI2) { @@ -147,7 +168,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) }
} // Device(PCI4) @@ -220,7 +241,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI5)
@@ -292,7 +313,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI6) // 1P NB PCIe3 @@ -363,7 +384,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI7) // 2P NA PCIe2 @@ -505,7 +526,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCIc)
@@ -577,7 +598,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCId) } diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 3242b29..1f5e084 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -167,7 +167,8 @@
gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + ## enable all the pcie device, because it is ok for bios + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
## SP805 Watchdog - Motherboard Watchdog
On Tue, Dec 06, 2016 at 06:57:07PM +0800, Heyi Guo wrote:
The pcie device should be disable for chip's reason before EC and the pcie device should be enable after EC for OS. Enable all the pcie device, because it is ok for bios.
The patch looks fine but can you define the term EC in the commit messages/comments.
If this is changed I can add my Reviewed-by
Thanks
Graeme
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang huangming23@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 33 ++++++++++++++++++---- Platforms/Hisilicon/D05/D05.dsc | 3 +- 2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 8574648..f9b4722 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -19,6 +19,27 @@ //#include "ArmPlatform.h" Scope(_SB) {
- /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */
- OperationRegion (ECRA, SystemMemory, 0xD000E014, 0x4)
- Field (ECRA, AnyAcc, NoLock, Preserve)
- {
- VECA, 32,
- }
- /* RBYV:Return by chip version
- the pcie device should be disable for chip's reason before EC,
- and the pcie device should be enable after EC for OS */
- Method (RBYV)
- {
- Store(VECA, local0)
- And (local0, 0xFFF00, local1)
- If (LEqual (local1, 0x10200)) {
Return (0xf)- } Else {
Return (0x0)- }
- }
- // 1P NA PCIe2 Device (PCI2) {
@@ -147,7 +168,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) {
Return (0x0)
Return (RBYV())} // Device(PCI4) @@ -220,7 +241,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) {
Return (0x0)
Return (RBYV())@@ -292,7 +313,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) {
Return (0x0)
Return (RBYV())@@ -363,7 +384,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) {
Return (0x0)
Return (RBYV())@@ -505,7 +526,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) {
Return (0x0)
Return (RBYV())@@ -577,7 +598,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) {
Return (0x0)
Return (RBYV())} diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 3242b29..1f5e084 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -167,7 +167,8 @@ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
- ## enable all the pcie device, because it is ok for bios
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
## SP805 Watchdog - Motherboard Watchdog
1.9.1
D05 platform numa nodes distance:
-------------- -------------- |Node1--Node0|<------>|Node2--Node3| -------------- -------------- cluster0 cluster1
Each cluster has two nodes, we treat that the node0 and node1 have the same distance to Node2 and node3, on the other hand, the node2 and node3 have the same distance to node0 and node1. The default distance of Slit table is wrong, correct it.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc index ea93504..89cc4a9 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc @@ -51,10 +51,10 @@ EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, }, { - {{0x0A, 0x10, 0x20, 0x21}}, //Locality 0 - {{0x10, 0x0A, 0x19, 0x20}}, //Locality 1 - {{0x20, 0x19, 0x0A, 0x10}}, //Locality 2 - {{0x21, 0x20, 0x10, 0x0A}}, //Locality 3 + {{0x0A, 0x0F, 0x14, 0x14}}, //Locality 0 + {{0x0F, 0x0A, 0x14, 0x14}}, //Locality 1 + {{0x14, 0x14, 0x0A, 0x0F}}, //Locality 2 + {{0x14, 0x14, 0x0F, 0x0A}}, //Locality 3 }, };
This looks fine style wise to me
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
On Tue, Dec 06, 2016 at 06:57:08PM +0800, Heyi Guo wrote:
D05 platform numa nodes distance:
|Node1--Node0|<------>|Node2--Node3|
cluster0 cluster1Each cluster has two nodes, we treat that the node0 and node1 have the same distance to Node2 and node3, on the other hand, the node2 and node3 have the same distance to node0 and node1. The default distance of Slit table is wrong, correct it.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com
Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc index ea93504..89cc4a9 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc @@ -51,10 +51,10 @@ EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, }, {
- {{0x0A, 0x10, 0x20, 0x21}}, //Locality 0
- {{0x10, 0x0A, 0x19, 0x20}}, //Locality 1
- {{0x20, 0x19, 0x0A, 0x10}}, //Locality 2
- {{0x21, 0x20, 0x10, 0x0A}}, //Locality 3
- {{0x0A, 0x0F, 0x14, 0x14}}, //Locality 0
- {{0x0F, 0x0A, 0x14, 0x14}}, //Locality 1
- {{0x14, 0x14, 0x0A, 0x0F}}, //Locality 2
- {{0x14, 0x14, 0x0F, 0x0A}}, //Locality 3 },
}; -- 1.9.1
On 12/06/2016 06:57 PM, Heyi Guo wrote:
D05 platform numa nodes distance:
|Node1--Node0|<------>|Node2--Node3|
cluster0 cluster1Each cluster has two nodes, we treat that the node0 and node1 have the same distance to Node2 and node3, on the other hand, the node2 and node3 have the same distance to node0 and node1. The default distance of Slit table is wrong, correct it.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com
Reviewed-by: Hanjun Guo hanjun.guo@linaro.org
On 12/06/2016 06:57 PM, Heyi Guo wrote:
D05 platform numa nodes distance:
|Node1--Node0|<------>|Node2--Node3|
cluster0 cluster1Each cluster has two nodes, we treat that the node0 and node1 have the same distance to Node2 and node3, on the other hand, the node2 and node3 have the same distance to node0 and node1. The default distance of Slit table is wrong, correct it.
By the way, the SRAT seems wrong, and I can see that you send a patch for that, should that be sent for merge?
Thanks Hanjun
Hi Hanjun,
Only rp-16.12-01-all branch is wrong, we fix it at the new branch.
Thanks and Regards,
Heyi
在 12/7/2016 5:21 PM, Hanjun Guo 写道:
On 12/06/2016 06:57 PM, Heyi Guo wrote:
D05 platform numa nodes distance:
|Node1--Node0|<------>|Node2--Node3|
cluster0 cluster1Each cluster has two nodes, we treat that the node0 and node1 have the same distance to Node2 and node3, on the other hand, the node2 and node3 have the same distance to node0 and node1. The default distance of Slit table is wrong, correct it.
By the way, the SRAT seems wrong, and I can see that you send a patch for that, should that be sent for merge?
Thanks Hanjun
On 12/07/2016 08:23 PM, Heyi Guo wrote:
Hi Hanjun,
Only rp-16.12-01-all branch is wrong, we fix it at the new branch.
Got it, thanks!
Hanjun
Thanks and Regards,
Heyi
在 12/7/2016 5:21 PM, Hanjun Guo 写道:
On 12/06/2016 06:57 PM, Heyi Guo wrote:
D05 platform numa nodes distance:
|Node1--Node0|<------>|Node2--Node3|
cluster0 cluster1Each cluster has two nodes, we treat that the node0 and node1 have the same distance to Node2 and node3, on the other hand, the node2 and node3 have the same distance to node0 and node1. The default distance of Slit table is wrong, correct it.
By the way, the SRAT seems wrong, and I can see that you send a patch for that, should that be sent for merge?
Thanks Hanjun
-
Ard Biesheuvel -
graeme.gregory＠linaro.org -
Hanjun Guo -
Heyi Guo -
Leif Lindholm