+ Manuel,
On 8/30/23 09:01, Guenter Roeck wrote:
On 8/30/23 03:52, Greg Kroah-Hartman wrote:
On Mon, Aug 28, 2023 at 09:42:11AM -0700, Guenter Roeck wrote:
On 8/28/23 03:13, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 5.10.193 release. There are 84 patches in this series, all will be posted as a response to this one. If anyone has any issues with these being applied, please let me know.
Responses should be made by Wed, 30 Aug 2023 10:11:30 +0000. Anything received after that time might be too late.
FWIW, commit 619672bf2d04 ("MIPS: Alchemy: fix dbdma2") should be reverted v5.10.y since it doesn't fix anything but breaks the build for affected boards completely.
arch/mips/alchemy/common/dbdma.c: In function 'au1xxx_dbdma_put_source': arch/mips/alchemy/common/dbdma.c:632:14: error: 'dma_default_coherent' undeclared
There is no 'dma_default_coherent' in v5.10.y.
But that was added in 5.10.185, from back in June. What changed to suddenly cause this to fail now?
Nothing. I started to build this configuration and tracked down the problem after the build failure was reported by others. Sorry, I didn't initially realize that this is an old problem.
We could back port 6d4e9a8efe3d59f31367d79e970c2f328da139a4 ("driver core: lift dma_default_coherent into common code") but that won't work too well on 4.14 or 4.19. I believe it would be simpler to adjust the branches with this patch, Manuel does that work?
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index e9ee9ab90a0c..101cccfaf757 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -29,8 +29,6 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * */ - -#include <linux/dma-map-ops.h> /* for dma_default_coherent */ #include <linux/init.h> #include <linux/kernel.h> #include <linux/slab.h> @@ -38,6 +36,7 @@ #include <linux/interrupt.h> #include <linux/export.h> #include <linux/syscore_ops.h> +#include <asm/dma-coherence.h> #include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1xxx_dbdma.h>
@@ -626,10 +625,10 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) /* * There is an erratum on certain Au1200/Au1550 revisions that could * result in "stale" data being DMA'ed. It has to do with the snoop - * logic on the cache eviction buffer. dma_default_coherent is set - * to false on these parts. + * logic on the cache eviction buffer. coherentio is set + * to IO_COHERENCE_DISABLED on these parts. */ - if (!dma_default_coherent) + if (coherentio == IO_COHERENCE_DISABLED) dma_cache_wback_inv(KSEG0ADDR(buf), nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ wmb(); /* drain writebuffer */ @@ -689,10 +688,10 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) /* * There is an erratum on certain Au1200/Au1550 revisions that could * result in "stale" data being DMA'ed. It has to do with the snoop - * logic on the cache eviction buffer. dma_default_coherent is set - * to false on these parts. + * logic on the cache eviction buffer. coherentio is set + * to IO_COHERENCE_DISABLED on these parts. */ - if (!dma_default_coherent) + if (coherentio == IO_COHERENCE_DISABLED) dma_cache_inv(KSEG0ADDR(buf), nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ wmb(); /* drain writebuffer */