Tcwg-commits January 2018

tcwg-commits@lists.linaro.org

6 participants
3262 discussions

[llvm] branch master updated (1076969bfeb -> 48c8d1e7632)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 1076969bfeb Followup on Proposal to move MIR physical register namespac [...] new 48c8d1e7632 [llvm-cov] Fix incorrect usage of .precision specifier in f [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: tools/llvm-cov/SourceCoverageViewHTML.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[gcc] branch master updated (54540bdd479 -> d3af137c241)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 54540bdd479 PR rtl-optimization/84123 * combine.c (change_zero_ext): [...] new d3af137c241 PR c/81779 * c-parser.c (c_parser_compound_statement_nost [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/c/ChangeLog | 6 ++++++ gcc/c/c-parser.c | 1 + gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/pr81779.c | 15 +++++++++++++++ 4 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/pr81779.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (42b2a1d5ed9 -> 1076969bfeb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 42b2a1d5ed9 [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFC new 1076969bfeb Followup on Proposal to move MIR physical register namespac [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/CodeGen/MIRParser/MILexer.cpp | 23 +- lib/CodeGen/TargetRegisterInfo.cpp | 6 +- .../AArch64/GlobalISel/arm64-callingconv-ios.ll | 6 +- .../AArch64/GlobalISel/arm64-callingconv.ll | 74 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 554 +- .../AArch64/GlobalISel/arm64-regbankselect.mir | 286 +- .../AArch64/GlobalISel/call-translator-ios.ll | 22 +- test/CodeGen/AArch64/GlobalISel/call-translator.ll | 114 +- test/CodeGen/AArch64/GlobalISel/debug-insts.ll | 12 +- test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll | 24 +- .../GlobalISel/fp128-legalize-crash-pr35690.mir | 8 +- .../AArch64/GlobalISel/irtranslator-bitcast.ll | 2 +- .../AArch64/GlobalISel/irtranslator-exceptions.ll | 22 +- test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 110 +- test/CodeGen/AArch64/GlobalISel/legalize-and.mir | 18 +- .../AArch64/GlobalISel/legalize-atomicrmw.mir | 40 +- test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 22 +- .../GlobalISel/legalize-cmpxchg-with-success.mir | 20 +- .../AArch64/GlobalISel/legalize-cmpxchg.mir | 40 +- .../AArch64/GlobalISel/legalize-combines.mir | 34 +- .../AArch64/GlobalISel/legalize-constant.mir | 40 +- test/CodeGen/AArch64/GlobalISel/legalize-div.mir | 18 +- .../AArch64/GlobalISel/legalize-exceptions.ll | 4 +- test/CodeGen/AArch64/GlobalISel/legalize-ext.mir | 78 +- .../AArch64/GlobalISel/legalize-extracts.mir | 46 +- test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir | 18 +- test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir | 20 +- test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir | 128 +- test/CodeGen/AArch64/GlobalISel/legalize-gep.mir | 14 +- .../GlobalISel/legalize-ignore-non-generic.mir | 10 +- .../AArch64/GlobalISel/legalize-inserts.mir | 68 +- test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir | 112 +- .../AArch64/GlobalISel/legalize-load-store.mir | 26 +- .../AArch64/GlobalISel/legalize-merge-values.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-mul.mir | 50 +- .../GlobalISel/legalize-nonpowerof2eltsvec.mir | 10 +- test/CodeGen/AArch64/GlobalISel/legalize-or.mir | 44 +- test/CodeGen/AArch64/GlobalISel/legalize-phi.mir | 122 +- test/CodeGen/AArch64/GlobalISel/legalize-pow.mir | 30 +- test/CodeGen/AArch64/GlobalISel/legalize-rem.mir | 84 +- test/CodeGen/AArch64/GlobalISel/legalize-shift.mir | 22 +- .../CodeGen/AArch64/GlobalISel/legalize-simple.mir | 94 +- test/CodeGen/AArch64/GlobalISel/legalize-sub.mir | 14 +- test/CodeGen/AArch64/GlobalISel/legalize-undef.mir | 2 +- .../AArch64/GlobalISel/legalize-unmerge-values.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 4 +- test/CodeGen/AArch64/GlobalISel/legalize-xor.mir | 14 +- .../GlobalISel/localizer-in-O0-pipeline.mir | 10 +- test/CodeGen/AArch64/GlobalISel/localizer.mir | 8 +- .../GlobalISel/machine-cse-mid-pipeline.mir | 72 +- test/CodeGen/AArch64/GlobalISel/no-regclass.mir | 12 +- .../CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir | 10 +- .../AArch64/GlobalISel/regbankselect-dbg-value.mir | 12 +- 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76 +- .../MIR/PowerPC/unordered-implicit-registers.mir | 12 +- test/CodeGen/MIR/X86/auto-successor.mir | 24 +- test/CodeGen/MIR/X86/basic-block-liveins.mir | 24 +- .../X86/basic-block-not-at-start-of-line-error.mir | 18 +- test/CodeGen/MIR/X86/block-address-operands.mir | 40 +- test/CodeGen/MIR/X86/branch-probabilities.mir | 4 +- test/CodeGen/MIR/X86/callee-saved-info.mir | 48 +- test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir | 4 +- test/CodeGen/MIR/X86/cfi-def-cfa-register.mir | 12 +- test/CodeGen/MIR/X86/cfi-offset.mir | 26 +- test/CodeGen/MIR/X86/constant-pool.mir | 52 +- test/CodeGen/MIR/X86/dead-register-flag.mir | 6 +- .../MIR/X86/def-register-already-tied-error.mir | 10 +- test/CodeGen/MIR/X86/diexpr-win32.mir | 44 +- .../MIR/X86/duplicate-memory-operand-flag.mir | 12 +- .../MIR/X86/duplicate-register-flag-error.mir | 12 +- .../MIR/X86/early-clobber-register-flag.mir | 22 +- .../MIR/X86/expected-align-in-memory-operand.mir | 16 +- ...ted-alignment-after-align-in-memory-operand.mir | 16 +- .../X86/expected-basic-block-at-start-of-body.mir | 18 +- .../expected-block-reference-in-blockaddress.mir | 6 +- .../MIR/X86/expected-comma-after-cfi-register.mir | 22 +- .../X86/expected-comma-after-memory-operand.mir | 6 +- .../X86/expected-different-implicit-operand.mir | 10 +- .../expected-different-implicit-register-flag.mir | 10 +- ...ected-function-reference-after-blockaddress.mir | 6 +- .../expected-global-value-after-blockaddress.mir | 6 +- .../MIR/X86/expected-integer-after-offset-sign.mir | 8 +- .../MIR/X86/expected-integer-after-tied-def.mir | 10 +- .../X86/expected-integer-in-successor-weight.mir | 16 +- .../expected-load-or-store-in-memory-operand.mir | 8 +- test/CodeGen/MIR/X86/expected-machine-operand.mir | 4 +- ...expected-metadata-node-after-debug-location.mir | 8 +- .../X86/expected-metadata-node-after-exclaim.mir | 6 +- .../X86/expected-metadata-node-in-stack-object.mir | 10 +- .../expected-named-register-in-allocation-hint.mir | 16 +- ...ted-named-register-in-callee-saved-register.mir | 40 +- .../MIR/X86/expected-named-register-livein.mir | 4 +- .../MIR/X86/expected-newline-at-end-of-list.mir | 18 +- test/CodeGen/MIR/X86/expected-number-after-bb.mir | 10 +- .../MIR/X86/expected-offset-after-cfi-operand.mir | 4 +- .../expected-pointer-value-in-memory-operand.mir | 8 +- .../expected-positive-alignment-after-align.mir | 16 +- .../X86/expected-register-after-cfi-operand.mir | 20 +- .../MIR/X86/expected-register-after-flags.mir | 4 +- ...xpected-size-integer-after-memory-operation.mir | 8 +- test/CodeGen/MIR/X86/expected-stack-object.mir | 30 +- .../MIR/X86/expected-subregister-after-colon.mir | 8 +- test/CodeGen/MIR/X86/expected-target-flag-name.mir | 8 +- .../MIR/X86/expected-tied-def-after-lparen.mir | 10 +- .../MIR/X86/expected-value-in-memory-operand.mir | 8 +- ...pected-virtual-register-in-functions-livein.mir | 10 +- test/CodeGen/MIR/X86/external-symbol-operands.mir | 34 +- .../MIR/X86/fixed-stack-memory-operands.mir | 12 +- .../X86/fixed-stack-object-redefinition-error.mir | 6 +- test/CodeGen/MIR/X86/fixed-stack-objects.mir | 6 +- .../MIR/X86/frame-info-save-restore-points.mir | 32 +- .../MIR/X86/frame-info-stack-references.mir | 36 +- .../MIR/X86/frame-setup-instruction-flag.mir | 16 +- test/CodeGen/MIR/X86/function-liveins.mir | 20 +- test/CodeGen/MIR/X86/generic-instr-type.mir | 8 +- test/CodeGen/MIR/X86/global-value-operands.mir | 72 +- test/CodeGen/MIR/X86/immediate-operands.mir | 16 +- test/CodeGen/MIR/X86/implicit-register-flag.mir | 30 +- test/CodeGen/MIR/X86/inline-asm-registers.mir | 28 +- .../MIR/X86/instructions-debug-location.mir | 28 +- .../CodeGen/MIR/X86/invalid-constant-pool-item.mir | 4 +- test/CodeGen/MIR/X86/invalid-target-flag-name.mir | 8 +- .../MIR/X86/invalid-tied-def-index-error.mir | 10 +- test/CodeGen/MIR/X86/jump-table-info.mir | 72 +- .../MIR/X86/jump-table-redefinition-error.mir | 34 +- test/CodeGen/MIR/X86/killed-register-flag.mir | 20 +- .../MIR/X86/large-cfi-offset-number-error.mir | 4 +- .../MIR/X86/large-immediate-operand-error.mir | 4 +- test/CodeGen/MIR/X86/large-index-number-error.mir | 10 +- test/CodeGen/MIR/X86/large-offset-number-error.mir | 8 +- .../MIR/X86/large-size-in-memory-operand-error.mir | 8 +- test/CodeGen/MIR/X86/liveout-register-mask.mir | 20 +- .../MIR/X86/machine-basic-block-operands.mir | 24 +- test/CodeGen/MIR/X86/machine-instructions.mir | 4 +- test/CodeGen/MIR/X86/machine-verifier.mir | 2 +- test/CodeGen/MIR/X86/memory-operands.mir | 282 +- test/CodeGen/MIR/X86/metadata-operands.mir | 12 +- test/CodeGen/MIR/X86/missing-closing-quote.mir | 6 +- test/CodeGen/MIR/X86/missing-comma.mir | 4 +- test/CodeGen/MIR/X86/missing-implicit-operand.mir | 8 +- test/CodeGen/MIR/X86/named-registers.mir | 8 +- test/CodeGen/MIR/X86/newline-handling.mir | 70 +- test/CodeGen/MIR/X86/null-register-operands.mir | 8 +- test/CodeGen/MIR/X86/register-mask-operands.mir | 16 +- .../MIR/X86/register-operand-class-invalid0.mir | 2 +- .../MIR/X86/register-operand-class-invalid1.mir | 2 +- test/CodeGen/MIR/X86/register-operand-class.mir | 16 +- .../X86/register-operands-target-flag-error.mir | 8 +- test/CodeGen/MIR/X86/renamable-register-flag.mir | 6 +- test/CodeGen/MIR/X86/roundtrip.mir | 12 +- .../MIR/X86/simple-register-allocation-hints.mir | 20 +- .../MIR/X86/spill-slot-fixed-stack-objects.mir | 6 +- test/CodeGen/MIR/X86/stack-object-invalid-name.mir | 6 +- .../stack-object-operand-name-mismatch-error.mir | 6 +- test/CodeGen/MIR/X86/stack-object-operands.mir | 16 +- .../MIR/X86/stack-object-redefinition-error.mir | 12 +- test/CodeGen/MIR/X86/stack-objects.mir | 8 +- test/CodeGen/MIR/X86/standalone-register-error.mir | 10 +- test/CodeGen/MIR/X86/subreg-on-physreg.mir | 2 +- .../CodeGen/MIR/X86/subregister-index-operands.mir | 20 +- test/CodeGen/MIR/X86/subregister-operands.mir | 20 +- .../MIR/X86/successor-basic-blocks-weights.mir | 16 +- test/CodeGen/MIR/X86/successor-basic-blocks.mir | 34 +- test/CodeGen/MIR/X86/tied-def-operand-invalid.mir | 10 +- test/CodeGen/MIR/X86/tied-physical-regs-match.mir | 6 +- test/CodeGen/MIR/X86/undef-register-flag.mir | 14 +- .../MIR/X86/undefined-fixed-stack-object.mir | 4 +- test/CodeGen/MIR/X86/undefined-global-value.mir | 8 +- .../MIR/X86/undefined-ir-block-in-blockaddress.mir | 6 +- .../undefined-ir-block-slot-in-blockaddress.mir | 6 +- test/CodeGen/MIR/X86/undefined-jump-table-id.mir | 34 +- .../MIR/X86/undefined-named-global-value.mir | 8 +- test/CodeGen/MIR/X86/undefined-stack-object.mir | 6 +- .../MIR/X86/undefined-value-in-memory-operand.mir | 8 +- .../CodeGen/MIR/X86/undefined-virtual-register.mir | 6 +- test/CodeGen/MIR/X86/unexpected-type-phys.mir | 4 +- .../MIR/X86/unknown-machine-basic-block.mir | 10 +- test/CodeGen/MIR/X86/unknown-metadata-keyword.mir | 12 +- test/CodeGen/MIR/X86/unknown-metadata-node.mir | 6 +- .../MIR/X86/unknown-named-machine-basic-block.mir | 10 +- test/CodeGen/MIR/X86/unknown-register.mir | 4 +- .../MIR/X86/unknown-subregister-index-op.mir | 2 +- test/CodeGen/MIR/X86/unknown-subregister-index.mir | 8 +- .../MIR/X86/variable-sized-stack-objects.mir | 8 +- test/CodeGen/MIR/X86/virtual-registers.mir | 46 +- .../compact-branch-implicit-def.mir | 98 +- test/CodeGen/Mips/compactbranches/empty-block.mir | 24 +- test/CodeGen/Mips/instverify/dext-pos.mir | 10 +- test/CodeGen/Mips/instverify/dext-size.mir | 10 +- test/CodeGen/Mips/instverify/dextm-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dextm-pos.mir | 10 +- test/CodeGen/Mips/instverify/dextm-size.mir | 10 +- test/CodeGen/Mips/instverify/dextu-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dextu-pos.mir | 10 +- test/CodeGen/Mips/instverify/dextu-size-valid.mir | 10 +- test/CodeGen/Mips/instverify/dextu-size.mir | 10 +- test/CodeGen/Mips/instverify/dins-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dins-pos.mir | 10 +- test/CodeGen/Mips/instverify/dins-size.mir | 10 +- test/CodeGen/Mips/instverify/dinsm-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dinsm-pos.mir | 10 +- test/CodeGen/Mips/instverify/dinsm-size.mir | 10 +- test/CodeGen/Mips/instverify/dinsu-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/dinsu-pos.mir | 10 +- test/CodeGen/Mips/instverify/dinsu-size.mir | 10 +- test/CodeGen/Mips/instverify/ext-pos-size.mir | 10 +- test/CodeGen/Mips/instverify/ext-pos.mir | 10 +- test/CodeGen/Mips/instverify/ext-size.mir | 10 +- test/CodeGen/Mips/instverify/ins-pos-size.mir | 14 +- test/CodeGen/Mips/instverify/ins-pos.mir | 14 +- test/CodeGen/Mips/instverify/ins-size.mir | 14 +- test/CodeGen/Mips/llvm-ir/call.ll | 4 +- .../Mips/mirparser/target-flags-pic-mxgot-tls.mir | 120 +- .../Mips/mirparser/target-flags-pic-o32.mir | 28 +- test/CodeGen/Mips/mirparser/target-flags-pic.mir | 26 +- .../Mips/mirparser/target-flags-static-tls.mir | 78 +- test/CodeGen/Mips/msa/emergency-spill.mir | 180 +- test/CodeGen/Mips/sll-micromips-r6-encoding.mir | 6 +- test/CodeGen/PowerPC/aantidep-def-ec.mir | 52 +- test/CodeGen/PowerPC/addegluecrash.ll | 2 +- test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 52 +- .../PowerPC/aggressive-anti-dep-breaker-subreg.ll | 2 +- test/CodeGen/PowerPC/byval-agg-info.ll | 2 +- ...convert-rr-to-ri-instrs-R0-special-handling.mir | 110 +- .../convert-rr-to-ri-instrs-out-of-range.mir | 340 +- test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir | 1344 +-- test/CodeGen/PowerPC/debuginfo-split-int.ll | 8 +- test/CodeGen/PowerPC/debuginfo-stackarg.ll | 2 +- test/CodeGen/PowerPC/expand-isel-1.mir | 18 +- test/CodeGen/PowerPC/expand-isel-10.mir | 20 +- test/CodeGen/PowerPC/expand-isel-2.mir | 22 +- test/CodeGen/PowerPC/expand-isel-3.mir | 22 +- test/CodeGen/PowerPC/expand-isel-4.mir | 24 +- test/CodeGen/PowerPC/expand-isel-5.mir | 18 +- test/CodeGen/PowerPC/expand-isel-6.mir | 18 +- test/CodeGen/PowerPC/expand-isel-7.mir | 22 +- test/CodeGen/PowerPC/expand-isel-8.mir | 36 +- test/CodeGen/PowerPC/expand-isel-9.mir | 16 +- test/CodeGen/PowerPC/fp64-to-int16.ll | 2 +- test/CodeGen/PowerPC/livephysregs.mir | 54 +- test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 8 +- test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 14 +- test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 26 +- test/CodeGen/PowerPC/quadint-return.ll | 4 +- test/CodeGen/PowerPC/scavenging.mir | 264 +- test/CodeGen/PowerPC/tls_get_addr_fence1.mir | 18 +- test/CodeGen/PowerPC/tls_get_addr_fence2.mir | 16 +- test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir | 90 +- test/CodeGen/SystemZ/clear-liverange-spillreg.mir | 212 +- test/CodeGen/SystemZ/cond-move-04.mir | 12 +- test/CodeGen/SystemZ/cond-move-05.mir | 8 +- test/CodeGen/SystemZ/fp-cmp-07.mir | 20 +- test/CodeGen/SystemZ/fp-conv-17.mir | 112 +- test/CodeGen/SystemZ/load-and-test.mir | 32 +- test/CodeGen/SystemZ/lower-copy-undef-src.mir | 6 +- test/CodeGen/SystemZ/pr32505.ll | 4 +- .../SystemZ/regalloc-fast-invalid-kill-flag.mir | 10 +- test/CodeGen/SystemZ/store_nonbytesized_vecs.ll | 2 +- test/CodeGen/Thumb/machine-cse-physreg.mir | 24 +- test/CodeGen/Thumb/tbb-reuse.mir | 82 +- test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir | 32 +- test/CodeGen/Thumb2/t2sizereduction.mir | 52 +- test/CodeGen/Thumb2/tbb-removeadd.mir | 46 +- test/CodeGen/X86/2006-11-17-IllegalMove.ll | 2 +- test/CodeGen/X86/2010-05-28-Crash.ll | 2 +- test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll | 2 +- test/CodeGen/X86/3addr-or.ll | 8 +- test/CodeGen/X86/GlobalISel/add-scalar.ll | 10 +- test/CodeGen/X86/GlobalISel/ext-x86-64.ll | 2 +- test/CodeGen/X86/GlobalISel/ext.ll | 4 +- test/CodeGen/X86/GlobalISel/gep.ll | 4 +- .../X86/GlobalISel/irtranslator-callingconv.ll | 450 +- test/CodeGen/X86/GlobalISel/legalize-add-v128.mir | 24 +- test/CodeGen/X86/GlobalISel/legalize-add-v256.mir | 40 +- test/CodeGen/X86/GlobalISel/legalize-add-v512.mir | 78 +- test/CodeGen/X86/GlobalISel/legalize-add.mir | 26 +- .../CodeGen/X86/GlobalISel/legalize-and-scalar.mir | 40 +- test/CodeGen/X86/GlobalISel/legalize-brcond.mir | 20 +- test/CodeGen/X86/GlobalISel/legalize-cmp.mir | 90 +- test/CodeGen/X86/GlobalISel/legalize-constant.mir | 42 +- .../CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir | 168 +- test/CodeGen/X86/GlobalISel/legalize-ext.mir | 342 +- .../X86/GlobalISel/legalize-fadd-scalar.mir | 36 +- .../X86/GlobalISel/legalize-fdiv-scalar.mir | 36 +- .../X86/GlobalISel/legalize-fmul-scalar.mir | 36 +- .../X86/GlobalISel/legalize-fpext-scalar.mir | 14 +- .../X86/GlobalISel/legalize-fsub-scalar.mir | 36 +- .../X86/GlobalISel/legalize-insert-vec256.mir | 18 +- .../X86/GlobalISel/legalize-insert-vec512.mir | 36 +- .../X86/GlobalISel/legalize-memop-scalar.mir | 4 +- .../CodeGen/X86/GlobalISel/legalize-mul-scalar.mir | 58 +- test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir | 54 +- test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir | 54 +- test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir | 54 +- test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir | 36 +- test/CodeGen/X86/GlobalISel/legalize-phi.mir | 168 +- test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir | 16 +- test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir | 16 +- test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir | 16 +- test/CodeGen/X86/GlobalISel/legalize-sub.mir | 24 +- .../CodeGen/X86/GlobalISel/legalize-xor-scalar.mir | 36 +- test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir | 14 +- .../X86/GlobalISel/regbankselect-AVX512.mir | 14 +- .../X86/GlobalISel/regbankselect-X86_64.mir | 804 +- test/CodeGen/X86/GlobalISel/select-GV.mir | 54 +- test/CodeGen/X86/GlobalISel/select-add-v128.mir | 40 +- test/CodeGen/X86/GlobalISel/select-add-v256.mir | 40 +- test/CodeGen/X86/GlobalISel/select-add-v512.mir | 72 +- test/CodeGen/X86/GlobalISel/select-add-x32.mir | 22 +- test/CodeGen/X86/GlobalISel/select-add.mir | 100 +- test/CodeGen/X86/GlobalISel/select-and-scalar.mir | 80 +- test/CodeGen/X86/GlobalISel/select-blsi.mir | 28 +- test/CodeGen/X86/GlobalISel/select-blsr.mir | 26 +- test/CodeGen/X86/GlobalISel/select-brcond.mir | 30 +- test/CodeGen/X86/GlobalISel/select-cmp.mir | 312 +- test/CodeGen/X86/GlobalISel/select-constant.mir | 66 +- test/CodeGen/X86/GlobalISel/select-copy.mir | 84 +- test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir | 100 +- test/CodeGen/X86/GlobalISel/select-ext.mir | 204 +- .../X86/GlobalISel/select-extract-vec256.mir | 36 +- .../X86/GlobalISel/select-extract-vec512.mir | 56 +- test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir | 84 +- test/CodeGen/X86/GlobalISel/select-fconstant.mir | 68 +- test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir | 84 +- test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir | 84 +- .../CodeGen/X86/GlobalISel/select-fpext-scalar.mir | 14 +- test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir | 84 +- test/CodeGen/X86/GlobalISel/select-gep.mir | 16 +- test/CodeGen/X86/GlobalISel/select-inc.mir | 8 +- .../X86/GlobalISel/select-insert-vec256.mir | 92 +- .../X86/GlobalISel/select-insert-vec512.mir | 128 +- .../select-intrinsic-x86-flags-read-u32.mir | 6 +- .../X86/GlobalISel/select-leaf-constant.mir | 36 +- .../X86/GlobalISel/select-memop-scalar-x32.mir | 96 +- .../CodeGen/X86/GlobalISel/select-memop-scalar.mir | 816 +- test/CodeGen/X86/GlobalISel/select-memop-v128.mir | 92 +- test/CodeGen/X86/GlobalISel/select-memop-v256.mir | 112 +- test/CodeGen/X86/GlobalISel/select-memop-v512.mir | 56 +- .../CodeGen/X86/GlobalISel/select-merge-vec256.mir | 12 +- .../CodeGen/X86/GlobalISel/select-merge-vec512.mir | 16 +- test/CodeGen/X86/GlobalISel/select-mul-scalar.mir | 60 +- test/CodeGen/X86/GlobalISel/select-mul-vec.mir | 270 +- test/CodeGen/X86/GlobalISel/select-or-scalar.mir | 80 +- test/CodeGen/X86/GlobalISel/select-phi.mir | 168 +- test/CodeGen/X86/GlobalISel/select-sub-v128.mir | 40 +- test/CodeGen/X86/GlobalISel/select-sub-v256.mir | 40 +- test/CodeGen/X86/GlobalISel/select-sub-v512.mir | 72 +- test/CodeGen/X86/GlobalISel/select-sub.mir | 60 +- test/CodeGen/X86/GlobalISel/select-trunc.mir | 84 +- test/CodeGen/X86/GlobalISel/select-undef.mir | 24 +- .../X86/GlobalISel/select-unmerge-vec256.mir | 18 +- .../X86/GlobalISel/select-unmerge-vec512.mir | 16 +- test/CodeGen/X86/GlobalISel/select-xor-scalar.mir | 80 +- .../X86/GlobalISel/x32-select-frameIndex.mir | 10 +- test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir | 8 +- .../X86/GlobalISel/x86-select-frameIndex.mir | 10 +- test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir | 8 +- .../X86/GlobalISel/x86_64-select-frameIndex.mir | 10 +- test/CodeGen/X86/add-i64.ll | 2 +- test/CodeGen/X86/add-sub-nsw-nuw.ll | 2 +- test/CodeGen/X86/add.ll | 4 +- test/CodeGen/X86/addcarry.ll | 2 +- test/CodeGen/X86/and-encoding.ll | 2 +- test/CodeGen/X86/anyext.ll | 8 +- test/CodeGen/X86/atomic-eflags-reuse.ll | 2 +- test/CodeGen/X86/avx-cast.ll | 12 +- test/CodeGen/X86/avx-cmp.ll | 2 +- test/CodeGen/X86/avx-insertelt.ll | 4 +- test/CodeGen/X86/avx-intrinsics-fast-isel.ll | 56 +- test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll | 4 +- test/CodeGen/X86/avx-load-store.ll | 26 +- test/CodeGen/X86/avx-splat.ll | 2 +- test/CodeGen/X86/avx-vinsertf128.ll | 6 +- test/CodeGen/X86/avx-vzeroupper.ll | 12 +- test/CodeGen/X86/avx2-conversions.ll | 12 +- test/CodeGen/X86/avx2-intrinsics-fast-isel.ll | 4 +- test/CodeGen/X86/avx2-masked-gather.ll | 24 +- test/CodeGen/X86/avx2-shift.ll | 8 +- test/CodeGen/X86/avx2-vector-shifts.ll | 8 +- test/CodeGen/X86/avx512-arith.ll | 24 +- test/CodeGen/X86/avx512-build-vector.ll | 2 +- test/CodeGen/X86/avx512-calling-conv.ll | 14 +- test/CodeGen/X86/avx512-cmp-kor-sequence.ll | 2 +- test/CodeGen/X86/avx512-cvt.ll | 152 +- test/CodeGen/X86/avx512-ext.ll | 64 +- test/CodeGen/X86/avx512-extract-subvector.ll | 4 +- test/CodeGen/X86/avx512-hadd-hsub.ll | 20 +- test/CodeGen/X86/avx512-insert-extract.ll | 144 +- test/CodeGen/X86/avx512-insert-extract_i1.ll | 2 +- test/CodeGen/X86/avx512-intrinsics-upgrade.ll | 38 +- test/CodeGen/X86/avx512-intrinsics.ll | 24 +- test/CodeGen/X86/avx512-mask-op.ll | 188 +- test/CodeGen/X86/avx512-memfold.ll | 2 +- test/CodeGen/X86/avx512-regcall-Mask.ll | 78 +- test/CodeGen/X86/avx512-regcall-NoMask.ll | 30 +- test/CodeGen/X86/avx512-schedule.ll | 64 +- test/CodeGen/X86/avx512-select.ll | 12 +- test/CodeGen/X86/avx512-shift.ll | 10 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 10 +- test/CodeGen/X86/avx512-trunc.ll | 30 +- test/CodeGen/X86/avx512-vbroadcast.ll | 8 +- test/CodeGen/X86/avx512-vec-cmp.ll | 106 +- test/CodeGen/X86/avx512-vec3-crash.ll | 6 +- test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll | 16 +- test/CodeGen/X86/avx512bw-mov.ll | 16 +- test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll | 42 +- test/CodeGen/X86/avx512bwvl-vec-test-testn.ll | 24 +- test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll | 16 +- test/CodeGen/X86/avx512dq-intrinsics.ll | 12 +- test/CodeGen/X86/avx512dq-mask-op.ll | 4 +- test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll | 16 +- test/CodeGen/X86/avx512dqvl-intrinsics.ll | 8 +- test/CodeGen/X86/avx512f-vec-test-testn.ll | 16 +- test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 52 +- test/CodeGen/X86/avx512vl-intrinsics.ll | 8 +- test/CodeGen/X86/avx512vl-vec-cmp.ll | 338 +- test/CodeGen/X86/avx512vl-vec-masked-cmp.ll | 2318 ++--- test/CodeGen/X86/avx512vl-vec-test-testn.ll | 64 +- test/CodeGen/X86/bitcast-and-setcc-128.ll | 102 +- test/CodeGen/X86/bitcast-and-setcc-256.ll | 46 +- test/CodeGen/X86/bitcast-and-setcc-512.ll | 36 +- .../CodeGen/X86/bitcast-int-to-vector-bool-sext.ll | 18 +- .../CodeGen/X86/bitcast-int-to-vector-bool-zext.ll | 28 +- test/CodeGen/X86/bitcast-int-to-vector-bool.ll | 6 +- test/CodeGen/X86/bitcast-int-to-vector.ll | 2 +- test/CodeGen/X86/bitcast-setcc-128.ll | 102 +- test/CodeGen/X86/bitcast-setcc-256.ll | 46 +- test/CodeGen/X86/bitcast-setcc-512.ll | 40 +- test/CodeGen/X86/bitreverse.ll | 14 +- test/CodeGen/X86/block-placement.mir | 32 +- test/CodeGen/X86/bmi-schedule.ll | 24 +- test/CodeGen/X86/bmi.ll | 22 +- test/CodeGen/X86/bool-simplify.ll | 4 +- test/CodeGen/X86/bool-vector.ll | 8 +- test/CodeGen/X86/branchfolding-undef.mir | 14 +- test/CodeGen/X86/broadcastm-lowering.ll | 8 +- test/CodeGen/X86/bypass-slow-division-32.ll | 14 +- test/CodeGen/X86/bypass-slow-division-64.ll | 8 +- test/CodeGen/X86/clz.ll | 68 +- test/CodeGen/X86/cmov-into-branch.ll | 2 +- test/CodeGen/X86/cmov-promotion.ll | 8 +- test/CodeGen/X86/cmov.ll | 2 +- test/CodeGen/X86/combine-abs.ll | 4 +- test/CodeGen/X86/compress_expand.ll | 22 +- test/CodeGen/X86/conditional-tailcall-samedest.mir | 30 +- test/CodeGen/X86/critical-edge-split-2.ll | 2 +- test/CodeGen/X86/ctpop-combine.ll | 2 +- test/CodeGen/X86/dagcombine-cse.ll | 4 +- test/CodeGen/X86/divide-by-constant.ll | 34 +- test/CodeGen/X86/divrem.ll | 4 +- test/CodeGen/X86/divrem8_ext.ll | 36 +- test/CodeGen/X86/domain-reassignment.mir | 274 +- test/CodeGen/X86/dynamic-regmask.ll | 12 +- test/CodeGen/X86/eflags-copy-expansion.mir | 22 +- test/CodeGen/X86/evex-to-vex-compress.mir | 9132 ++++++++++---------- test/CodeGen/X86/expand-vr64-gr64-copy.mir | 24 +- test/CodeGen/X86/extractelement-index.ll | 50 +- test/CodeGen/X86/f16c-intrinsics-fast-isel.ll | 4 +- test/CodeGen/X86/fast-isel-cmp.ll | 8 +- test/CodeGen/X86/fast-isel-nontemporal.ll | 36 +- test/CodeGen/X86/fast-isel-sext-zext.ll | 16 +- test/CodeGen/X86/fast-isel-shift.ll | 24 +- test/CodeGen/X86/fixup-bw-copy.ll | 2 +- test/CodeGen/X86/fixup-bw-copy.mir | 70 +- test/CodeGen/X86/fixup-bw-inst.mir | 74 +- test/CodeGen/X86/gpr-to-mask.ll | 40 +- .../X86/greedy_regalloc_bad_eviction_sequence.ll | 14 +- test/CodeGen/X86/half.ll | 2 +- test/CodeGen/X86/horizontal-reduce-smax.ll | 96 +- test/CodeGen/X86/horizontal-reduce-smin.ll | 96 +- test/CodeGen/X86/horizontal-reduce-umax.ll | 104 +- test/CodeGen/X86/horizontal-reduce-umin.ll | 96 +- test/CodeGen/X86/iabs.ll | 2 +- test/CodeGen/X86/illegal-bitfield-loadstore.ll | 6 +- test/CodeGen/X86/implicit-null-checks.mir | 748 +- test/CodeGen/X86/implicit-use-spill.mir | 4 +- test/CodeGen/X86/imul.ll | 4 +- test/CodeGen/X86/invalid-liveness.mir | 6 +- test/CodeGen/X86/ipra-inline-asm.ll | 2 +- test/CodeGen/X86/ipra-reg-alias.ll | 2 +- test/CodeGen/X86/ipra-reg-usage.ll | 2 +- test/CodeGen/X86/lea-3.ll | 8 +- test/CodeGen/X86/lea-opt-cse3.ll | 16 +- test/CodeGen/X86/lea-opt-with-debug.mir | 30 +- test/CodeGen/X86/lea32-schedule.ll | 306 +- test/CodeGen/X86/leaFixup32.mir | 182 +- test/CodeGen/X86/leaFixup64.mir | 372 +- test/CodeGen/X86/loop-search.ll | 6 +- test/CodeGen/X86/lzcnt-schedule.ll | 12 +- test/CodeGen/X86/lzcnt-zext-cmp.ll | 6 +- test/CodeGen/X86/machine-combiner-int.ll | 4 +- test/CodeGen/X86/machine-copy-prop.mir | 192 +- test/CodeGen/X86/machine-cse.ll | 6 +- test/CodeGen/X86/machine-region-info.mir | 28 +- test/CodeGen/X86/masked_gather_scatter.ll | 110 +- test/CodeGen/X86/masked_memop.ll | 100 +- test/CodeGen/X86/misched-copy.ll | 8 +- test/CodeGen/X86/movmsk.ll | 2 +- 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test/CodeGen/X86/select_const.ll | 12 +- test/CodeGen/X86/setcc-lowering.ll | 4 +- test/CodeGen/X86/sext-i1.ll | 4 +- test/CodeGen/X86/shift-combine.ll | 8 +- test/CodeGen/X86/shift-double.ll | 4 +- test/CodeGen/X86/shrink-compare.ll | 4 +- test/CodeGen/X86/shrink_wrap_dbg_value.mir | 50 +- test/CodeGen/X86/shuffle-vs-trunc-256.ll | 12 +- .../X86/simple-register-allocation-read-undef.mir | 2 +- test/CodeGen/X86/sqrt-fastmath-mir.ll | 12 +- test/CodeGen/X86/sse2-schedule.ll | 20 +- test/CodeGen/X86/sse42-schedule.ll | 36 +- test/CodeGen/X86/subvector-broadcast.ll | 112 +- test/CodeGen/X86/swift-return.ll | 4 +- test/CodeGen/X86/switch-lower-peel-top-case.ll | 58 +- test/CodeGen/X86/tail-call-conditional.mir | 52 +- test/CodeGen/X86/tail-dup-debugloc.ll | 2 +- test/CodeGen/X86/tail-merge-after-mbp.mir | 60 +- test/CodeGen/X86/tail-merge-debugloc.ll | 2 +- test/CodeGen/X86/tbm-intrinsics-fast-isel.ll | 8 +- test/CodeGen/X86/tbm_patterns.ll | 10 +- test/CodeGen/X86/trunc-subvector.ll | 20 +- test/CodeGen/X86/umul-with-overflow.ll | 6 +- test/CodeGen/X86/unreachable-mbb-undef-phi.mir | 2 +- test/CodeGen/X86/update-terminator-debugloc.ll | 4 +- test/CodeGen/X86/update-terminator.mir | 22 +- test/CodeGen/X86/urem-i8-constant.ll | 2 +- test/CodeGen/X86/urem-power-of-two.ll | 12 +- test/CodeGen/X86/var-permute-256.ll | 16 +- test/CodeGen/X86/vec_cmp_sint-128.ll | 24 +- test/CodeGen/X86/vec_cmp_uint-128.ll | 16 +- test/CodeGen/X86/vec_fp_to_int.ll | 102 +- test/CodeGen/X86/vec_ins_extract-1.ll | 8 +- test/CodeGen/X86/vec_insert-4.ll | 2 +- test/CodeGen/X86/vec_insert-5.ll | 2 +- test/CodeGen/X86/vec_insert-8.ll | 4 +- test/CodeGen/X86/vec_insert-mmx.ll | 2 +- test/CodeGen/X86/vec_int_to_fp.ll | 186 +- test/CodeGen/X86/vec_minmax_sint.ll | 48 +- test/CodeGen/X86/vec_minmax_uint.ll | 48 +- test/CodeGen/X86/vec_ss_load_fold.ll | 20 +- test/CodeGen/X86/vector-bitreverse.ll | 16 +- test/CodeGen/X86/vector-compare-all_of.ll | 36 +- test/CodeGen/X86/vector-compare-any_of.ll | 36 +- test/CodeGen/X86/vector-compare-results.ll | 48 +- test/CodeGen/X86/vector-extend-inreg.ll | 4 +- test/CodeGen/X86/vector-half-conversions.ll | 118 +- test/CodeGen/X86/vector-lzcnt-128.ll | 16 +- test/CodeGen/X86/vector-lzcnt-256.ll | 16 +- test/CodeGen/X86/vector-popcnt-128.ll | 18 +- test/CodeGen/X86/vector-popcnt-256.ll | 16 +- test/CodeGen/X86/vector-rotate-128.ll | 38 +- test/CodeGen/X86/vector-rotate-256.ll | 38 +- test/CodeGen/X86/vector-sext.ll | 28 +- test/CodeGen/X86/vector-shift-ashr-128.ll | 38 +- test/CodeGen/X86/vector-shift-ashr-256.ll | 28 +- test/CodeGen/X86/vector-shift-lshr-128.ll | 24 +- test/CodeGen/X86/vector-shift-lshr-256.ll | 10 +- test/CodeGen/X86/vector-shift-shl-128.ll | 20 +- test/CodeGen/X86/vector-shift-shl-256.ll | 10 +- test/CodeGen/X86/vector-shuffle-256-v4.ll | 6 +- test/CodeGen/X86/vector-shuffle-512-v16.ll | 4 +- test/CodeGen/X86/vector-shuffle-512-v8.ll | 12 +- test/CodeGen/X86/vector-shuffle-avx512.ll | 84 +- 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test/CodeGen/X86/xor-combine-debugloc.ll | 10 +- test/CodeGen/X86/xray-empty-firstmbb.mir | 4 +- test/CodeGen/X86/xray-empty-function.mir | 2 +- test/CodeGen/X86/xray-multiplerets-in-blocks.mir | 4 +- test/CodeGen/X86/zext-demanded.ll | 8 +- test/DebugInfo/ARM/PR16736.ll | 2 +- test/DebugInfo/ARM/sdag-split-arg.ll | 4 +- test/DebugInfo/ARM/sdag-split-arg1.ll | 2 +- test/DebugInfo/COFF/fpo-csrs.ll | 20 +- test/DebugInfo/COFF/local-variable-gap.ll | 6 +- test/DebugInfo/COFF/pieces.ll | 18 +- test/DebugInfo/COFF/register-variables.ll | 22 +- test/DebugInfo/MIR/AArch64/clobber-sp.mir | 60 +- .../MIR/AArch64/implicit-def-dead-scope.mir | 78 +- test/DebugInfo/MIR/ARM/split-superreg-complex.mir | 52 +- test/DebugInfo/MIR/ARM/split-superreg-piece.mir | 52 +- test/DebugInfo/MIR/ARM/split-superreg.mir | 52 +- test/DebugInfo/MIR/Mips/last-inst-bundled.mir | 48 +- test/DebugInfo/MIR/X86/bit-piece-dh.mir | 22 +- test/DebugInfo/MIR/X86/empty-inline.mir | 26 +- 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test/DebugInfo/X86/live-debug-vars-dse.mir | 28 +- test/DebugInfo/X86/op_deref.ll | 2 +- test/DebugInfo/X86/pieces-4.ll | 2 +- test/DebugInfo/X86/pr34545.ll | 18 +- test/DebugInfo/X86/sdag-combine.ll | 2 +- test/DebugInfo/X86/sdag-salvage-add.ll | 6 +- test/DebugInfo/X86/sdag-split-arg.ll | 10 +- test/DebugInfo/X86/sdagsplit-1.ll | 4 +- test/DebugInfo/X86/spill-indirect-nrvo.ll | 4 +- test/DebugInfo/X86/spill-nontrivial-param.ll | 4 +- test/DebugInfo/X86/spill-nospill.ll | 6 +- test/DebugInfo/X86/vla.ll | 2 +- .../LoopStrengthReduce/X86/ivchain-X86.ll | 4 +- test/Verifier/test_g_phi.mir | 8 +- unittests/CodeGen/GlobalISel/PatternMatchTest.cpp | 6 +- unittests/CodeGen/MachineInstrTest.cpp | 2 +- unittests/CodeGen/MachineOperandTest.cpp | 2 +- unittests/MI/LiveIntervalTest.cpp | 12 +- 970 files changed, 29359 insertions(+), 29350 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[clang] branch master updated (5762b182a1 -> 253065ecad)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from 5762b182a1 [clang-format] Align preprocessor comments with # new 253065ecad [PR32482] Fix bitfield layout for -mms-bitfield and pragma pack The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/AST/RecordLayoutBuilder.cpp | 7 ++++--- test/CodeGen/mms-bitfields.c | 43 +++++++++++++++++++++++++++++++++++++++++ test/Sema/mms-bitfields.c | 15 ++++++++++++++ 3 files changed, 62 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[clang-tools-extra] branch master updated (2fa4cfef -> ceea3284)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang-tools-extra. from 2fa4cfef [clangd] Add a test URI scheme for lit tests to unbreak platf [...] new ceea3284 [clang-tidy] New argument --language to add_new_check.py The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tidy/add_new_check.py | 49 ++++++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 16 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[libcxx] branch master updated (65c4c248c -> 37e4c9b15)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository libcxx. from 65c4c248c Add LWG3051 new 37e4c9b15 Implement LWG2870: Default value of parameter theta of polar [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/complex | 4 ++-- test/std/numerics/complex.number/complex.value.ops/polar.pass.cpp | 2 +- www/cxx2a_status.html | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[gcc] branch master updated (c0655a3ec04 -> 54540bdd479)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from c0655a3ec04 PR fortran/84116 * openmp.c (gfc_match_omp_clauses): If a [...] new 54540bdd479 PR rtl-optimization/84123 * combine.c (change_zero_ext): [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 6 ++++++ gcc/combine.c | 17 +++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[lldb] branch master updated (750addfeb -> 4360355fc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lldb. from 750addfeb Fix TestMixedDwarfBinary.py new 4360355fc replace os.mkdirs with lldbutil.mkdir_p (NFC) The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../lldbsuite/test/functionalities/process_launch/TestProcessLaunch.py | 3 +-- .../single-quote-in-filename-to-lldb/TestSingleQuoteInFilename.py | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (e4eed790f89 -> 42b2a1d5ed9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from e4eed790f89 [x86] Make the retpoline thunk insertion a machine function pass. new 42b2a1d5ed9 [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFC The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/Hexagon/HexagonISelLowering.cpp | 42 ++++++++--------- lib/Target/Hexagon/HexagonISelLowering.h | 4 +- lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 66 +++++++++++++-------------- 3 files changed, 56 insertions(+), 56 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (8e8c64faa1f -> e4eed790f89)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 8e8c64faa1f [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering new 2bd04d66a7c [SeparateConstOffsetFromGEP] Fix up addrspace in the AMDGPU test new f42f82fde05 [Hexagon] Implement HVX codegen for vector shifts new e4eed790f89 [x86] Make the retpoline thunk insertion a machine function pass. The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/Hexagon/HexagonISelLowering.cpp | 92 ++--- lib/Target/Hexagon/HexagonISelLowering.h | 1 + lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 6 + lib/Target/Hexagon/HexagonPatterns.td | 22 +- lib/Target/X86/X86.h | 2 +- lib/Target/X86/X86RetpolineThunks.cpp | 135 +++++--- test/CodeGen/Hexagon/autohvx/isel-build-undef.ll | 2 +- test/CodeGen/Hexagon/autohvx/shift-128b.ll | 376 +++++++++++++++++++++ test/CodeGen/Hexagon/autohvx/shift-64b.ll | 232 +++++++++++++ test/CodeGen/X86/O0-pipeline.ll | 3 +- ...split-gep-and-gvn-addrspace-addressing-modes.ll | 12 +- 11 files changed, 756 insertions(+), 127 deletions(-) create mode 100644 test/CodeGen/Hexagon/autohvx/shift-128b.ll create mode 100644 test/CodeGen/Hexagon/autohvx/shift-64b.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

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Tcwg-commits January 2018